From nobody Tue Apr 15 10:45:37 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518720029352956.2965250945142; Thu, 15 Feb 2018 10:40:29 -0800 (PST) Received: from localhost ([::1]:47639 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emOSI-0000OQ-H0 for importer@patchew.org; Thu, 15 Feb 2018 13:40:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36544) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emOPC-0006Gb-NO for qemu-devel@nongnu.org; Thu, 15 Feb 2018 13:37:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emOPB-0004IU-Ib for qemu-devel@nongnu.org; Thu, 15 Feb 2018 13:37:14 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46446) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1emOPB-0004H0-B5 for qemu-devel@nongnu.org; Thu, 15 Feb 2018 13:37:13 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1emOPA-00027X-4V for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:37:12 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 18:36:55 +0000 Message-Id: <20180215183700.26101-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180215183700.26101-1-peter.maydell@linaro.org> References: <20180215183700.26101-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/20] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 In many of the NVIC registers relating to interrupts, we have to convert from a byte offset within a register set into the number of the first interrupt which is affected. We were getting this wrong for: * reads of NVIC_ISPR, NVIC_ISER, NVIC_ICPR, NVIC_ICER, NVIC_IABR -- in all these cases we were missing the "* 8" needed to convert from the byte offset to the interrupt number (since all these registers use one bit per interrupt) * writes of NVIC_IPR had the opposite problem of a spurious "* 8" (since these registers use one byte per interrupt) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180209165810.6668-9-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index ea3b7cce14..c51151fa8a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1724,7 +1724,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwa= ddr addr, /* fall through */ case 0x180 ... 0x1bf: /* NVIC Clear enable */ val =3D 0; - startvec =3D offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */ + startvec =3D 8 * (offset - 0x180) + NVIC_FIRST_IRQ; /* vector # */ =20 for (i =3D 0, end =3D size * 8; i < end && startvec + i < s->num_i= rq; i++) { if (s->vectors[startvec + i].enabled && @@ -1738,7 +1738,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwa= ddr addr, /* fall through */ case 0x280 ... 0x2bf: /* NVIC Clear pend */ val =3D 0; - startvec =3D offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */ + startvec =3D 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ for (i =3D 0, end =3D size * 8; i < end && startvec + i < s->num_i= rq; i++) { if (s->vectors[startvec + i].pending && (attrs.secure || s->itns[startvec + i])) { @@ -1748,7 +1748,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwa= ddr addr, break; case 0x300 ... 0x33f: /* NVIC Active */ val =3D 0; - startvec =3D offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */ + startvec =3D 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */ =20 for (i =3D 0, end =3D size * 8; i < end && startvec + i < s->num_i= rq; i++) { if (s->vectors[startvec + i].active && @@ -1863,7 +1863,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hw= addr addr, case 0x300 ... 0x33f: /* NVIC Active */ return MEMTX_OK; /* R/O */ case 0x400 ... 0x5ef: /* NVIC Priority */ - startvec =3D 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ + startvec =3D (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ =20 for (i =3D 0; i < size && startvec + i < s->num_irq; i++) { if (attrs.secure || s->itns[startvec + i]) { --=20 2.16.1