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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Thu, 15 Feb 2018 18:36:54 +0000
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Subject: [Qemu-devel] [PULL 14/20] target/arm: Implement writing to
CONTROL_NS for v8M
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In commit 50f11062d4c896 we added support for MSR/MRS access
to the NS banked special registers, but we forgot to implement
the support for writing to CONTROL_NS. Correct the omission.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-8-peter.maydell@linaro.org
---
target/arm/helper.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 550dc3d290..1ae11997fb 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10507,6 +10507,16 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t ma=
skreg, uint32_t val)
}
env->v7m.faultmask[M_REG_NS] =3D val & 1;
return;
+ case 0x94: /* CONTROL_NS */
+ if (!env->v7m.secure) {
+ return;
+ }
+ write_v7m_control_spsel_for_secstate(env,
+ val & R_V7M_CONTROL_SPSEL=
_MASK,
+ M_REG_NS);
+ env->v7m.control[M_REG_NS] &=3D ~R_V7M_CONTROL_NPRIV_MASK;
+ env->v7m.control[M_REG_NS] |=3D val & R_V7M_CONTROL_NPRIV_MASK;
+ return;
case 0x98: /* SP_NS */
{
/* This gives the non-secure SP selected based on whether we're
--=20
2.16.1