From nobody Tue Apr 15 10:46:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151872051035381.99864602991113; Thu, 15 Feb 2018 10:48:30 -0800 (PST) Received: from localhost ([::1]:47931 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emOa5-0008Ga-Dp for importer@patchew.org; Thu, 15 Feb 2018 13:48:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36521) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emOPB-0006FI-BL for qemu-devel@nongnu.org; Thu, 15 Feb 2018 13:37:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emOPA-0004HL-8A for qemu-devel@nongnu.org; Thu, 15 Feb 2018 13:37:13 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46444) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1emOP9-0004Fo-WE for qemu-devel@nongnu.org; Thu, 15 Feb 2018 13:37:12 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1emOP8-000272-Mt for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:37:10 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 18:36:53 +0000 Message-Id: <20180215183700.26101-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180215183700.26101-1-peter.maydell@linaro.org> References: <20180215183700.26101-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/20] hw/intc/armv7m_nvic: Implement SCR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We were previously making the system control register (SCR) just RAZ/WI. Although we don't implement the functionality this register controls, we should at least provide the state, including the banked state for v8M. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180209165810.6668-7-peter.maydell@linaro.org --- target/arm/cpu.h | 7 +++++++ hw/intc/armv7m_nvic.c | 12 ++++++++---- target/arm/machine.c | 12 ++++++++++++ 3 files changed, 27 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8938a7c953..bc0638d3fa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -497,6 +497,7 @@ typedef struct CPUARMState { uint32_t aircr; /* only holds r/w state if security extn implement= ed */ uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ uint32_t csselr[M_REG_NUM_BANKS]; + uint32_t scr[M_REG_NUM_BANKS]; } v7m; =20 /* Information associated with an exception about to be taken: @@ -1258,6 +1259,12 @@ FIELD(V7M_CCR, STKALIGN, 9, 1) FIELD(V7M_CCR, DC, 16, 1) FIELD(V7M_CCR, IC, 17, 1) =20 +/* V7M SCR bits */ +FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) +FIELD(V7M_SCR, SLEEPDEEP, 2, 1) +FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) +FIELD(V7M_SCR, SEVONPEND, 4, 1) + /* V7M AIRCR bits */ FIELD(V7M_AIRCR, VECTRESET, 0, 1) FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 040f3380ec..ea3b7cce14 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -863,8 +863,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) } return val; case 0xd10: /* System Control. */ - /* TODO: Implement SLEEPONEXIT. */ - return 0; + return cpu->env.v7m.scr[attrs.secure]; case 0xd14: /* Configuration Control. */ /* The BFHFNMIGN bit is the only non-banked bit; we * keep it in the non-secure copy of the register. @@ -1285,8 +1284,13 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, } break; case 0xd10: /* System Control. */ - /* TODO: Implement control registers. */ - qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n"); + /* We don't implement deep-sleep so these bits are RAZ/WI. + * The other bits in the register are banked. + * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which + * is architecturally permitted. + */ + value &=3D ~(R_V7M_SCR_SLEEPDEEP_MASK | R_V7M_SCR_SLEEPDEEPS_MASK); + cpu->env.v7m.scr[attrs.secure] =3D value; break; case 0xd14: /* Configuration Control. */ /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ diff --git a/target/arm/machine.c b/target/arm/machine.c index cae63c2f98..30fb1454a6 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -226,6 +226,16 @@ static const VMStateDescription vmstate_m_csselr =3D { } }; =20 +static const VMStateDescription vmstate_m_scr =3D { + .name =3D "cpu/m/scr", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m =3D { .name =3D "cpu/m", .version_id =3D 4, @@ -248,6 +258,7 @@ static const VMStateDescription vmstate_m =3D { .subsections =3D (const VMStateDescription*[]) { &vmstate_m_faultmask_primask, &vmstate_m_csselr, + &vmstate_m_scr, NULL } }; @@ -411,6 +422,7 @@ static const VMStateDescription vmstate_m_security =3D { VMSTATE_UINT32(env.sau.rnr, ARMCPU), VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), VMSTATE_UINT32(env.sau.ctrl, ARMCPU), + VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; --=20 2.16.1