From nobody Fri Oct 24 22:18:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518710672585617.0077263204142; Thu, 15 Feb 2018 08:04:32 -0800 (PST) Received: from localhost ([::1]:33310 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emM1P-0002ha-I9 for importer@patchew.org; Thu, 15 Feb 2018 11:04:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35862) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emLeq-0004iI-VG for qemu-devel@nongnu.org; Thu, 15 Feb 2018 10:41:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emLen-0003da-0Q for qemu-devel@nongnu.org; Thu, 15 Feb 2018 10:41:13 -0500 Received: from mail-cys01nam02on0070.outbound.protection.outlook.com ([104.47.37.70]:28672 helo=NAM02-CY1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1emLem-0003dL-Lu for qemu-devel@nongnu.org; Thu, 15 Feb 2018 10:41:08 -0500 Received: from wsp141597wss.amd.com (165.204.78.1) by SN1PR12MB0157.namprd12.prod.outlook.com (10.162.3.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.506.18; Thu, 15 Feb 2018 15:41:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=O5vUMw/JkifBqHjVfj6Yl0OIzX8a9hEQbORAdJwJwaE=; b=thSD/s27Q/pm3rAGotcspmSiFYAT5oSnkV5QibcnFf4zDlI0nWbcEHEbwr9bgwEnVCqUr6Al/1EfTpFEcGmpDOQ5z0Ay8QHiqrj4h64pYOuq0oAn7u3JrnsZcr3llM9ueAJPooKYYAVpe3I12QENIOzUiufnWFrXWEHvpQfmKG8= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=brijesh.singh@amd.com; From: Brijesh Singh To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 09:39:48 -0600 Message-Id: <20180215153955.3253-23-brijesh.singh@amd.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180215153955.3253-1-brijesh.singh@amd.com> References: <20180215153955.3253-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.78.1] X-ClientProxiedBy: CY4PR04CA0044.namprd04.prod.outlook.com (10.172.133.30) To SN1PR12MB0157.namprd12.prod.outlook.com (10.162.3.144) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: f3ea603b-9f67-4eff-e90e-08d5748a8636 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(48565401081)(4534165)(4627221)(201703031133081)(201702281549075)(5600026)(4604075)(2017052603307)(7153060)(7193020); SRVR:SN1PR12MB0157; X-Microsoft-Exchange-Diagnostics: 1; SN1PR12MB0157; 3:eJciXU10lj580vcOjN15yQhmjn0XBPT723lWPBRRS3tcj9o47zw92gW+8tqRoj0qEpVxC6dZ4/81mvgp9CUyfP6pXy3/sszknzI8kCY8dB/ZuKLSwYIzoLbIouwaDWESqDKUVkSb9IHGfX2Rll1npncrmzW7GoxjejslNSrV/PkZFrceXKVXEw2ETS1HquCxWA+gZBIrEqpTyl6p8gxOctv//LtYMk6TYbFFJt2bA4UVd5tRceSLNLgO8CMU8OLc; 25:e4Tb2ZcvJLSRFzzteYfxlBJukjDO3AXImoiTtRL1bMJGq2J2NiBITHFX/dqxz0Oom9+dXx1IPlNZYlarW8wR8zgwit4AWlP/XpE7ZoTGb6CaEx1lh18LNi0A9siI+ZEB0TDENmw630KWy7WQCRfzJCzfpFj3+D4xyPHhE0DqIJSR2ZjDaSVe3s43vAEfRlUP7H+LRg+4/0JTyrUJu1kcVZENRnmBS0dNFjS9Lju7lFY8W5BZaJq4YbpoXFjEUYmTGcIMHQoEZ/I6vfWYTVUF9bGEfOT8c/+SflmHFUws9gaOGYyBQaW6OQpRRgghBh8cR47QTl6NpdPixWnouQYi+Q==; 31:+RZl7u5Zvfd78E01MvQTv2zTf4uHsWYnyUs9QJUtifa6Pnhyzl0P+urfja44hDlDPScsCLcTn9638c41WdfXtyq8pT7w9rDhJq3Si3U44DLphefCaAIGqHBKpVOsmieWddzfm1JLmPXfpWoAb2moLdxByF67R2rBeMPuNcCuB/xWcSRL2dIO5rVpThvll2Otqpuq8fQnrkNXsP55p3GQP4SS8E4Til2Va1JvMU4px7E= X-MS-TrafficTypeDiagnostic: SN1PR12MB0157: X-Microsoft-Exchange-Diagnostics: 1; SN1PR12MB0157; 20:4WO919gVtbfRUqPcdb/0G2HTPaudUBMkftR3RMEdk/L+L2TBkWo01SXujOnXmapd9lNyDoHScsOzU0L54kXlZBiIipsPzm23RzfPwjIc4dk/razdFoiymFMvg+OJi3rCvoQIk3+ytLjqtQEGUJIBU/vZeHyypidypn+11/IaZu+Nds8BFronJr0oYoQy4uL3u4UfNHj0NGJCiXfEAufZ95w/ru6JFYnj+A0zzmcMRjoDUEDsI3/cjfGFpOlRRo6cj9N6wO8Xj3VTSgRZPdL/foF6+hwHwWR4CkArWt7O/YYmz2BDpjpwZYfvksrdRoR0GJ58ncjaPBDJk/v0uYQY+waEeatNEnevk34LCO5ia3gZVHMMymAUy/SRmh5qylHsybEETQi/QBQ2FK63MtC+4G+OooTCKaHb3FPCkZUavCDHb0IReaiU5aM8rzFuQhUaj8tSLE7CFUO1Zze9XyflzFz3prhVTGJF1p7p+fxDehnE6Vy3DoX8hYHRubiiqYVE; 4:00yH/jUxkOIYJu9z0zwjdjVsF68O5T6pzqJX2TXmyG3LNwTKaixuvpEw1KJvvckrPC8qw+3CaFFAPpnNmZMLTElX7usZGAdnpv2JgqayPSa1okSHiIGL0KuDUQqmETjyHWVFBaPa6WlDs+ruLHxcu+FWRjnj/JNSgX0eodXVwEgk7WZfUhYyqISvxWQTjaybzjRKO4ixknECo7NKHkZyFeJF1HERhF2AmVddMXCO6PiDlliABbGpEK4Olh/+xShBwTSzV+eTJQGUOhwx0fziElwxAAgtyo7611g83BOTzb3vG/w3AXcuH6ZpBnP7cMN3 X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(767451399110); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040501)(2401047)(5005006)(8121501046)(3002001)(10201501046)(93006095)(93001095)(3231101)(944501161)(6055026)(6041288)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123558120)(6072148)(201708071742011); SRVR:SN1PR12MB0157; BCL:0; PCL:0; RULEID:; SRVR:SN1PR12MB0157; X-Forefront-PRVS: 058441C12A X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(1496009)(376002)(39380400002)(346002)(396003)(39860400002)(366004)(189003)(199004)(26005)(3846002)(386003)(8936002)(5660300001)(186003)(16526019)(316002)(6666003)(8666007)(1076002)(54906003)(6116002)(48376002)(50466002)(7416002)(478600001)(8676002)(68736007)(86362001)(16586007)(2906002)(50226002)(39060400002)(2351001)(6916009)(7736002)(106356001)(51416003)(8656006)(52116002)(25786009)(4326008)(97736004)(2950100002)(6486002)(2361001)(36756003)(76176011)(81166006)(53416004)(66066001)(53936002)(81156014)(47776003)(305945005)(105586002)(7696005); DIR:OUT; SFP:1101; SCL:1; SRVR:SN1PR12MB0157; H:wsp141597wss.amd.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; SN1PR12MB0157; 23:sNcKWxz88MTPPZlyx3sqgVpCecXrwbtZhKcV1ki1T?= =?us-ascii?Q?2YvBVZ5T3MLl/JXXSJ+5b815/ehMaX/vLMoRavwctIWDoODkgDzxYkCPtJRP?= =?us-ascii?Q?n4KzN7poWPUy6EzIamTbjfz7DC9lRAJ4g6DGfAF2v+Bxdh1ZQBsQZCUSY+9n?= =?us-ascii?Q?gcZFYI4u6LiOBAE16btYkmUizNag1JpBib3zqAReWgPBP8F50i72whYxyAn5?= =?us-ascii?Q?Or5I+2SeQSdAhvvdypYWt44i6roObJ7kedaG7TVEgeN+hc+efvtstWO+IJen?= =?us-ascii?Q?WkisE0Zv4vlpo/tlc0I9zebBPeBYACidltZcfHWDEISnW5mCKfh5RvefnBEk?= =?us-ascii?Q?Wg9kz/9YhJoEn/QflAbF9pNYjcIY+ysiDsu3UXBT88jKDPYm66fYJAqKbIWq?= =?us-ascii?Q?QpEf/2YPysT4KKblq4uYBG36qFb+pctLIwvidgxhYp8Uvf7oTIr47mQ/SrMt?= =?us-ascii?Q?Qg6RXfZ3BJw9EcgV+ug6RCwsVTqqrkPENH9YSMed72lu/drB0uonqyHSnE9Z?= =?us-ascii?Q?/WxZ3FqVJg0zSuHMlv6S02duQn3yWRr3lQlpdEJUKFA9pBk41mQ5JwbGv2xZ?= =?us-ascii?Q?v/2Ij8ixky5I5jT6TU0CmRC7CYX97ALNyua7sk1TRSuoFeZVFzMU1IRIrhYE?= =?us-ascii?Q?zfBR1dR3MdfqBcIMFnivFH5UhJaMqH4567fg6hQZRK3NJPabj5JJp4jbg0j3?= =?us-ascii?Q?ICqsfyeaBVp2aEBt7ZwSPBJsqgksU+DXX0InTEdWBhQNe3I0jjjqFqW8+eJ7?= =?us-ascii?Q?PNt7EzzNtatLTWbqU1/FYUdeksje49xOjN9r/SWh26qgXaew6aOHc++HoyFC?= =?us-ascii?Q?PuRfHIvh6Y8YacORXpF0rS9LqCyz7xlqLZL2wZ8Pez6aPczRxDD9mkHB7Eg/?= =?us-ascii?Q?lPcvAIYc5XzkuddXKGnFpdNkjNxbGdmrQEnSaevwxZoxkPGQR8Gx9SJL3nIc?= =?us-ascii?Q?/8XH9N/mQTb38tS8EUcPVSSdU+5k9PlycxikZ0eZ7q47p3rL0K39Vw8ffl81?= =?us-ascii?Q?oNk8xJo7uVD7l812o6+kgiMfBhXq7+yy/IbaM3GkZg+aOya2MHAW+2AftWW/?= =?us-ascii?Q?CfkgH8cILbQtsn1Dj3tFHcyj9U+OAIW11mvtpiH3DzCbIEoYKCWIFTHqRp+m?= =?us-ascii?Q?pg7zl+9plB8eyAvJygRdGYGRXqoywOC1GSd0K3MBdCo8BmNOJGnjQjxP+PQD?= =?us-ascii?Q?1lNVyEr94VILiDuUMwvmPTyU2bCjAZI/lbPen+HnsySv7qxE8cSbaBapau63?= =?us-ascii?Q?w4toIUBtvHDfwX4mMTjh6c08D8cKN1/0oLllljce0iKmWBECVArsTrLC6JNV?= =?us-ascii?B?UT09?= X-Microsoft-Exchange-Diagnostics: 1; SN1PR12MB0157; 6:i75d0LlGXMvzmKGcz75YofsQBOC015/TeLtLvhWQe/FDd2v47MKG8VWL09n2uaLG6eYa9HnQvQqpfTQx/HsLznMnX2/2cqsI/WHFsdZiKmMVYKvcMk78GXZpWyKfztjnb05jhMtVB8DMBwhW3mnUnXBpewMsvILR7xaO6Y+48zneKjhjAps5/mq0gAPXIPZHJpwx0BzC12kn0VUOB/PfPia/k/73O5i+M+x3u/XxFkbrveV4dt0ztl7fCyPgvnr3logzhlyexBZy4xQxUh7lWRNkVL4G3wjMlu7NQ5Cg8HXFB3yIQnmSowe0ZY7sWQ7G3MOOiSYwBl4n1Mxvl2sLThIB/XgKH5/Sa5tMGTjJSeQ=; 5:eE1VNs0bVXUqEi13woIAjL8ftN64YLR+RuEmmHzvDvxvLyggpOJeMDUfcPx9A3SBhyIJ6wFe/NROxfjPrMtRA7wnK2lv/xboP7Xhx2SlBLqyAxeP0ZFQO/S6hgJWQlXJoMYTck6Upo8EGmp9XVrl7R6Ie+ouqniVTAsg3TIHAdY=; 24:TKlG8Ha/f9LpqQNgmIMrcwtdid7y2dMZIAiow7PSJAgkiYjXXqCqg/MYqgrhW1Gu+u7IvRv40YKsw913RkeqehztYLy3jOscJPWF+AXo0L4=; 7:bPPUWmHcD+t/3eFB5+gvdqiNaxvOhgZGyMOpjMg8Nqqz9P1gsM/FZoZ1DUp8dvtug9NjISyt6sGdEQMgtHqMNKQ2/qdFjPPLPtIJwBqxgLt8sLDlP72DXCidXxCG65WcX3nApo9k/tAm3ho1RfyDHEZcSm+utLZ5MjhKg5AymhCj6vfrajW4dTkaBpEUEaHVXmfZ08KtddsYV204W7aBO+qzNsfiPwNQJNLz9RvPUQYs/rnCwmvQnQYpVZwgHkjA SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; SN1PR12MB0157; 20:xQvzaCFBkT2rbAJRqk0BJzVssXgGB3TwIoLs73APXk5L6gpO/1pq2O4iOwELDq9zzvqGXXkR15nCEelZypWwEMokzX1V4jydCmPB0k4i3j+A/Ll7rueVSB8yOJeoBNDShLzyg0o36Ka1kJNN7PbhCa8s6mpE6Ytqn8z0VwNvBxyvru4iD2e9XW6X/cl523iGLuvnJ9Ak0EwNdo4rw17hpYU1d/By+Bw/s7i00tuOpEg3UQhFOidPWMqY3tOg315o X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2018 15:41:02.6503 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f3ea603b-9f67-4eff-e90e-08d5748a8636 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB0157 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.37.70 Subject: [Qemu-devel] [PATCH v9 22/29] target/i386: clear C-bit when walking SEV guest page table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Brijesh Singh , kvm@vger.kernel.org, "Michael S. Tsirkin" , Stefan Hajnoczi , Alexander Graf , "Edgar E. Iglesias" , Markus Armbruster , Bruce Rogers , Christian Borntraeger , Marcel Apfelbaum , Borislav Petkov , Thomas Lendacky , Eduardo Habkost , Richard Henderson , "Dr. David Alan Gilbert" , Alistair Francis , Cornelia Huck , Richard Henderson , Peter Crosthwaite , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In SEV-enabled guest the pte entry will have C-bit set, we need to clear the C-bit when walking the page table. Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Signed-off-by: Brijesh Singh --- target/i386/helper.c | 31 +++++++++++++---------- target/i386/monitor.c | 69 +++++++++++++++++++++++++++++++++--------------= ---- 2 files changed, 63 insertions(+), 37 deletions(-) diff --git a/target/i386/helper.c b/target/i386/helper.c index 58fb6eec562a..1791c854f7cf 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" +#include "sysemu/sev.h" #include "kvm_i386.h" #ifndef CONFIG_USER_ONLY #include "sysemu/sysemu.h" @@ -732,6 +733,9 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr = addr) int32_t a20_mask; uint32_t page_offset; int page_size; + uint64_t me_mask; + + me_mask =3D sev_get_me_mask(); =20 a20_mask =3D x86_get_a20_mask(env); if (!(env->cr[0] & CR0_PG_MASK)) { @@ -755,25 +759,25 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) } =20 if (la57) { - pml5e_addr =3D ((env->cr[3] & ~0xfff) + + pml5e_addr =3D ((env->cr[3] & ~0xfff & me_mask) + (((addr >> 48) & 0x1ff) << 3)) & a20_mask; - pml5e =3D ldq_phys_debug(cs, pml5e_addr); + pml5e =3D ldq_phys_debug(cs, pml5e_addr) & me_mask; if (!(pml5e & PG_PRESENT_MASK)) { return -1; } } else { - pml5e =3D env->cr[3]; + pml5e =3D env->cr[3] & me_mask; } =20 pml4e_addr =3D ((pml5e & PG_ADDRESS_MASK) + (((addr >> 39) & 0x1ff) << 3)) & a20_mask; - pml4e =3D ldq_phys_debug(cs, pml4e_addr); + pml4e =3D ldq_phys_debug(cs, pml4e_addr) & me_mask; if (!(pml4e & PG_PRESENT_MASK)) { return -1; } pdpe_addr =3D ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) & a20_mask; - pdpe =3D x86_ldq_phys(cs, pdpe_addr); + pdpe =3D ldq_phys_debug(cs, pdpe_addr) & me_mask; if (!(pdpe & PG_PRESENT_MASK)) { return -1; } @@ -786,16 +790,16 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) } else #endif { - pdpe_addr =3D ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) & - a20_mask; - pdpe =3D ldq_phys_debug(cs, pdpe_addr); + pdpe_addr =3D ((env->cr[3] & ~0x1f & me_mask) + ((addr >> 27) = & 0x18)) + & a20_mask; + pdpe =3D ldq_phys_debug(cs, pdpe_addr) & me_mask; if (!(pdpe & PG_PRESENT_MASK)) return -1; } =20 pde_addr =3D ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) & a20_mask; - pde =3D ldq_phys_debug(cs, pde_addr); + pde =3D ldq_phys_debug(cs, pde_addr) & me_mask; if (!(pde & PG_PRESENT_MASK)) { return -1; } @@ -808,7 +812,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr = addr) pte_addr =3D ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) & a20_mask; page_size =3D 4096; - pte =3D ldq_phys_debug(cs, pte_addr); + pte =3D ldq_phys_debug(cs, pte_addr) & me_mask; } if (!(pte & PG_PRESENT_MASK)) { return -1; @@ -817,8 +821,9 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr = addr) uint32_t pde; =20 /* page directory entry */ - pde_addr =3D ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a2= 0_mask; - pde =3D ldl_phys_debug(cs, pde_addr); + pde_addr =3D ((env->cr[3] & ~0xfff & me_mask) + ((addr >> 20) & 0x= ffc)) + & a20_mask; + pde =3D ldl_phys_debug(cs, pde_addr) & me_mask; if (!(pde & PG_PRESENT_MASK)) return -1; if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { @@ -827,7 +832,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr = addr) } else { /* page directory entry */ pte_addr =3D ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_m= ask; - pte =3D ldl_phys_debug(cs, pte_addr); + pte =3D ldl_phys_debug(cs, pte_addr) & me_mask; if (!(pte & PG_PRESENT_MASK)) { return -1; } diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 55ea10deb8ef..00b8cfcd3044 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -29,6 +29,7 @@ #include "qapi/qmp/qdict.h" #include "hw/i386/pc.h" #include "sysemu/kvm.h" +#include "sysemu/sev.h" #include "hmp.h" =20 =20 @@ -95,16 +96,20 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *= env) unsigned int l1, l2, l3; uint64_t pdpe, pde, pte; uint64_t pdp_addr, pd_addr, pt_addr; + uint64_t me_mask; + + me_mask =3D sev_get_me_mask(); =20 pdp_addr =3D env->cr[3] & ~0x1f; + pdp_addr &=3D me_mask; for (l1 =3D 0; l1 < 4; l1++) { cpu_physical_memory_read_debug(pdp_addr + l1 * 8, &pdpe, 8); - pdpe =3D le64_to_cpu(pdpe); + pdpe =3D le64_to_cpu(pdpe & me_mask); if (pdpe & PG_PRESENT_MASK) { pd_addr =3D pdpe & 0x3fffffffff000ULL; for (l2 =3D 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pd_addr + l2 * 8, &pde, 8); - pde =3D le64_to_cpu(pde); + pde =3D le64_to_cpu(pde & me_mask); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { /* 2M pages with PAE, CR4.PSE is ignored */ @@ -115,7 +120,7 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *= env) for (l3 =3D 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pt_addr + l3 * = 8, &pte, 8); - pte =3D le64_to_cpu(pte); + pte =3D le64_to_cpu(pte & me_mask); if (pte & PG_PRESENT_MASK) { print_pte(mon, env, (l1 << 30) + (l2 << 21) + (l3 << 12), @@ -137,10 +142,13 @@ static void tlb_info_la48(Monitor *mon, CPUArchState = *env, uint64_t l1, l2, l3, l4; uint64_t pml4e, pdpe, pde, pte; uint64_t pdp_addr, pd_addr, pt_addr; + uint64_t me_mask; + + me_mask =3D sev_get_me_mask(); =20 for (l1 =3D 0; l1 < 512; l1++) { cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); - pml4e =3D le64_to_cpu(pml4e); + pml4e =3D le64_to_cpu(pml4e & me_mask); if (!(pml4e & PG_PRESENT_MASK)) { continue; } @@ -148,7 +156,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *e= nv, pdp_addr =3D pml4e & 0x3fffffffff000ULL; for (l2 =3D 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); - pdpe =3D le64_to_cpu(pdpe); + pdpe =3D le64_to_cpu(pdpe & me_mask); if (!(pdpe & PG_PRESENT_MASK)) { continue; } @@ -163,7 +171,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *e= nv, pd_addr =3D pdpe & 0x3fffffffff000ULL; for (l3 =3D 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde, 8); - pde =3D le64_to_cpu(pde); + pde =3D le64_to_cpu(pde & me_mask); if (!(pde & PG_PRESENT_MASK)) { continue; } @@ -178,7 +186,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *e= nv, pt_addr =3D pde & 0x3fffffffff000ULL; for (l4 =3D 0; l4 < 512; l4++) { cpu_physical_memory_read_debug(pt_addr + l4 * 8, &pte,= 8); - pte =3D le64_to_cpu(pte); + pte =3D le64_to_cpu(pte & me_mask); if (pte & PG_PRESENT_MASK) { print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21) + (l4 << 12), @@ -195,11 +203,14 @@ static void tlb_info_la57(Monitor *mon, CPUArchState = *env) uint64_t l0; uint64_t pml5e; uint64_t pml5_addr; + uint64_t me_mask; =20 - pml5_addr =3D env->cr[3] & 0x3fffffffff000ULL; + me_mask =3D sev_get_me_mask(); + + pml5_addr =3D env->cr[3] & 0x3fffffffff000ULL & me_mask; for (l0 =3D 0; l0 < 512; l0++) { cpu_physical_memory_read_debug(pml5_addr + l0 * 8, &pml5e, 8); - pml5e =3D le64_to_cpu(pml5e); + pml5e =3D le64_to_cpu(pml5e & me_mask); if (pml5e & PG_PRESENT_MASK) { tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL); } @@ -227,7 +238,8 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) if (env->cr[4] & CR4_LA57_MASK) { tlb_info_la57(mon, env); } else { - tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL= ); + tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL= & + sev_get_me_mask()); } } else #endif @@ -311,19 +323,22 @@ static void mem_info_pae32(Monitor *mon, CPUArchState= *env) uint64_t pdpe, pde, pte; uint64_t pdp_addr, pd_addr, pt_addr; hwaddr start, end; + uint64_t me_mask; =20 - pdp_addr =3D env->cr[3] & ~0x1f; + me_mask =3D sev_get_me_mask(); + + pdp_addr =3D env->cr[3] & ~0x1f & me_mask; last_prot =3D 0; start =3D -1; for (l1 =3D 0; l1 < 4; l1++) { cpu_physical_memory_read_debug(pdp_addr + l1 * 8, &pdpe, 8); - pdpe =3D le64_to_cpu(pdpe); + pdpe =3D le64_to_cpu(pdpe & me_mask); end =3D l1 << 30; if (pdpe & PG_PRESENT_MASK) { pd_addr =3D pdpe & 0x3fffffffff000ULL; for (l2 =3D 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pd_addr + l2 * 8, &pde, 8); - pde =3D le64_to_cpu(pde); + pde =3D le64_to_cpu(pde & me_mask); end =3D (l1 << 30) + (l2 << 21); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { @@ -335,7 +350,7 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *= env) for (l3 =3D 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pt_addr + l3 * = 8, &pte, 8); - pte =3D le64_to_cpu(pte); + pte =3D le64_to_cpu(pte & me_mask); end =3D (l1 << 30) + (l2 << 21) + (l3 << 12); if (pte & PG_PRESENT_MASK) { prot =3D pte & pde & (PG_USER_MASK | PG_RW= _MASK | @@ -368,19 +383,22 @@ static void mem_info_la48(Monitor *mon, CPUArchState = *env) uint64_t l1, l2, l3, l4; uint64_t pml4e, pdpe, pde, pte; uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr, start, end; + uint64_t me_mask; + + me_mask =3D sev_get_me_mask(); =20 - pml4_addr =3D env->cr[3] & 0x3fffffffff000ULL; + pml4_addr =3D env->cr[3] & 0x3fffffffff000ULL & me_mask; last_prot =3D 0; start =3D -1; for (l1 =3D 0; l1 < 512; l1++) { cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); - pml4e =3D le64_to_cpu(pml4e); + pml4e =3D le64_to_cpu(pml4e & me_mask); end =3D l1 << 39; if (pml4e & PG_PRESENT_MASK) { pdp_addr =3D pml4e & 0x3fffffffff000ULL; for (l2 =3D 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8= ); - pdpe =3D le64_to_cpu(pdpe); + pdpe =3D le64_to_cpu(pdpe & me_mask); end =3D (l1 << 39) + (l2 << 30); if (pdpe & PG_PRESENT_MASK) { if (pdpe & PG_PSE_MASK) { @@ -393,7 +411,7 @@ static void mem_info_la48(Monitor *mon, CPUArchState *e= nv) for (l3 =3D 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pd_addr + l3 * = 8, &pde, 8); - pde =3D le64_to_cpu(pde); + pde =3D le64_to_cpu(pde & me_mask); end =3D (l1 << 39) + (l2 << 30) + (l3 << 21); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { @@ -407,7 +425,7 @@ static void mem_info_la48(Monitor *mon, CPUArchState *e= nv) cpu_physical_memory_read_debug(pt_= addr + l4 * 8, &pte, 8); - pte =3D le64_to_cpu(pte); + pte =3D le64_to_cpu(pte & me_mask); end =3D (l1 << 39) + (l2 << 30) + (l3 << 21) + (l4 << 12); if (pte & PG_PRESENT_MASK) { @@ -446,13 +464,16 @@ static void mem_info_la57(Monitor *mon, CPUArchState = *env) uint64_t l0, l1, l2, l3, l4; uint64_t pml5e, pml4e, pdpe, pde, pte; uint64_t pml5_addr, pml4_addr, pdp_addr, pd_addr, pt_addr, start, end; + uint64_t me_mask; + + me_mask =3D sev_get_me_mask(); =20 - pml5_addr =3D env->cr[3] & 0x3fffffffff000ULL; + pml5_addr =3D env->cr[3] & 0x3fffffffff000ULL & me_mask; last_prot =3D 0; start =3D -1; for (l0 =3D 0; l0 < 512; l0++) { cpu_physical_memory_read_debug(pml5_addr + l0 * 8, &pml5e, 8); - pml5e =3D le64_to_cpu(pml5e); + pml5e =3D le64_to_cpu(pml5e & me_mask); end =3D l0 << 48; if (!(pml5e & PG_PRESENT_MASK)) { prot =3D 0; @@ -463,7 +484,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *e= nv) pml4_addr =3D pml5e & 0x3fffffffff000ULL; for (l1 =3D 0; l1 < 512; l1++) { cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); - pml4e =3D le64_to_cpu(pml4e); + pml4e =3D le64_to_cpu(pml4e & me_mask); end =3D (l0 << 48) + (l1 << 39); if (!(pml4e & PG_PRESENT_MASK)) { prot =3D 0; @@ -474,7 +495,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *e= nv) pdp_addr =3D pml4e & 0x3fffffffff000ULL; for (l2 =3D 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8= ); - pdpe =3D le64_to_cpu(pdpe); + pdpe =3D le64_to_cpu(pdpe & me_mask); end =3D (l0 << 48) + (l1 << 39) + (l2 << 30); if (pdpe & PG_PRESENT_MASK) { prot =3D 0; @@ -493,7 +514,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *e= nv) pd_addr =3D pdpe & 0x3fffffffff000ULL; for (l3 =3D 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde,= 8); - pde =3D le64_to_cpu(pde); + pde =3D le64_to_cpu(pde & me_mask); end =3D (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << = 21); if (pde & PG_PRESENT_MASK) { prot =3D 0; --=20 2.14.3