From nobody Fri Oct 24 20:17:15 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of _spf.google.com designates 209.85.220.194 as permitted sender) client-ip=209.85.220.194; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-qk0-f194.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of _spf.google.com designates 209.85.220.194 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-qk0-f194.google.com (mail-qk0-f194.google.com [209.85.220.194]) by mx.zohomail.com with SMTPS id 151866897095251.04673289202174; Wed, 14 Feb 2018 20:29:30 -0800 (PST) Received: by mail-qk0-f194.google.com with SMTP id h129so9489318qke.8 for ; Wed, 14 Feb 2018 20:29:30 -0800 (PST) Return-Path: Return-Path: Received: from x1.local ([138.117.48.219]) by smtp.gmail.com with ESMTPSA id t33sm10680312qtc.14.2018.02.14.20.29.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Feb 2018 20:29:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=86GnShG4IKgp81+b/18PI7uYP7amnZd51UDqCTkIo3U=; b=SzCbgsAFAfhSZPDOCzZw49xO42WT+1cZZEUF7UolPrproB5lunxB9GU8pIAbdTwJLF JEmxNoZyiXOtKvRD3QYzb3NDlYrRXw6qWYO4fzr+x/xA9QxnMqpycjmdy9SfU74uCw/y 6ztA9q4ZO/v2YIdh+DZPT6MfVcnUvTZjbUQ0sviw+BsjiZYQPWkwHw8gIYcq2t88urL6 rgdP2JXyT8ixmKrjrZtTedOKDhMbst/dSCLk2edaCMP7bRE9W0RZ3xls2bpfBI+jHdAY 8qqk3RYekTCBy/SH0GZx+hcMj5wk8Ly53YLruLBARXG2xGcdyTh/pMyW9sknpwAqKKj7 n/Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=86GnShG4IKgp81+b/18PI7uYP7amnZd51UDqCTkIo3U=; b=f7GpEsUcVxxWSFNUI9D0dlqmqkEhse2OUMF4UrP7G5SuiTka2rjTtFi+Sz6lmTdETm 8KonQYjWRkvzzs4amM9ilo32lTfPFl7tyNvi5lwhxTjOP0d71czLlju3bU7/1uuRrqgI k8yikGPo9kv5jr/+engoKwFBSm93/8RDX5FMhF3RDfhZhNws9fKytu3w8HtZEpdmb26C Ci3zsH7hYCujF51M8g594qrhXVQepRkw8UAt+WQ+DGLeMmchLVq2EzCt6U0aD1wQNQ3h MuKQibggFhBSRstp/l+I92PxtwApw6OoUNj/1N6SpM6tXXxf6F2GK7o6sA+3orin6iEg sIug== X-Gm-Message-State: APf1xPABzNGZw+j1IqgSv1nrmrnkStNOxKiqPUOeiJhtMEu8WK7VYpd5 B+a0vc8qTaBbmhTBXv0Z19zAdmTw X-Google-Smtp-Source: AH8x226Y1cyOBsVnC0vx28cDs10Ia2epJsDaQOPNBv6+UDB7XlZSBoBjOOq4R3qm/kZPeMohbINlEQ== X-Received: by 10.55.19.232 with SMTP id 101mr2205526qkt.198.1518668970009; Wed, 14 Feb 2018 20:29:30 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Aurelien Jarno , Yongbok Kim Subject: [PATCH 06/30] hw/mips: use the BYTE-based definitions Date: Thu, 15 Feb 2018 01:28:36 -0300 Message-Id: <20180215042900.16078-7-f4bug@amsat.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180215042900.16078-1-f4bug@amsat.org> References: <20180215042900.16078-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZohoMail: RDKM_0 RSF_0 Z_629925259 SPT_0 It ease code review, unit is explicit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/intc/mips_gic.h | 2 +- include/hw/mips/bios.h | 2 +- hw/mips/boston.c | 2 +- hw/mips/mips_fulong2e.c | 6 +++--- hw/mips/mips_malta.c | 19 ++++++++++--------- hw/mips/mips_r4k.c | 10 +++++----- hw/misc/mips_itu.c | 2 +- hw/pci-host/xilinx-pcie.c | 4 ++-- 8 files changed, 24 insertions(+), 23 deletions(-) diff --git a/include/hw/intc/mips_gic.h b/include/hw/intc/mips_gic.h index b98d50094a..5ae5a74249 100644 --- a/include/hw/intc/mips_gic.h +++ b/include/hw/intc/mips_gic.h @@ -19,7 +19,7 @@ =20 /* The MIPS default location */ #define GIC_BASE_ADDR 0x1bdc0000ULL -#define GIC_ADDRSPACE_SZ (128 * 1024) +#define GIC_ADDRSPACE_SZ (128 * K_BYTE) =20 /* Constants */ #define GIC_POL_POS 1 diff --git a/include/hw/mips/bios.h b/include/hw/mips/bios.h index b4b88ac43d..c70fab193a 100644 --- a/include/hw/mips/bios.h +++ b/include/hw/mips/bios.h @@ -1,6 +1,6 @@ #include "cpu.h" =20 -#define BIOS_SIZE (4 * 1024 * 1024) +#define BIOS_SIZE (4 * M_BYTE) #ifdef TARGET_WORDS_BIGENDIAN #define BIOS_FILENAME "mips_bios.bin" #else diff --git a/hw/mips/boston.c b/hw/mips/boston.c index e99f3638cf..1a1be57ba0 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -436,7 +436,7 @@ static void boston_mach_init(MachineState *machine) bool is_64b; =20 if ((machine->ram_size % G_BYTE) || - (machine->ram_size > (2 * G_BYTE))) { + (machine->ram_size > 2 * G_BYTE)) { error_report("Memory size must be 1GB or 2GB"); exit(1); } diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index f68c625666..428bf11fb4 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -164,7 +164,7 @@ static int64_t load_kernel (CPUMIPSState *env) /* Setup minimum environment variables */ prom_set(prom_buf, index++, "busclock=3D33000000"); prom_set(prom_buf, index++, "cpuclock=3D100000000"); - prom_set(prom_buf, index++, "memsize=3D%i", loaderparams.ram_size/1024= /1024); + prom_set(prom_buf, index++, "memsize=3D%llu", loaderparams.ram_size / = M_BYTE); prom_set(prom_buf, index++, "modetty0=3D38400n8r"); prom_set(prom_buf, index++, NULL); =20 @@ -281,10 +281,10 @@ static void mips_fulong2e_init(MachineState *machine) qemu_register_reset(main_cpu_reset, cpu); =20 /* fulong 2e has 256M ram. */ - ram_size =3D 256 * 1024 * 1024; + ram_size =3D 256 * M_BYTE; =20 /* fulong 2e has a 1M flash.Winbond W39L040AP70Z */ - bios_size =3D 1024 * 1024; + bios_size =3D 1 * M_BYTE; =20 /* allocate RAM */ memory_region_allocate_system_memory(ram, NULL, "fulong2e.ram", ram_si= ze); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 6f0deb99e7..7d27502b1a 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1033,9 +1033,9 @@ void mips_malta_init(MachineState *machine) mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq); =20 /* allocate RAM */ - if (ram_size > (2048u << 20)) { - error_report("Too much memory for this machine: %dMB, maximum 2048= MB", - ((unsigned int)ram_size / (1 << 20))); + if (ram_size > 2 * G_BYTE) { + error_report("Too much memory for this machine: %lluMB, maximum 20= 48MB", + ram_size / M_BYTE); exit(1); } =20 @@ -1046,17 +1046,18 @@ void mips_malta_init(MachineState *machine) =20 /* alias for pre IO hole access */ memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ra= m", - ram_high, 0, MIN(ram_size, (256 << 20))); + ram_high, 0, MIN(ram_size, 256 * M_BYTE)); memory_region_add_subregion(system_memory, 0, ram_low_preio); =20 /* alias for post IO hole access, if there is enough RAM */ - if (ram_size > (512 << 20)) { + if (ram_size > 512 * M_BYTE) { ram_low_postio =3D g_new(MemoryRegion, 1); memory_region_init_alias(ram_low_postio, NULL, "mips_malta_low_postio.ram", - ram_high, 512 << 20, - ram_size - (512 << 20)); - memory_region_add_subregion(system_memory, 512 << 20, ram_low_post= io); + ram_high, 512 * M_BYTE, + ram_size - 512 * M_BYTE); + memory_region_add_subregion(system_memory, 512 * M_BYTE, + ram_low_postio); } =20 /* generate SPD EEPROM data */ @@ -1090,7 +1091,7 @@ void mips_malta_init(MachineState *machine) bios =3D pflash_cfi01_get_memory(fl); fl_idx++; if (kernel_filename) { - ram_low_size =3D MIN(ram_size, 256 << 20); + ram_low_size =3D MIN(ram_size, 256 * M_BYTE); /* For KVM we reserve 1MB of RAM for running bootloader */ if (kvm_enabled()) { ram_low_size -=3D 0x100000; diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 5a74c44b9a..d814045c27 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -143,7 +143,7 @@ static int64_t load_kernel(void) } =20 rom_add_blob_fixed("params", params_buf, params_size, - (16 << 20) - 264); + 16 * M_BYTE - params_size); g_free(params_buf); return entry; } @@ -157,7 +157,7 @@ static void main_cpu_reset(void *opaque) env->active_tc.PC =3D s->vector; } =20 -static const int sector_len =3D 32 * 1024; +static const int sector_len =3D 32 * K_BYTE; static void mips_r4k_init(MachineState *machine) { @@ -193,9 +193,9 @@ void mips_r4k_init(MachineState *machine) qemu_register_reset(main_cpu_reset, reset_info); =20 /* allocate RAM */ - if (ram_size > (256 << 20)) { - error_report("Too much memory for this machine: %dMB, maximum 256M= B", - ((unsigned int)ram_size / (1 << 20))); + if (ram_size > 256 * M_BYTE) { + error_report("Too much memory for this machine: %lluMB, maximum 25= 6MB", + ram_size / M_BYTE); exit(1); } memory_region_allocate_system_memory(ram, NULL, "mips_r4k.ram", ram_si= ze); diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index ef935b51a8..fc72d376e4 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -83,7 +83,7 @@ static void itc_reconfigure(MIPSITUState *tag) uint64_t *am =3D &tag->ITCAddressMap[0]; MemoryRegion *mr =3D &tag->storage_io; hwaddr address =3D am[0] & ITC_AM0_BASE_ADDRESS_MASK; - uint64_t size =3D (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK); + uint64_t size =3D (1 * K_BYTE) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled =3D (am[0] & ITC_AM0_EN_MASK) !=3D 0; =20 memory_region_transaction_begin(); diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c index 044e312dc1..b7272d173a 100644 --- a/hw/pci-host/xilinx-pcie.c +++ b/hw/pci-host/xilinx-pcie.c @@ -158,9 +158,9 @@ static void xilinx_pcie_host_init(Object *obj) static Property xilinx_pcie_host_props[] =3D { DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0), DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0), - DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 << 20), + DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 * M_BYTE), DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0), - DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 << 20), + DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 * M_BYTE), DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true), DEFINE_PROP_END_OF_LIST(), }; --=20 2.16.1