From nobody Fri Oct 24 21:38:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518629580131468.09221777476296; Wed, 14 Feb 2018 09:33:00 -0800 (PST) Received: from localhost ([::1]:42777 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1em0vL-000417-3C for importer@patchew.org; Wed, 14 Feb 2018 12:32:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39861) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1em0ti-00033F-CS for qemu-devel@nongnu.org; Wed, 14 Feb 2018 12:31:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1em0te-0001Vp-A0 for qemu-devel@nongnu.org; Wed, 14 Feb 2018 12:31:10 -0500 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:49240 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1em0te-0001Vg-4X; Wed, 14 Feb 2018 12:31:06 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B891440267C2; Wed, 14 Feb 2018 17:31:05 +0000 (UTC) Received: from t460s.redhat.com (unknown [10.36.118.10]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0C6C6101041A; Wed, 14 Feb 2018 17:31:02 +0000 (UTC) From: David Hildenbrand To: qemu-s390x@nongnu.org Date: Wed, 14 Feb 2018 18:31:02 +0100 Message-Id: <20180214173102.9363-1-david@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.6]); Wed, 14 Feb 2018 17:31:05 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.6]); Wed, 14 Feb 2018 17:31:05 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'david@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PATCH v2] s390x/tcg: add various alignment check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Graf , Cornelia Huck , David Hildenbrand , qemu-devel@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Let's add proper alignment checks for a handful of instructions that require a SPECIFICATION exception in case alignment is violated. Introduce new wout/in functions. Declare them as "static inline" to avoid warnings about not being used for CONFIG_USER_ONLY (as we are right now only using them for privileged instructions). Convert STORE CPU ID right away to make use of the wout function. Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson --- target/s390x/insn-data.def | 16 ++++++++-------- target/s390x/mem_helper.c | 25 +++++++++++++++++++++++++ target/s390x/translate.c | 33 ++++++++++++++++++++++++++++++++- 3 files changed, 65 insertions(+), 9 deletions(-) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 621e10d615..157619403d 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1000,13 +1000,13 @@ /* ??? Not implemented - is it necessary? */ C(0xb204, SCK, S, Z, 0, 0, 0, 0, 0, 0) /* SET CLOCK COMPARATOR */ - C(0xb206, SCKC, S, Z, 0, m2_64, 0, 0, sckc, 0) + C(0xb206, SCKC, S, Z, 0, m2_64a, 0, 0, sckc, 0) /* SET CLOCK PROGRAMMABLE FIELD */ C(0x0107, SCKPF, E, Z, 0, 0, 0, 0, sckpf, 0) /* SET CPU TIMER */ - C(0xb208, SPT, S, Z, 0, m2_64, 0, 0, spt, 0) + C(0xb208, SPT, S, Z, 0, m2_64a, 0, 0, spt, 0) /* SET PREFIX */ - C(0xb210, SPX, S, Z, 0, m2_32u, 0, 0, spx, 0) + C(0xb210, SPX, S, Z, 0, m2_32ua, 0, 0, spx, 0) /* SET PSW KEY FROM ADDRESS */ C(0xb20a, SPKA, S, Z, 0, a2, 0, 0, spka, 0) /* SET STORAGE KEY EXTENDED */ @@ -1021,20 +1021,20 @@ /* STORE CLOCK EXTENDED */ C(0xb278, STCKE, S, Z, 0, a2, 0, 0, stcke, 0) /* STORE CLOCK COMPARATOR */ - C(0xb207, STCKC, S, Z, la2, 0, new, m1_64, stckc, 0) + C(0xb207, STCKC, S, Z, la2, 0, new, m1_64a, stckc, 0) /* STORE CONTROL */ C(0xb600, STCTL, RS_a, Z, 0, a2, 0, 0, stctl, 0) C(0xeb25, STCTG, RSY_a, Z, 0, a2, 0, 0, stctg, 0) /* STORE CPU ADDRESS */ - C(0xb212, STAP, S, Z, la2, 0, new, m1_16, stap, 0) + C(0xb212, STAP, S, Z, la2, 0, new, m1_16a, stap, 0) /* STORE CPU ID */ - C(0xb202, STIDP, S, Z, la2, 0, new, 0, stidp, 0) + C(0xb202, STIDP, S, Z, la2, 0, new, m1_64a, stidp, 0) /* STORE CPU TIMER */ - C(0xb209, STPT, S, Z, la2, 0, new, m1_64, stpt, 0) + C(0xb209, STPT, S, Z, la2, 0, new, m1_64a, stpt, 0) /* STORE FACILITY LIST */ C(0xb2b1, STFL, S, Z, 0, 0, 0, 0, stfl, 0) /* STORE PREFIX */ - C(0xb211, STPX, S, Z, la2, 0, new, m1_32, stpx, 0) + C(0xb211, STPX, S, Z, la2, 0, new, m1_32a, stpx, 0) /* STORE SYSTEM INFORMATION */ C(0xb27d, STSI, S, Z, 0, a2, 0, 0, stsi, 0) /* STORE THEN AND SYSTEM MASK */ diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 427b795a78..d5291b246e 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -693,6 +693,11 @@ void HELPER(lam)(CPUS390XState *env, uint32_t r1, uint= 64_t a2, uint32_t r3) uintptr_t ra =3D GETPC(); int i; =20 + if (a2 & 0x3) { + /* we either came here by lam or lamy, which have different length= s */ + s390_program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO, ra); + } + for (i =3D r1;; i =3D (i + 1) % 16) { env->aregs[i] =3D cpu_ldl_data_ra(env, a2, ra); a2 +=3D 4; @@ -709,6 +714,10 @@ void HELPER(stam)(CPUS390XState *env, uint32_t r1, uin= t64_t a2, uint32_t r3) uintptr_t ra =3D GETPC(); int i; =20 + if (a2 & 0x3) { + s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); + } + for (i =3D r1;; i =3D (i + 1) % 16) { cpu_stl_data_ra(env, a2, env->aregs[i], ra); a2 +=3D 4; @@ -1620,6 +1629,10 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, = uint64_t a2, uint32_t r3) uint64_t src =3D a2; uint32_t i; =20 + if (src & 0x7) { + s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); + } + for (i =3D r1;; i =3D (i + 1) % 16) { uint64_t val =3D cpu_ldq_data_ra(env, src, ra); if (env->cregs[i] !=3D val && i >=3D 9 && i <=3D 11) { @@ -1650,6 +1663,10 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) uint64_t src =3D a2; uint32_t i; =20 + if (src & 0x3) { + s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); + } + for (i =3D r1;; i =3D (i + 1) % 16) { uint32_t val =3D cpu_ldl_data_ra(env, src, ra); if ((uint32_t)env->cregs[i] !=3D val && i >=3D 9 && i <=3D 11) { @@ -1677,6 +1694,10 @@ void HELPER(stctg)(CPUS390XState *env, uint32_t r1, = uint64_t a2, uint32_t r3) uint64_t dest =3D a2; uint32_t i; =20 + if (dest & 0x7) { + s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); + } + for (i =3D r1;; i =3D (i + 1) % 16) { cpu_stq_data_ra(env, dest, env->cregs[i], ra); dest +=3D sizeof(uint64_t); @@ -1693,6 +1714,10 @@ void HELPER(stctl)(CPUS390XState *env, uint32_t r1, = uint64_t a2, uint32_t r3) uint64_t dest =3D a2; uint32_t i; =20 + if (dest & 0x3) { + s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); + } + for (i =3D r1;; i =3D (i + 1) % 16) { cpu_stl_data_ra(env, dest, env->cregs[i], ra); dest +=3D sizeof(uint32_t); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 5aea3bbca6..4ea4e195bb 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -4062,7 +4062,6 @@ static ExitStatus op_stidp(DisasContext *s, DisasOps = *o) { check_privileged(s); tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, cpuid)); - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEQ | MO_AL= IGN); return NO_EXIT; } =20 @@ -5220,18 +5219,36 @@ static void wout_m1_16(DisasContext *s, DisasFields= *f, DisasOps *o) } #define SPEC_wout_m1_16 0 =20 +static inline void wout_m1_16a(DisasContext *s, DisasFields *f, DisasOps *= o) +{ + tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUW | MO_AL= IGN); +} +#define SPEC_wout_m1_16a 0 + static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o) { tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s)); } #define SPEC_wout_m1_32 0 =20 +static inline void wout_m1_32a(DisasContext *s, DisasFields *f, DisasOps *= o) +{ + tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUL | MO_AL= IGN); +} +#define SPEC_wout_m1_32a 0 + static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o) { tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s)); } #define SPEC_wout_m1_64 0 =20 +static inline void wout_m1_64a(DisasContext *s, DisasFields *f, DisasOps *= o) +{ + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEQ | MO_AL= IGN); +} +#define SPEC_wout_m1_64a 0 + static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o) { tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s)); @@ -5657,6 +5674,13 @@ static void in2_m2_32u(DisasContext *s, DisasFields = *f, DisasOps *o) } #define SPEC_in2_m2_32u 0 =20 +static inline void in2_m2_32ua(DisasContext *s, DisasFields *f, DisasOps *= o) +{ + in2_a2(s, f, o); + tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_TEUL | MO_ALIG= N); +} +#define SPEC_in2_m2_32ua 0 + static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o) { in2_a2(s, f, o); @@ -5664,6 +5688,13 @@ static void in2_m2_64(DisasContext *s, DisasFields *= f, DisasOps *o) } #define SPEC_in2_m2_64 0 =20 +static inline void in2_m2_64a(DisasContext *s, DisasFields *f, DisasOps *o) +{ + in2_a2(s, f, o); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEQ | MO_ALIG= N); +} +#define SPEC_in2_m2_64a 0 + static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o) { in2_ri2(s, f, o); --=20 2.14.3