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Iglesias" , Fam Zheng Subject: [PATCH v13 19/30] sdhci: implement the Host Control 2 register (tuning sequence) Date: Tue, 13 Feb 2018 01:07:58 -0300 Message-Id: <20180213040809.26021-20-f4bug@amsat.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180213040809.26021-1-f4bug@amsat.org> References: <20180213040809.26021-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZohoMail: RDKM_0 RSF_0 Z_629925259 SPT_0 [based on a patch from Alistair Francis from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 10 ++++++++++ include/hw/sd/sdhci.h | 1 + hw/sd/sdhci.c | 22 +++++++++++++++++++--- 3 files changed, 30 insertions(+), 3 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index bfb39d614b..5c69270988 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -189,6 +189,16 @@ FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR, 1, 1); FIELD(SDHC_ACMD12ERRSTS, CRC_ERR, 2, 1); FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1); =20 +/* Host Control Register 2 (since v3) */ +#define SDHC_HOSTCTL2 0x3E +FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL, 0, 3); +FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1); +FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1); + /* HWInit Capabilities Register 0x05E80080 */ #define SDHC_CAPAB 0x40 FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6); diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 54594845ce..fd606e9928 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -73,6 +73,7 @@ typedef struct SDHCIState { uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */ uint16_t errintsigen; /* Error Interrupt Signal Enable Register */ uint16_t acmd12errsts; /* Auto CMD12 error status register */ + uint16_t hostctl2; /* Host Control 2 */ uint64_t admasysaddr; /* ADMA System Address Register */ =20 /* Read-only registers */ diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 9a8cdd551c..1dbcb99f52 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -408,14 +408,29 @@ static void sdhci_end_transfer(SDHCIState *s) static void sdhci_read_block_from_card(SDHCIState *s) { int index =3D 0; + uint8_t data; + const uint16_t blk_size =3D s->blksize & BLOCK_SIZE_MASK; =20 if ((s->trnmod & SDHC_TRNS_MULTI) && (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt =3D=3D 0)) { return; } =20 - for (index =3D 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) { - s->fifo_buffer[index] =3D sdbus_read_data(&s->sdbus); + for (index =3D 0; index < blk_size; index++) { + data =3D sdbus_read_data(&s->sdbus); + if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { + /* Device is not in tunning */ + s->fifo_buffer[index] =3D data; + } + } + + if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { + /* Device is in tunning */ + s->hostctl2 &=3D ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; + s->hostctl2 |=3D R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; + s->prnsts &=3D ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | + SDHC_DATA_INHIBIT); + goto read_done; } =20 /* New data now available for READ through Buffer Port Register */ @@ -440,6 +455,7 @@ static void sdhci_read_block_from_card(SDHCIState *s) } } =20 +read_done: sdhci_update_irq(s); } =20 @@ -1005,7 +1021,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offse= t, unsigned size) ret =3D s->norintsigen | (s->errintsigen << 16); break; case SDHC_ACMD12ERRSTS: - ret =3D s->acmd12errsts; + ret =3D s->acmd12errsts | (s->hostctl2 << 16); break; case SDHC_CAPAB: ret =3D (uint32_t)s->capareg; --=20 2.16.1