From nobody Tue Feb 10 02:28:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of _spf.google.com designates 209.85.220.195 as permitted sender) client-ip=209.85.220.195; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-qk0-f195.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of _spf.google.com designates 209.85.220.195 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-qk0-f195.google.com (mail-qk0-f195.google.com [209.85.220.195]) by mx.zohomail.com with SMTPS id 1518494955111108.73353165372703; Mon, 12 Feb 2018 20:09:15 -0800 (PST) Received: by mail-qk0-f195.google.com with SMTP id n188so21057929qkn.11 for ; Mon, 12 Feb 2018 20:09:14 -0800 (PST) Return-Path: Return-Path: Received: from x1.local ([138.117.48.219]) by smtp.gmail.com with ESMTPSA id q2sm7350435qki.10.2018.02.12.20.09.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Feb 2018 20:09:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x3xRuCz5oAMlz8xBc1AR1pWqfZdkWnVa+b8snqcVGb0=; b=Uq/L8JAX3plWvKRfXASw7Hsa+HD8eK3NW0fvIsIg778AVlnyS6Rh3DPdtFS3p7HYBc X8OX63kUoq0aulGVfardIs9mY55BugyuwvoIwoe+1VxN7SXGJXYeHkmF2K9if2r3B/sQ vmOMNeen258gTLItZSp0iQlgLPYevommpe59jwWkRItb8ZN6JAbSqaU0PXBuTkbe8SIG qlxBnIm5uWKdtTNmGLItrXKTWi6ux44mVDD1sdeFsBs20hvO2h3RB/QQ2qU7habb3fRm Csh+SPJXyhsJzWxOHoi6DgTVrW/v7mt7DKd2WvfAz9e4aWhgSp4VFsk6Jv3+pP4gXTES sVUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=x3xRuCz5oAMlz8xBc1AR1pWqfZdkWnVa+b8snqcVGb0=; b=gVa4Q7UwoVeLeoX/mulOJiYOkKIL+x7S11YpHVSnHJYlrt4SKKhODr/GFDhW7ZQAv4 ovubpkwCmOyNPGcF8JOwNxtuNvXQYA9TDxpMjFo3uh3vVCg2zll/G+RBSTTh57/FnFAv d9t/FlJcIJOLE9hOu3tsE4K+quB7q3hREnhE0TFN6J5jeIFbK5k1RWmk/RJ6qxbTEkZB gXA2nvjxWnpCdNHQM/x/cPj5sWeqsi+FOLlWOHXu8wOdTsQj/eGSJ5Qvau0G2W9nWd3U NOtSQ4OmOjTr7qJPR6B+A6Qfxl4MqDN2iQLY0oFdFUQl6am0LoFf2VHFbQetRGMuegMP JA2w== X-Gm-Message-State: APf1xPDrglCXhsW2vNW21pxWLQbXm8HfrakfAG3Y19drRpuDq9B9fxv7 NF/M52BV1hID1pOFRBYmS/s= X-Google-Smtp-Source: AH8x225tsMgEHPYH48KKecDbApzHPUezTtNwkCnQRzQDMJ5tKvuAwTCclT/AVmAUCTxWw0/OkVIfUQ== X-Received: by 10.55.98.149 with SMTP id w143mr3851836qkb.338.1518494954091; Mon, 12 Feb 2018 20:09:14 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , Fam Zheng Subject: [PATCH v13 17/30] sdhci: add support for v3 capabilities Date: Tue, 13 Feb 2018 01:07:56 -0300 Message-Id: <20180213040809.26021-18-f4bug@amsat.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180213040809.26021-1-f4bug@amsat.org> References: <20180213040809.26021-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZohoMail: RDKM_0 RSF_0 Z_629925259 SPT_0 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 13 ++++++++++++ hw/sd/sdhci.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++= ++-- 2 files changed, 65 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index fe68b21e92..bfb39d614b 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -43,6 +43,7 @@ #define SDHC_TRNS_DMA 0x0001 #define SDHC_TRNS_BLK_CNT_EN 0x0002 #define SDHC_TRNS_ACMD12 0x0004 +#define SDHC_TRNS_ACMD23 0x0008 /* since v3 */ #define SDHC_TRNS_READ 0x0010 #define SDHC_TRNS_MULTI 0x0020 #define SDHC_TRNMOD_MASK 0x0037 @@ -194,6 +195,7 @@ FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6); FIELD(SDHC_CAPAB, TOUNIT, 7, 1); FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8); FIELD(SDHC_CAPAB, MAXBLOCKLENGTH, 16, 2); +FIELD(SDHC_CAPAB, EMBEDDED_8BIT, 18, 1); /* since v3 */ FIELD(SDHC_CAPAB, ADMA2, 19, 1); /* since v2 */ FIELD(SDHC_CAPAB, ADMA1, 20, 1); /* v1 only? */ FIELD(SDHC_CAPAB, HIGHSPEED, 21, 1); @@ -203,6 +205,17 @@ FIELD(SDHC_CAPAB, V33, 24, 1); FIELD(SDHC_CAPAB, V30, 25, 1); FIELD(SDHC_CAPAB, V18, 26, 1); FIELD(SDHC_CAPAB, BUS64BIT, 28, 1); /* since v2 */ +FIELD(SDHC_CAPAB, ASYNC_INT, 29, 1); /* since v3 */ +FIELD(SDHC_CAPAB, SLOT_TYPE, 30, 2); /* since v3 */ +FIELD(SDHC_CAPAB, BUS_SPEED, 32, 3); /* since v3 */ +FIELD(SDHC_CAPAB, DRIVER_STRENGTH, 36, 3); /* since v3 */ +FIELD(SDHC_CAPAB, DRIVER_TYPE_A, 36, 1); /* since v3 */ +FIELD(SDHC_CAPAB, DRIVER_TYPE_C, 37, 1); /* since v3 */ +FIELD(SDHC_CAPAB, DRIVER_TYPE_D, 38, 1); /* since v3 */ +FIELD(SDHC_CAPAB, TIMER_RETUNING, 40, 4); /* since v3 */ +FIELD(SDHC_CAPAB, SDR50_TUNING, 45, 1); /* since v3 */ +FIELD(SDHC_CAPAB, RETUNING_MODE, 46, 2); /* since v3 */ +FIELD(SDHC_CAPAB, CLOCK_MULT, 48, 8); /* since v3 */ =20 /* HWInit Maximum Current Capabilities Register 0x0 */ #define SDHC_MAXCURR 0x48 diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index a0775e266a..e7214d6f60 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -69,6 +69,9 @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *= s) static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, uint8_t freq, Error **errp) { + if (s->sd_spec_version >=3D 3) { + return false; + } switch (freq) { case 0: case 10 ... 63: @@ -88,6 +91,50 @@ static void sdhci_check_capareg(SDHCIState *s, Error **e= rrp) bool unit_mhz; =20 switch (s->sd_spec_version) { + case 3: + val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); + trace_sdhci_capareg("async interrupt", val); + msk =3D FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); + + val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); + if (val) { + error_setg(errp, "slot-type not supported"); + return; + } + trace_sdhci_capareg("slot type", val); + msk =3D FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); + + if (val !=3D 0b10) { + val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); + trace_sdhci_capareg("8-bit bus", val); + } + msk =3D FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); + + val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); + trace_sdhci_capareg("bus speed mask", val); + msk =3D FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); + + val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); + trace_sdhci_capareg("driver strength mask", val); + msk =3D FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); + + val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); + trace_sdhci_capareg("timer re-tuning", val); + msk =3D FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); + + val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); + trace_sdhci_capareg("use SDR50 tuning", val); + msk =3D FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); + + val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); + trace_sdhci_capareg("re-tuning mode", val); + msk =3D FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); + + val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); + trace_sdhci_capareg("clock multiplier", val); + msk =3D FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); + + /* fallback */ case 2: /* default version */ val =3D FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); msk =3D FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); @@ -1227,8 +1274,11 @@ static void sdhci_init_readonly_registers(SDHCIState= *s, Error **errp) { Error *local_err =3D NULL; =20 - if (s->sd_spec_version !=3D 2) { - error_setg(errp, "Only Spec v2 is supported"); + switch (s->sd_spec_version) { + case 2 ... 3: + break; + default: + error_setg(errp, "Only Spec v2/v3 are supported"); return; } s->version =3D (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); --=20 2.16.1