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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id y129sm8850354pgb.27.2018.02.11.12.59.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 11 Feb 2018 12:59:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XNE6HRogROpjH970mSZvci6V/G9pwgU/mAd5NppeIP0=; b=Ay9geIMU7SCGT2QjCa77oVuAxxIqykoEwuHiZ1b8TQsyySc7FR/3P6IQ9BKnnIsAkA H8DZT3nSvg8G2+0QH1MfLl0PvSt7cVzYyDZGTA/z+xvCaLNEj5C/4WhMV/MiftwUZV9t tt/nsK+bey9EJg7+ILTE/kn4zFbQVXw8iXqho= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XNE6HRogROpjH970mSZvci6V/G9pwgU/mAd5NppeIP0=; b=cs5lNd84yVYXtn+BxkI7J9tGpJgk1v9NG8EMgz8eaB/m+Z6NxZPsi/eAZB5gwh9xRx Tzke039aofGXm0EVKl/GubgbtBXDtOLuo4Kzhs/1TIReDGxmQpzXMSYDmAGt4Qd8POzF 4tTnew8UKtSx0Fwk17g0ppRuvD85dE/8qhKtOlh9i3B0CIaWOecavOsoL9XXp9XXGVH2 csnN7l63sMnkpkssrz3cg+o+9cfrOP92c14PuCU15TuvrFLJUjB3Z6RSybwdTufz7Tw5 VbKp1XTlRBHXMt5RLyBQe5vt35GQzU2dgV9VFyKmAF+RmH+kNIdxUkwiXKl5rhGj8hlE kkeg== X-Gm-Message-State: APf1xPAIpY3tKTRlOwjeV4li3N4jgfZ5XgHwPfSFwwsBiD3/V5XO07rY ynAVidxk5jUZcBGUQ2WUdAURtI3BVtI= X-Google-Smtp-Source: AH8x224Vp1EA7bd2DItVGeElKXkoCfEU6wEsFDbiOI+0M1q1UvEvzpWbywmImRgiDsYHXnLuuqwywA== X-Received: by 2002:a17:902:7297:: with SMTP id d23-v6mr2607507pll.417.1518382741763; Sun, 11 Feb 2018 12:59:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 11 Feb 2018 12:58:48 -0800 Message-Id: <20180211205848.4568-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180211205848.4568-1-richard.henderson@linaro.org> References: <20180211205848.4568-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v2 7/7] linux-user: Implement aarch64 PR_SVE_SET/GET_VL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As an implementation choice, widening VL has zeroed the previously inaccessible portion of the sve registers. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ linux-user/syscall.c | 20 +++++++++++++++++ target/arm/cpu64.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 83 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 51a3e16275..8e1016cfd6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -842,6 +842,8 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, C= PUState *cs, #ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +unsigned aarch64_get_sve_vlen(CPUARMState *env); +unsigned aarch64_set_sve_vlen(CPUARMState *env, unsigned vlen); #endif =20 target_ulong do_arm_semihosting(CPUARMState *env); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 82b35a6bdf..4840bf502f 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10659,6 +10659,26 @@ abi_long do_syscall(void *cpu_env, int num, abi_lo= ng arg1, break; } #endif +#ifdef TARGET_AARCH64 + case 50: /* PR_SVE_SET_VL */ + /* We cannot support either PR_SVE_SET_VL_ONEXEC + or PR_SVE_VL_INHERIT. Therefore, anything above + ARM_MAX_VQ results in EINVAL. */ + if (!arm_feature(cpu_env, ARM_FEATURE_SVE) + || arg2 > ARM_MAX_VQ * 16 || arg2 & 15) { + ret =3D -TARGET_EINVAL; + } else { + ret =3D aarch64_set_sve_vlen(cpu_env, arg2); + } + break; + case 51: /* PR_SVE_GET_VL */ + if (arm_feature(cpu_env, ARM_FEATURE_SVE)) { + ret =3D aarch64_get_sve_vlen(cpu_env); + } else { + ret =3D -TARGET_EINVAL; + } + break; +#endif /* AARCH64 */ case PR_GET_SECCOMP: case PR_SET_SECCOMP: /* Disable seccomp to prevent the target disabling syscalls we diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1c330adc28..6dee78f006 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -363,3 +363,64 @@ static void aarch64_cpu_register_types(void) } =20 type_init(aarch64_cpu_register_types) + +/* Return the current cumulative SVE VLEN. */ +unsigned aarch64_get_sve_vlen(CPUARMState *env) +{ + return ((env->vfp.zcr_el[1] & 0xf) + 1) * 16; +} + +/* Set the cumulative ZCR.EL to VLEN, or the nearest supported value. + Return the new value. */ +unsigned aarch64_set_sve_vlen(CPUARMState *env, unsigned vl) +{ + unsigned vq =3D vl / 16; + unsigned old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + + if (vq < 1) { + vq =3D 1; + } else if (vq > ARM_MAX_VQ) { + vq =3D ARM_MAX_VQ; + } + env->vfp.zcr_el[1] =3D vq - 1; + + /* The manual sez that when SVE is enabled and VL is widened the + * implementation is allowed to zero the previously inaccessible + * portion of the registers. The corollary to that is that when + * SVE is enabled and VL is narrowed we are also allowed to zero + * the now inaccessible portion of the registers. + * + * The intent of this is that no predicate bit beyond VL is ever set. + * Which means that some operations on predicate registers themselves + * may operate on full uint64_t or even unrolled across the maximum + * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally + * may well be cheaper than conditionals to restrict to the operation + * to the relevant portion of a uint16_t[16]. + * + * ??? Need to move this somewhere else, so that it applies to + * changes to the real system registers and EL state changes. + */ + if (vq < old_vq) { + unsigned i, j; + uint64_t pmask; + + /* Zap the high bits of the zregs. */ + for (i =3D 0; i < 32; i++) { + memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)= ); + } + + /* Zap the high bits of the pregs and ffr. */ + pmask =3D 0; + if (vq & 3) { + pmask =3D ~(-1ULL << (16 * (vq & 3))); + } + for (j =3D vq / 4; j < ARM_MAX_VQ / 4; j++) { + for (i =3D 0; i < 17; ++i) { + env->vfp.pregs[i].p[j] &=3D pmask; + } + pmask =3D 0; + } + } + + return vq * 16; +} --=20 2.14.3