From nobody Thu Dec 18 17:55:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518175306263186.70683975354234; Fri, 9 Feb 2018 03:21:46 -0800 (PST) Received: from localhost ([::1]:34950 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ek6kT-0008Aa-9y for importer@patchew.org; Fri, 09 Feb 2018 06:21:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39879) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ek6St-000147-Ja for qemu-devel@nongnu.org; Fri, 09 Feb 2018 06:03:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ek6Ss-00021D-N5 for qemu-devel@nongnu.org; Fri, 09 Feb 2018 06:03:35 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46262) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ek6Ss-0001zI-Gr for qemu-devel@nongnu.org; Fri, 09 Feb 2018 06:03:34 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ek6Sr-0002du-Js for qemu-devel@nongnu.org; Fri, 09 Feb 2018 11:03:33 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 9 Feb 2018 11:03:09 +0000 Message-Id: <20180209110314.11766-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209110314.11766-1-peter.maydell@linaro.org> References: <20180209110314.11766-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 25/30] target/arm: Add SVE to migration state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Richard Henderson Save the high parts of the Zregs and all of the Pregs. The ZCR_ELx registers are migrated via the CP mechanism. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Message-id: 20180123035349.24538-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/machine.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 53 insertions(+) diff --git a/target/arm/machine.c b/target/arm/machine.c index cb0e1c92bb..2c8b43062f 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -122,6 +122,56 @@ static const VMStateDescription vmstate_iwmmxt =3D { } }; =20 +#ifdef TARGET_AARCH64 +/* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, + * and ARMPredicateReg is actively empty. This triggers errors + * in the expansion of the VMSTATE macros. + */ + +static bool sve_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_SVE); +} + +/* The first two words of each Zreg is stored in VFP state. */ +static const VMStateDescription vmstate_zreg_hi_reg =3D { + .name =3D "cpu/sve/zreg_hi", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_preg_reg =3D { + .name =3D "cpu/sve/preg", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_sve =3D { + .name =3D "cpu/sve", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D sve_needed, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, + vmstate_zreg_hi_reg, ARMVectorReg), + VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, + vmstate_preg_reg, ARMPredicateReg), + VMSTATE_END_OF_LIST() + } +}; +#endif /* AARCH64 */ + static bool m_needed(void *opaque) { ARMCPU *cpu =3D opaque; @@ -586,6 +636,9 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_pmsav7, &vmstate_pmsav8, &vmstate_m_security, +#ifdef TARGET_AARCH64 + &vmstate_sve, +#endif NULL } }; --=20 2.16.1