From nobody Thu Dec 18 19:32:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518175111234204.04412636390646; Fri, 9 Feb 2018 03:18:31 -0800 (PST) Received: from localhost ([::1]:34929 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ek6hK-00053y-AY for importer@patchew.org; Fri, 09 Feb 2018 06:18:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ek6Sq-00012k-UX for qemu-devel@nongnu.org; Fri, 09 Feb 2018 06:03:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ek6Sp-0001yk-Eg for qemu-devel@nongnu.org; Fri, 09 Feb 2018 06:03:32 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46260) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ek6Sp-0001y8-4f for qemu-devel@nongnu.org; Fri, 09 Feb 2018 06:03:31 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ek6So-0002cg-5C for qemu-devel@nongnu.org; Fri, 09 Feb 2018 11:03:30 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 9 Feb 2018 11:03:04 +0000 Message-Id: <20180209110314.11766-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209110314.11766-1-peter.maydell@linaro.org> References: <20180209110314.11766-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 20/30] i.MX: Add implementation of i.MX7 GPR IP block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Andrey Smirnov Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daud=C3=A9 Cc: Marcel Apfelbaum Cc: Michael S. Tsirkin Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Andrey Smirnov Signed-off-by: Peter Maydell --- hw/misc/Makefile.objs | 1 + include/hw/misc/imx7_gpr.h | 28 ++++++++++ hw/misc/imx7_gpr.c | 124 +++++++++++++++++++++++++++++++++++++++++= ++++ hw/misc/trace-events | 4 ++ 4 files changed, 157 insertions(+) create mode 100644 include/hw/misc/imx7_gpr.h create mode 100644 hw/misc/imx7_gpr.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 019886912c..fce426eb75 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -36,6 +36,7 @@ obj-$(CONFIG_IMX) +=3D imx6_src.o obj-$(CONFIG_IMX) +=3D imx7_ccm.o obj-$(CONFIG_IMX) +=3D imx2_wdt.o obj-$(CONFIG_IMX) +=3D imx7_snvs.o +obj-$(CONFIG_IMX) +=3D imx7_gpr.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-hpdmc.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-pfpu.o obj-$(CONFIG_MAINSTONE) +=3D mst_fpga.o diff --git a/include/hw/misc/imx7_gpr.h b/include/hw/misc/imx7_gpr.h new file mode 100644 index 0000000000..e19373d274 --- /dev/null +++ b/include/hw/misc/imx7_gpr.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 GPR IP block emulation code + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef IMX7_GPR_H +#define IMX7_GPR_H + +#include "qemu/bitops.h" +#include "hw/sysbus.h" + +#define TYPE_IMX7_GPR "imx7.gpr" +#define IMX7_GPR(obj) OBJECT_CHECK(IMX7GPRState, (obj), TYPE_IMX7_GPR) + +typedef struct IMX7GPRState { + /* */ + SysBusDevice parent_obj; + + MemoryRegion mmio; +} IMX7GPRState; + +#endif /* IMX7_GPR_H */ diff --git a/hw/misc/imx7_gpr.c b/hw/misc/imx7_gpr.c new file mode 100644 index 0000000000..c2a9df29c6 --- /dev/null +++ b/hw/misc/imx7_gpr.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2018, Impinj, Inc. + * + * i.MX7 GPR IP block emulation code + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + * Bare minimum emulation code needed to support being able to shut + * down linux guest gracefully. + */ + +#include "qemu/osdep.h" +#include "hw/misc/imx7_gpr.h" +#include "qemu/log.h" +#include "sysemu/sysemu.h" + +#include "trace.h" + +enum IMX7GPRRegisters { + IOMUXC_GPR0 =3D 0x00, + IOMUXC_GPR1 =3D 0x04, + IOMUXC_GPR2 =3D 0x08, + IOMUXC_GPR3 =3D 0x0c, + IOMUXC_GPR4 =3D 0x10, + IOMUXC_GPR5 =3D 0x14, + IOMUXC_GPR6 =3D 0x18, + IOMUXC_GPR7 =3D 0x1c, + IOMUXC_GPR8 =3D 0x20, + IOMUXC_GPR9 =3D 0x24, + IOMUXC_GPR10 =3D 0x28, + IOMUXC_GPR11 =3D 0x2c, + IOMUXC_GPR12 =3D 0x30, + IOMUXC_GPR13 =3D 0x34, + IOMUXC_GPR14 =3D 0x38, + IOMUXC_GPR15 =3D 0x3c, + IOMUXC_GPR16 =3D 0x40, + IOMUXC_GPR17 =3D 0x44, + IOMUXC_GPR18 =3D 0x48, + IOMUXC_GPR19 =3D 0x4c, + IOMUXC_GPR20 =3D 0x50, + IOMUXC_GPR21 =3D 0x54, + IOMUXC_GPR22 =3D 0x58, +}; + +#define IMX7D_GPR1_IRQ_MASK BIT(12) +#define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK BIT(13) +#define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK BIT(14) +#define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13) +#define IMX7D_GPR1_ENET1_CLK_DIR_MASK BIT(17) +#define IMX7D_GPR1_ENET2_CLK_DIR_MASK BIT(18) +#define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17) + +#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI BIT(4) +#define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5) +#define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31) + + +static uint64_t imx7_gpr_read(void *opaque, hwaddr offset, unsigned size) +{ + trace_imx7_gpr_read(offset); + + if (offset =3D=3D IOMUXC_GPR22) { + return IMX7D_GPR22_PCIE_PHY_PLL_LOCKED; + } + + return 0; +} + +static void imx7_gpr_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ + trace_imx7_gpr_write(offset, v); +} + +static const struct MemoryRegionOps imx7_gpr_ops =3D { + .read =3D imx7_gpr_read, + .write =3D imx7_gpr_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + /* + * Our device would not work correctly if the guest was doing + * unaligned access. This might not be a limitation on the + * real device but in practice there is no reason for a guest + * to access this device unaligned. + */ + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void imx7_gpr_init(Object *obj) +{ + SysBusDevice *sd =3D SYS_BUS_DEVICE(obj); + IMX7GPRState *s =3D IMX7_GPR(obj); + + memory_region_init_io(&s->mmio, obj, &imx7_gpr_ops, s, + TYPE_IMX7_GPR, 64 * 1024); + sysbus_init_mmio(sd, &s->mmio); +} + +static void imx7_gpr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "i.MX7 General Purpose Registers Module"; +} + +static const TypeInfo imx7_gpr_info =3D { + .name =3D TYPE_IMX7_GPR, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IMX7GPRState), + .instance_init =3D imx7_gpr_init, + .class_init =3D imx7_gpr_class_init, +}; + +static void imx7_gpr_register_type(void) +{ + type_register_static(&imx7_gpr_info); +} +type_init(imx7_gpr_register_type) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 616579a403..e6070f280d 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -66,3 +66,7 @@ mps2_scc_cfg_read(unsigned function, unsigned device, uin= t32_t value) "MPS2 SCC msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysr= eg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32 msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x= %08" HWADDR_PRIx " data 0x%08" PRIx32 msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status = register" + +#hw/misc/imx7_gpr.c +imx7_gpr_read(uint64_t offset) "addr 0x%08" HWADDR_PRIx +imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" HWADDR_PRIx "= value 0x%08" HWADDR_PRIx --=20 2.16.1