From nobody Thu Dec 18 19:30:38 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518174537753348.8111619767051; Fri, 9 Feb 2018 03:08:57 -0800 (PST) Received: from localhost ([::1]:34870 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ek6Y2-0005BP-Lu for importer@patchew.org; Fri, 09 Feb 2018 06:08:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39655) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ek6Sk-0000x3-K4 for qemu-devel@nongnu.org; Fri, 09 Feb 2018 06:03:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ek6Sj-0001tT-8U for qemu-devel@nongnu.org; Fri, 09 Feb 2018 06:03:26 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46250) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ek6Sj-0001oy-0d for qemu-devel@nongnu.org; Fri, 09 Feb 2018 06:03:25 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ek6Sg-0002Zg-Fa for qemu-devel@nongnu.org; Fri, 09 Feb 2018 11:03:22 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 9 Feb 2018 11:02:54 +0000 Message-Id: <20180209110314.11766-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209110314.11766-1-peter.maydell@linaro.org> References: <20180209110314.11766-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/30] target/arm: implement SM3 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel This implements emulation of the new SM3 instructions that have been added as an optional extension to the ARMv8 Crypto Extensions in ARM v8.2. Signed-off-by: Ard Biesheuvel Message-id: 20180207111729.15737-4-ard.biesheuvel@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/helper.h | 4 ++ target/arm/crypto_helper.c | 96 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++++++++++++-- 4 files changed, 186 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 86411320aa..f63b6e174a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1343,6 +1343,7 @@ enum arm_features { ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensio= ns */ ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ + ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/helper.h b/target/arm/helper.h index 81d4607028..9d9f42cc89 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -539,6 +539,10 @@ DEF_HELPER_FLAGS_3(crypto_sha512h2, TCG_CALL_NO_RWG, v= oid, ptr, ptr, ptr) DEF_HELPER_FLAGS_2(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr) DEF_HELPER_FLAGS_3(crypto_sha512su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32= , i32) +DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) + DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(dc_zva, void, env, i64) diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index 3d8d1fb5e7..2f6744edb0 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -507,3 +507,99 @@ void HELPER(crypto_sha512su1)(void *vd, void *vn, void= *vm) rd[0] +=3D s1_512(rn[0]) + rm[0]; rd[1] +=3D s1_512(rn[1]) + rm[1]; } + +void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; + uint32_t t; + + t =3D CR_ST_WORD(d, 0) ^ CR_ST_WORD(n, 0) ^ ror32(CR_ST_WORD(m, 1), 17= ); + CR_ST_WORD(d, 0) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + t =3D CR_ST_WORD(d, 1) ^ CR_ST_WORD(n, 1) ^ ror32(CR_ST_WORD(m, 2), 17= ); + CR_ST_WORD(d, 1) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + t =3D CR_ST_WORD(d, 2) ^ CR_ST_WORD(n, 2) ^ ror32(CR_ST_WORD(m, 3), 17= ); + CR_ST_WORD(d, 2) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + t =3D CR_ST_WORD(d, 3) ^ CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(d, 0), 17= ); + CR_ST_WORD(d, 3) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} + +void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; + uint32_t t =3D CR_ST_WORD(n, 0) ^ ror32(CR_ST_WORD(m, 0), 25); + + CR_ST_WORD(d, 0) ^=3D t; + CR_ST_WORD(d, 1) ^=3D CR_ST_WORD(n, 1) ^ ror32(CR_ST_WORD(m, 1), 25); + CR_ST_WORD(d, 2) ^=3D CR_ST_WORD(n, 2) ^ ror32(CR_ST_WORD(m, 2), 25); + CR_ST_WORD(d, 3) ^=3D CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(m, 3), 25) ^ + ror32(t, 17) ^ ror32(t, 2) ^ ror32(t, 26); + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} + +void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2, + uint32_t opcode) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; + uint32_t t; + + assert(imm2 < 4); + + if (opcode =3D=3D 0 || opcode =3D=3D 2) { + /* SM3TT1A, SM3TT2A */ + t =3D par(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1)); + } else if (opcode =3D=3D 1) { + /* SM3TT1B */ + t =3D maj(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1)); + } else if (opcode =3D=3D 3) { + /* SM3TT2B */ + t =3D cho(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1)); + } else { + g_assert_not_reached(); + } + + t +=3D CR_ST_WORD(d, 0) + CR_ST_WORD(m, imm2); + + CR_ST_WORD(d, 0) =3D CR_ST_WORD(d, 1); + + if (opcode < 2) { + /* SM3TT1A, SM3TT1B */ + t +=3D CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(d, 3), 20); + + CR_ST_WORD(d, 1) =3D ror32(CR_ST_WORD(d, 2), 23); + } else { + /* SM3TT2A, SM3TT2B */ + t +=3D CR_ST_WORD(n, 3); + t ^=3D rol32(t, 9) ^ rol32(t, 17); + + CR_ST_WORD(d, 1) =3D ror32(CR_ST_WORD(d, 2), 13); + } + + CR_ST_WORD(d, 2) =3D CR_ST_WORD(d, 3); + CR_ST_WORD(d, 3) =3D t; + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 19804fd110..2f8b4e6150 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11623,8 +11623,19 @@ static void disas_crypto_three_reg_sha512(DisasCon= text *s, uint32_t insn) break; } } else { - unallocated_encoding(s); - return; + switch (opcode) { + case 0: /* SM3PARTW1 */ + feature =3D ARM_FEATURE_V8_SM3; + genfn =3D gen_helper_crypto_sm3partw1; + break; + case 1: /* SM3PARTW2 */ + feature =3D ARM_FEATURE_V8_SM3; + genfn =3D gen_helper_crypto_sm3partw2; + break; + default: + unallocated_encoding(s); + return; + } } =20 if (!arm_dc_feature(s, feature)) { @@ -11737,6 +11748,9 @@ static void disas_crypto_four_reg(DisasContext *s, = uint32_t insn) case 1: /* BCAX */ feature =3D ARM_FEATURE_V8_SHA3; break; + case 2: /* SM3SS1 */ + feature =3D ARM_FEATURE_V8_SM3; + break; default: unallocated_encoding(s); return; @@ -11784,7 +11798,33 @@ static void disas_crypto_four_reg(DisasContext *s,= uint32_t insn) tcg_temp_free_i64(tcg_res[0]); tcg_temp_free_i64(tcg_res[1]); } else { - g_assert_not_reached(); + TCGv_i32 tcg_op1, tcg_op2, tcg_op3, tcg_res, tcg_zero; + + tcg_op1 =3D tcg_temp_new_i32(); + tcg_op2 =3D tcg_temp_new_i32(); + tcg_op3 =3D tcg_temp_new_i32(); + tcg_res =3D tcg_temp_new_i32(); + tcg_zero =3D tcg_const_i32(0); + + read_vec_element_i32(s, tcg_op1, rn, 3, MO_32); + read_vec_element_i32(s, tcg_op2, rm, 3, MO_32); + read_vec_element_i32(s, tcg_op3, ra, 3, MO_32); + + tcg_gen_rotri_i32(tcg_res, tcg_op1, 20); + tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2); + tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3); + tcg_gen_rotri_i32(tcg_res, tcg_res, 25); + + write_vec_element_i32(s, tcg_zero, rd, 0, MO_32); + write_vec_element_i32(s, tcg_zero, rd, 1, MO_32); + write_vec_element_i32(s, tcg_zero, rd, 2, MO_32); + write_vec_element_i32(s, tcg_res, rd, 3, MO_32); + + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + tcg_temp_free_i32(tcg_op3); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_zero); } } =20 @@ -11833,6 +11873,47 @@ static void disas_crypto_xar(DisasContext *s, uint= 32_t insn) tcg_temp_free_i64(tcg_res[1]); } =20 +/* Crypto three-reg imm2 + * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 + * +-----------------------+------+-----+------+--------+------+------+ + * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd | + * +-----------------------+------+-----+------+--------+------+------+ + */ +static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) +{ + int opcode =3D extract32(insn, 10, 2); + int imm2 =3D extract32(insn, 12, 2); + int rm =3D extract32(insn, 16, 5); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; + TCGv_i32 tcg_imm2, tcg_opcode; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_SM3)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); + tcg_rm_ptr =3D vec_full_reg_ptr(s, rm); + tcg_imm2 =3D tcg_const_i32(imm2); + tcg_opcode =3D tcg_const_i32(opcode); + + gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2, + tcg_opcode); + + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); + tcg_temp_free_ptr(tcg_rm_ptr); + tcg_temp_free_i32(tcg_imm2); + tcg_temp_free_i32(tcg_opcode); +} + /* C3.6 Data processing - SIMD, inc Crypto * * As the decode gets a little complex we are using a table based @@ -11866,6 +11947,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, { 0xce000000, 0xff808000, disas_crypto_four_reg }, { 0xce800000, 0xffe00000, disas_crypto_xar }, + { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.16.1