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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v2 06/32] target/arm/helper: pass explicit fpst to set_rmode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 As the rounding mode is now split between FP16 and the rest of floating point we need to be explicit when tweaking it. Instead of passing the CPU env we now pass the appropriate fpst pointer directly. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper.c | 4 ++-- target/arm/helper.h | 2 +- target/arm/translate-a64.c | 26 +++++++++++++------------- target/arm/translate.c | 12 ++++++------ 4 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1cc3d43a9f..72522c125c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10974,9 +10974,9 @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) /* Set the current fp rounding mode and return the old one. * The argument is a softfloat float_round_ value. */ -uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) +uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) { - float_status *fp_status =3D &env->vfp.fp_status; + float_status *fp_status =3D fpstp; =20 uint32_t prev_rmode =3D get_float_rounding_mode(fp_status); set_float_rounding_mode(rmode, fp_status); diff --git a/target/arm/helper.h b/target/arm/helper.h index 5dec2e6262..40dcd74cfd 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -167,7 +167,7 @@ DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) =20 -DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, env) +DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) =20 DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1afa669e6e..531ac5999c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4540,10 +4540,10 @@ static void handle_fp_1src_single(DisasContext *s, = int opcode, int rd, int rn) { TCGv_i32 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(opcode & 7)); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rints(tcg_res, tcg_op, fpst); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); break; } @@ -4596,10 +4596,10 @@ static void handle_fp_1src_double(DisasContext *s, = int opcode, int rd, int rn) { TCGv_i32 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(opcode & 7)); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rintd(tcg_res, tcg_op, fpst); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); break; } @@ -5126,7 +5126,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); =20 if (is_double) { TCGv_i64 tcg_double =3D read_fp_dreg(s, rn); @@ -5173,7 +5173,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, tcg_temp_free_i32(tcg_single); } =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); =20 if (!sf) { @@ -6946,8 +6946,8 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, assert(!(is_scalar && is_q)); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); tcg_fpstatus =3D get_fpstatus_ptr(false); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_shift =3D tcg_const_i32(fracbits); =20 if (is_double) { @@ -6993,7 +6993,7 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, =20 tcg_temp_free_ptr(tcg_fpstatus); tcg_temp_free_i32(tcg_shift); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); } =20 @@ -8262,8 +8262,8 @@ static void disas_simd_scalar_two_reg_misc(DisasConte= xt *s, uint32_t insn) =20 if (is_fcvt) { tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); tcg_fpstatus =3D get_fpstatus_ptr(false); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); } else { tcg_rmode =3D NULL; tcg_fpstatus =3D NULL; @@ -8328,7 +8328,7 @@ static void disas_simd_scalar_two_reg_misc(DisasConte= xt *s, uint32_t insn) } =20 if (is_fcvt) { - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_ptr(tcg_fpstatus); } @@ -10249,14 +10249,14 @@ static void disas_simd_two_reg_misc(DisasContext = *s, uint32_t insn) return; } =20 - if (need_fpstatus) { + if (need_fpstatus || need_rmode) { tcg_fpstatus =3D get_fpstatus_ptr(false); } else { tcg_fpstatus =3D NULL; } if (need_rmode) { tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); } else { tcg_rmode =3D NULL; } @@ -10485,7 +10485,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) } =20 if (need_rmode) { - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); } if (need_fpstatus) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 55826b7e5a..9aee67f067 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3144,7 +3144,7 @@ static int handle_vrint(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, TCGv_i32 tcg_rmode; =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); =20 if (dp) { TCGv_i64 tcg_op; @@ -3168,7 +3168,7 @@ static int handle_vrint(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, tcg_temp_free_i32(tcg_res); } =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); =20 tcg_temp_free_ptr(fpst); @@ -3185,7 +3185,7 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, ui= nt32_t rm, uint32_t dp, tcg_shift =3D tcg_const_i32(0); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); =20 if (dp) { TCGv_i64 tcg_double, tcg_res; @@ -3223,7 +3223,7 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, ui= nt32_t rm, uint32_t dp, tcg_temp_free_i32(tcg_single); } =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); =20 tcg_temp_free_i32(tcg_shift); @@ -3893,13 +3893,13 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) TCGv_ptr fpst =3D get_fpstatus_ptr(0); TCGv_i32 tcg_rmode; tcg_rmode =3D tcg_const_i32(float_round_to_zero); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env= ); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); if (dp) { gen_helper_rintd(cpu_F0d, cpu_F0d, fpst); } else { gen_helper_rints(cpu_F0s, cpu_F0s, fpst); } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env= ); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_ptr(fpst); break; --=20 2.15.1