From nobody Mon Feb 9 23:03:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518113422507724.8148946469227; Thu, 8 Feb 2018 10:10:22 -0800 (PST) Received: from localhost ([::1]:58371 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejqeG-0003Qz-08 for importer@patchew.org; Thu, 08 Feb 2018 13:10:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54611) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejq3a-0003Wq-Lm for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:32:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ejq3X-00070f-57 for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:32:22 -0500 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:52159) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ejq3W-0006z9-R4 for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:32:19 -0500 Received: by mail-wm0-x241.google.com with SMTP id r71so10969722wmd.1 for ; Thu, 08 Feb 2018 09:32:18 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id g127sm441215wmf.5.2018.02.08.09.32.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 09:32:11 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 2B5553E0D84; Thu, 8 Feb 2018 17:31:59 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9e/cIvJOEXVul/QTqPr7Bzfwdn7CVfZFq2X2Iak7uMg=; b=DUgQFcoCuDA7qlprprgKm5VUpaDXpRHuX2WDILZSmraVRKCX+5PQ+z9ZQhOVxpmDJp TzXb/2uj+yfVLLRbBFYbVpRzh2evkIpBrBSs4gon9OaVKeONlfuFqRLTB+HltdBMi45t D73D2Fs2hRInSYrhEL/ne01w6gBXH9tAfGfEA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9e/cIvJOEXVul/QTqPr7Bzfwdn7CVfZFq2X2Iak7uMg=; b=nWagxLusmFEyVjJ8QRqWl2X4JvAjWVFyqIJnwIkvEw3X0dSTcumUd94aODBeJJY3b2 N7foaWXv+Vd/AmpMgkSnzIwIfOrFpzqBffS+5fAEWRyRPpYrbD85BFUzwaHBAPdaNplG xTzUnIfwdCPkjr1lQlIxfShzqNkVWm7BTSkvJN1VUuvZNwKNI33LJmHrFE5Ql7p6nF1u NsFe56W8ZQlfNQHcJcYsmMxmjfqkq1qSFYgKGSSxgMbU4vwlUFSOWYBw/5X3IilGHWu1 YxIqyqA7fWBPKf9TneDFz0UQwRGdAYqzwikVDWL8DkNunrYX6gzFzkdg0uitG3p0BnlA pY5w== X-Gm-Message-State: APf1xPC/QCvwtJTk36V7grj/K1kXnH+WmU4E+++yiMHKJYoyUqILyrrY W3TtzIUf8z+0A9wx9PMUpvg2XyacmrA= X-Google-Smtp-Source: AH8x224e5VeMaHsjiF+rWliHaqmB85ICAekIa0lA2Z7J6KYuc70dgxpeWq3Mk7yWfmpa2Asc+OYE3g== X-Received: by 10.28.128.82 with SMTP id b79mr12682wmd.113.1518111137702; Thu, 08 Feb 2018 09:32:17 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Thu, 8 Feb 2018 17:31:44 +0000 Message-Id: <20180208173157.24705-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180208173157.24705-1-alex.bennee@linaro.org> References: <20180208173157.24705-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v2 19/32] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This covers all the floating point convert operations. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper-a64.c | 32 +++++++++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/translate-a64.c | 85 ++++++++++++++++++++++++++++++++++++++++++= +++- 3 files changed, 118 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 919b073635..76f3289e37 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -772,3 +772,35 @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_stat= us) =20 return ret; } + +/* + * Half-precision floating point conversion functions + * + * There are a multitude of conversion functions with various + * different rounding modes. This is dealt with by the calling code + * setting the mode appropriately before calling the helper. + */ + +uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp) +{ + float_status *fpst =3D fpstp; + + /* Invalid if we are passed a NaN */ + if (float16_is_any_nan(a)) { + float_raise(float_flag_invalid, fpst); + return 0; + } + return float16_to_int16(a, fpst); +} + +uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp) +{ + float_status *fpst =3D fpstp; + + /* Invalid if we are passed a NaN */ + if (float16_is_any_nan(a)) { + float_raise(float_flag_invalid, fpst); + return 0; + } + return float16_to_uint16(a, fpst); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index b583bc0dd8..453753f4e7 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -78,3 +78,5 @@ DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) +DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) +DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a0506f094f..0049111e6d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10797,6 +10797,46 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) only_in_vector =3D true; /* current rounding mode */ break; + case 0x1a: /* FCVTNS */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEEVEN; + break; + case 0x1b: /* FCVTMS */ + need_rmode =3D true; + rmode =3D FPROUNDING_NEGINF; + break; + case 0x1c: /* FCVTAS */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEAWAY; + break; + case 0x3a: /* FCVTPS */ + need_rmode =3D true; + rmode =3D FPROUNDING_POSINF; + break; + case 0x3b: /* FCVTZS */ + need_rmode =3D true; + rmode =3D FPROUNDING_ZERO; + break; + case 0x5a: /* FCVTNU */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEEVEN; + break; + case 0x5b: /* FCVTMU */ + need_rmode =3D true; + rmode =3D FPROUNDING_NEGINF; + break; + case 0x5c: /* FCVTAU */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEAWAY; + break; + case 0x7a: /* FCVTPU */ + need_rmode =3D true; + rmode =3D FPROUNDING_POSINF; + break; + case 0x7b: /* FCVTZU */ + need_rmode =3D true; + rmode =3D FPROUNDING_ZERO; + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); g_assert_not_reached(); @@ -10830,7 +10870,36 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) } =20 if (is_scalar) { - /* no operations yet */ + TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, 0, MO_16); + + switch (fpop) { + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ + gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x5a: /* FCVTNU */ + case 0x5b: /* FCVTMU */ + case 0x5c: /* FCVTAU */ + case 0x7a: /* FCVTPU */ + case 0x7b: /* FCVTZU */ + gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); + break; + default: + g_assert_not_reached(); + } + + /* limit any sign extension going on */ + tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff); + write_fp_sreg(s, rd, tcg_res); + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op); } else { for (pass =3D 0; pass < (is_q ? 8 : 4); pass++) { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); @@ -10839,6 +10908,20 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) read_vec_element_i32(s, tcg_op, rn, pass, MO_16); =20 switch (fpop) { + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ + gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatu= s); + break; + case 0x5a: /* FCVTNU */ + case 0x5b: /* FCVTMU */ + case 0x5c: /* FCVTAU */ + case 0x7a: /* FCVTPU */ + case 0x7b: /* FCVTZU */ + gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatu= s); + break; case 0x18: /* FRINTN */ case 0x19: /* FRINTM */ case 0x38: /* FRINTP */ --=20 2.15.1