From nobody Mon Feb 9 23:03:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15181129611801005.8785047467256; Thu, 8 Feb 2018 10:02:41 -0800 (PST) Received: from localhost ([::1]:58021 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejqWu-0005mR-Dc for importer@patchew.org; Thu, 08 Feb 2018 13:02:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57268) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejqBS-0002vv-Sh for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:40:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ejqBQ-0000QO-IQ for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:40:30 -0500 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:53307) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ejqBQ-0000Pt-7L for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:40:28 -0500 Received: by mail-wm0-x243.google.com with SMTP id t74so10991905wme.3 for ; Thu, 08 Feb 2018 09:40:28 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id a19sm573449wrg.9.2018.02.08.09.40.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 09:40:25 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 03ED13E0D1C; Thu, 8 Feb 2018 17:31:59 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=snCIeuHwZ2Iy8TQFZjGXmC1sKFnr41Jq+ozWnLy6cyY=; b=XdqQv03OrRmihNKbaLNJ+Lsvw1PMRSQ9uqvLjw0mnlbw00lS6eTXN1Frt+Jq8UShME upH3PIK8E5o56imBhlBi9dPCA22m6VzGOgNaJW3glfnmCeJQm4U6POK+RQv+Poe+EJ/p YhTAOeBm4d06PVtl6lTMV0+wVQcj8pdh50UEQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=snCIeuHwZ2Iy8TQFZjGXmC1sKFnr41Jq+ozWnLy6cyY=; b=WcypYAq8CdcMJ4Wbi5gDeTECUeOh1ZpNvvRlYoo0VcqK2dqgJtV4qKnEw5icbgoNRg VnwK876WG+L+LOiENHmasR23LsvzdlSW6w010fju2QbIoQyQSCCOt0Pumkw/nTp+KUSu kf4wA64CZYMMo2LOy5tvnuTgO4Vs2oMaCOEZ/KdIN8wp6AU7TUfYjyq8bTH13uPBTNXQ LJOo+StK80b1HgIoMu1LGt9l3Q9wBcPCjQ2mbCDJAh8aEQGamN0/uawJL761lg7VYC2K fiSiQrveXENKMRM78xSqa4zHp1YAm002BLa7NxlQi0a0o3ueDiXDXSGaBQZnbaW2EAJR iBgQ== X-Gm-Message-State: APf1xPCWgLSFhq2Krmi9Dj+kkft0O3ytMFQCIN6juUzXdQ86rnzCuiDV 4SZ7YyDwEoXkKl2WYc9qWAXEgw== X-Google-Smtp-Source: AH8x2252ScUwqT5Z1ZrNU+SfjaqRj3qYN+/XrYosoMseDk4Czm0/GhU38Tv+FtlTw9kLV3QS5HnZrw== X-Received: by 10.28.230.151 with SMTP id e23mr42944wmi.11.1518111627041; Thu, 08 Feb 2018 09:40:27 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Thu, 8 Feb 2018 17:31:42 +0000 Message-Id: <20180208173157.24705-18-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180208173157.24705-1-alex.bennee@linaro.org> References: <20180208173157.24705-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v2 17/32] arm/translate-a64: initial decode for simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This actually covers two different sections of the encoding table: Advanced SIMD scalar two-register miscellaneous FP16 Advanced SIMD two-register miscellaneous (FP16) The difference between the two is covered by a combination of Q (bit 30) and S (bit 28). Notably the FRINTx instructions are only available in the vector form. This is just the decode skeleton which will be filled out by later patches. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - checkpatch cleanups --- target/arm/translate-a64.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f01bab801c..f939ca4d40 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10724,6 +10724,45 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) } } =20 +/* AdvSIMD [scalar] two register miscellaneous (FP16) + * + * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 = 0 + * +---+---+---+---+--------+---+-------------+--------+-----+------+-----= -+ + * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd= | + * +---+---+---+---+--------+---+-------------+--------+-----+------+-----= -+ + * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00 + * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800 + * + * ???While the group is listed with bit 28 always set to 1 this is not + * always the case.???? + * + * This actually covers two groups, + */ +static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) +{ + int fpop, opcode, a; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + opcode =3D extract32(insn, 12, 4); + a =3D extract32(insn, 23, 1); + fpop =3D deposit32(opcode, 5, 1, a); + + switch (fpop) { + default: + fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); + g_assert_not_reached(); + } + +} + /* AdvSIMD scalar x indexed element * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 * +-----+---+-----------+------+---+---+------+-----+---+---+------+-----= -+ @@ -11459,6 +11498,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, + { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, { 0x00000000, 0x00000000, NULL } }; =20 @@ -11472,6 +11512,8 @@ static void disas_data_proc_simd(DisasContext *s, u= int32_t insn) if (fn) { fn(s, insn); } else { + /* fprintf(stderr, "%s: failed to find %#4x @ %#" PRIx64 "\n", */ + /* __func__, insn, s->pc); */ unallocated_encoding(s); } } --=20 2.15.1