From nobody Mon Feb 9 23:03:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518112945287271.46543169016695; Thu, 8 Feb 2018 10:02:25 -0800 (PST) Received: from localhost ([::1]:57993 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejqWe-0005ZH-EY for importer@patchew.org; Thu, 08 Feb 2018 13:02:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54300) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejq3R-0003OH-8I for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:32:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ejq3O-0006iG-Ra for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:32:13 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:52929) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ejq3O-0006h7-JW for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:32:10 -0500 Received: by mail-wm0-x242.google.com with SMTP id g1so10887196wmg.2 for ; Thu, 08 Feb 2018 09:32:10 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id b133sm452066wmh.4.2018.02.08.09.32.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 09:32:05 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 67DB13E0C29; Thu, 8 Feb 2018 17:31:58 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BVeImd1OiYsSaUNnIN2vG509/0i0QwAcJu2NtStwtTo=; b=NxSZaYMXe7rCiWKDXY5IgI80aahpZZd7xcUaEWyu1sgrvHS3oZuSq86jSUJa5DJs6w 11P3Pm5P8aqkJc2xDsoQyqNz8pRGVHW9yYXyH/8Nex/lagNfLrNiGusZBRzerDCtxiZ3 UkdydtPq1SWL7qfZw1oQgWG3irGSUc31GPt1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BVeImd1OiYsSaUNnIN2vG509/0i0QwAcJu2NtStwtTo=; b=bptYzq8MRS4UK6F4KgBQhr8P3t+p+tK/t85ZMZhePBtq0DlJB5SQ38ZMYcMSHP9jXj VP8YJLU9LHY5d69dl+IjVy14s2sRLPpYkZygZXNu9YY9oMsqrNeup4hqRNML0C5zga1A aKM0kQb9+5mwGet7D2WAmiIae4qVLv4LjCU0Z8NB7eLKrGV2U4Hf1Svt82o8B9KDNcBA HIWIkKP4gHnvldgDNt/g12/JvULTKbyzCmjqo4leXrbvfNSkTxJxLq3y8bohGbFGn4VL x6bGXL+yQhpxugOgV+NuZlD8O3GLSwUxmAD+lpzcWNAdc4DjriO2caZ8Zo5/5BZQQ54+ teKA== X-Gm-Message-State: APf1xPDeRcPKAyBiCjWSgIcef6PlguqMiYGPqa4XMb9NIDO0/UrT6ubl oBQXuhsU99M05gTf7/fnMg6pxw== X-Google-Smtp-Source: AH8x2260RrMS+Ge1uF6mtnWDBA0NU7ugSDnLxCqhpk5mgbLkOjmQfybTpJKLKi7EM3AVa9YB9QvAww== X-Received: by 10.28.124.4 with SMTP id x4mr42055wmc.84.1518111129453; Thu, 08 Feb 2018 09:32:09 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Thu, 8 Feb 2018 17:31:34 +0000 Message-Id: <20180208173157.24705-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180208173157.24705-1-alex.bennee@linaro.org> References: <20180208173157.24705-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v2 09/32] arm/translate-a64: initial decode for simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This is the initial decode skeleton for the Advanced SIMD three same instruction group. The fprintf is purely to aid debugging as the additional instructions are added. It will be removed once the group is complete. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 77 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 77 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2dd958c0e7..5392f83794 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9794,6 +9794,82 @@ static void disas_simd_three_reg_same(DisasContext *= s, uint32_t insn) } } =20 +/* + * Advanced SIMD three same (ARMv8.2 FP16 variants) + * + * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 = 0 + * +---+---+---+-----------+---------+------+-----+--------+---+------+---= ---+ + * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | R= d | + * +---+---+---+-----------+---------+------+-----+--------+---+------+---= ---+ + * + * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE + * (register), FACGE, FABD, FCMGT (register) and FACGT. + * + */ +static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) +{ + int opcode, fpopcode; + int is_q, u, a, rm, rn, rd; + int datasize, elements; + int pass; + TCGv_ptr fpst; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + /* For these floating point ops, the U, a and opcode bits + * together indicate the operation. + */ + opcode =3D extract32(insn, 11, 3); + u =3D extract32(insn, 29, 1); + a =3D extract32(insn, 23, 1); + is_q =3D extract32(insn, 30, 1); + rm =3D extract32(insn, 16, 5); + rn =3D extract32(insn, 5, 5); + rd =3D extract32(insn, 0, 5); + + fpopcode =3D opcode | (a << 3) | (u << 4); + datasize =3D is_q ? 128 : 64; + elements =3D datasize / 16; + + fpst =3D get_fpstatus_ptr(true); + + for (pass =3D 0; pass < elements; pass++) { + TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op2 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); + read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); + + switch (fpopcode) { + default: + fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", + __func__, insn, fpopcode, s->pc); + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + } + + tcg_temp_free_ptr(fpst); + + if (!is_q) { + /* non-quad vector op */ + clear_vec_high(s, rd); + } + +} + static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, int size, int rn, int rd) { @@ -11199,6 +11275,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, + { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.15.1