From nobody Wed Feb 11 04:05:59 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518044536223791.6917145360668; Wed, 7 Feb 2018 15:02:16 -0800 (PST) Received: from localhost ([::1]:40527 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejYjH-000478-BF for importer@patchew.org; Wed, 07 Feb 2018 18:02:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37431) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejYdE-0007Hf-C7 for qemu-devel@nongnu.org; Wed, 07 Feb 2018 17:56:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ejYd9-0004td-Ft for qemu-devel@nongnu.org; Wed, 07 Feb 2018 17:56:00 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:37882) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ejYd9-0004ra-7A for qemu-devel@nongnu.org; Wed, 07 Feb 2018 17:55:55 -0500 Received: by mail-pg0-x244.google.com with SMTP id o1so900426pgn.4 for ; Wed, 07 Feb 2018 14:55:55 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id v73sm5874836pfk.84.2018.02.07.14.55.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 07 Feb 2018 14:55:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lg4QsNCVaEFgOIm4s9MbStPoT6rwbuxZcXRG0TtRpy0=; b=HlRMrf6GbntSoq28RJxcV/UI4KjmLU2YlAiDVSBSFW6IvApTvtl/12vPNsIJfM1NKP xpqLdVJRJFuTbhl3Eqq+GB2y1ZKY3LXc61uIoX7V+V5XpGpyrCFy9oE3E6/KFnvYeNTI cBmdwmj7qIyHZetQfCf8Kdg8dterW08qCtF3w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lg4QsNCVaEFgOIm4s9MbStPoT6rwbuxZcXRG0TtRpy0=; b=IcDLFAgp1ao3oeQv4m4ksMNITaNJ2kYbKGfIFfn2zZ4fROBzh5JbFxAJ7tkVkYdRPH KCf4r6capqIYVqEQnl0UVXT6JvOIKjrXNdn8+gKEtTtIULsXKobsEwG3eUH6GOI962tZ Z3sGnMIVWOxGqgqQ1xhHW5YJqNyZgBP3MHWmbO3rpnyjzHKZczXiA8+BJt4Qvz2UAfMr TXw5VILDLVrUbD2mUehJiqyJrkbw6Ho4wOkXSvbEV49dm9f8Cw7tX4PsMXbur6/DHZga IBl1uO5lY41Nxr7RvxshCTIPiKLfMwscNV8i3YlERHbLbTnaY2HkD1GzlrCXB3VQZ3C3 l7Xg== X-Gm-Message-State: APf1xPDsYosFKJg9nLOnLwo/RbzKjufHpIGHtPOUbo1O52/kCqtjLAma 5BNdk3woTe/uOGBxZssovXgDvrt2cA4= X-Google-Smtp-Source: AH8x227Cd0jtEt4v3QILN1a04N8PcJoDzii9LYLqeLzYB+YhHd04wMDJ0Bm8+vYHkY7eNqsCpiKc1g== X-Received: by 10.98.219.68 with SMTP id f65mr6748931pfg.25.1518044153648; Wed, 07 Feb 2018 14:55:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 7 Feb 2018 14:55:27 -0800 Message-Id: <20180207225540.31698-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180207225540.31698-1-richard.henderson@linaro.org> References: <20180207225540.31698-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 07/20] tcg: Add generic vector ops for multiplication X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 5 +++++ tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-op.h | 1 + tcg/tcg-opc.h | 1 + tcg/tcg.h | 1 + accel/tcg/tcg-runtime-gvec.c | 44 ++++++++++++++++++++++++++++++++++++++++= ++++ tcg/tcg-op-gvec.c | 29 +++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 22 ++++++++++++++++++++++ tcg/tcg.c | 2 ++ tcg/README | 4 ++++ 10 files changed, 111 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index c840debc40..54f7e78b09 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -152,6 +152,11 @@ DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(gvec_mul8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_mul16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_mul32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_mul64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 60a17ee908..abe909df39 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -176,6 +176,8 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uin= t32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 113d9a6c3a..75bb55aeac 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -917,6 +917,7 @@ void tcg_gen_dup64i_vec(TCGv_vec, uint64_t); void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 13c0eed3da..d81a6c4535 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -219,6 +219,7 @@ DEF(st_vec, 0, 2, 1, IMPLVEC) =20 DEF(add_vec, 1, 2, 0, IMPLVEC) DEF(sub_vec, 1, 2, 0, IMPLVEC) +DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec)) DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec)) =20 DEF(and_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/tcg.h b/tcg/tcg.h index 8c19a1f41d..9e2d909a4a 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -181,6 +181,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 #else #define TCG_TARGET_MAYBE_vec 1 #endif diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index f2b0cba4a2..59d7a0a2fe 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -166,6 +166,50 @@ void HELPER(gvec_sub64)(void *d, void *a, void *b, uin= t32_t desc) clear_high(d, oprsz, desc); } =20 +void HELPER(gvec_mul8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec8)) { + *(vec8 *)(d + i) =3D *(vec8 *)(a + i) * *(vec8 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_mul16)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec16)) { + *(vec16 *)(d + i) =3D *(vec16 *)(a + i) * *(vec16 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_mul32)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec32)) { + *(vec32 *)(d + i) =3D *(vec32 *)(a + i) * *(vec32 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_mul64)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D *(vec64 *)(a + i) * *(vec64 *)(b + i); + } + clear_high(d, oprsz, desc); +} + void HELPER(gvec_neg8)(void *d, void *a, uint32_t desc) { intptr_t oprsz =3D simd_oprsz(desc); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 094c69dc59..49c77e31aa 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1280,6 +1280,35 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, = uint32_t aofs, tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 +void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_mul_vec, + .fno =3D gen_helper_gvec_mul8, + .opc =3D INDEX_op_mul_vec, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_mul_vec, + .fno =3D gen_helper_gvec_mul16, + .opc =3D INDEX_op_mul_vec, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_mul_i32, + .fniv =3D tcg_gen_mul_vec, + .fno =3D gen_helper_gvec_mul32, + .opc =3D INDEX_op_mul_vec, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_mul_i64, + .fniv =3D tcg_gen_mul_vec, + .fno =3D gen_helper_gvec_mul64, + .opc =3D INDEX_op_mul_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + /* Perform a vector negation using normal negation and a mask. Compare gen_subv_mask above. */ static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 4a6f92fd11..70ec889bc1 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -365,3 +365,25 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond); } } + +void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + TCGTemp *rt =3D tcgv_vec_temp(r); + TCGTemp *at =3D tcgv_vec_temp(a); + TCGTemp *bt =3D tcgv_vec_temp(b); + TCGArg ri =3D temp_arg(rt); + TCGArg ai =3D temp_arg(at); + TCGArg bi =3D temp_arg(bt); + TCGType type =3D rt->base_type; + int can; + + tcg_debug_assert(at->base_type =3D=3D type); + tcg_debug_assert(bt->base_type =3D=3D type); + can =3D tcg_can_emit_vec_op(INDEX_op_mul_vec, type, vece); + if (can > 0) { + vec_gen_3(INDEX_op_mul_vec, type, vece, ri, ai, bi); + } else { + tcg_debug_assert(can < 0); + tcg_expand_vec_op(INDEX_op_mul_vec, type, vece, ri, ai, bi); + } +} diff --git a/tcg/tcg.c b/tcg/tcg.c index de709833b1..bb24526c93 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1403,6 +1403,8 @@ bool tcg_op_supported(TCGOpcode op) return have_vec && TCG_TARGET_HAS_andc_vec; case INDEX_op_orc_vec: return have_vec && TCG_TARGET_HAS_orc_vec; + case INDEX_op_mul_vec: + return have_vec && TCG_TARGET_HAS_mul_vec; case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: diff --git a/tcg/README b/tcg/README index 90d4de7776..bb2ea5121b 100644 --- a/tcg/README +++ b/tcg/README @@ -538,6 +538,10 @@ E.g. VECL=3D1 -> 64 << 1 -> v128, and VECE=3D2 -> 1 <<= 2 -> i32. =20 Similarly, v0 =3D v1 - v2. =20 +* mul_vec v0, v1, v2 + + Similarly, v0 =3D v1 * v2. + * neg_vec v0, v1 =20 Similarly, v0 =3D -v1. --=20 2.14.3