From nobody Mon Feb 9 19:06:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517963445896334.79409756174107; Tue, 6 Feb 2018 16:30:45 -0800 (PST) Received: from localhost ([::1]:54613 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejDdN-0002Wk-3l for importer@patchew.org; Tue, 06 Feb 2018 19:30:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56396) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejDZN-0007ei-NS for qemu-devel@nongnu.org; Tue, 06 Feb 2018 19:26:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ejDZK-0005LO-Bl for qemu-devel@nongnu.org; Tue, 06 Feb 2018 19:26:37 -0500 Received: from mx1.redhat.com ([209.132.183.28]:50716) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ejDZK-0005Jw-3b for qemu-devel@nongnu.org; Tue, 06 Feb 2018 19:26:34 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 674B9C001F28; Wed, 7 Feb 2018 00:26:33 +0000 (UTC) Received: from gimli.home (ovpn-117-203.phx2.redhat.com [10.3.117.203]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1B31D5C88F; Wed, 7 Feb 2018 00:26:32 +0000 (UTC) From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 06 Feb 2018 17:26:32 -0700 Message-ID: <20180207002632.1156.53770.stgit@gimli.home> In-Reply-To: <20180207001615.1156.10547.stgit@gimli.home> References: <20180207001615.1156.10547.stgit@gimli.home> User-Agent: StGit/0.18-102-gdf9f MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Wed, 07 Feb 2018 00:26:33 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC PATCH 3/5] vfio/quirks: Automatic ioeventfd enabling for NVIDIA BAR0 quirks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.williamson@redhat.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Record data writes that come through the NVIDIA BAR0 quirk, if we get enough in a row that we're only passing through, automatically enable an ioeventfd for it. The primary target for this is the MSI-ACK that NVIDIA uses to allow the MSI interrupt to re-trigger, which is a 4-byte write, data value 0x0 to offset 0x704 into the quirk, 0x88704 into BAR0 MMIO space. For an interrupt latency sensitive micro- benchmark, this takes us from 83% of performance versus disabling the quirk entirely (which GeForce cannot do), to to almost 90%. Signed-off-by: Alex Williamson --- hw/vfio/pci-quirks.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++= +++- hw/vfio/pci.h | 2 + 2 files changed, 89 insertions(+), 2 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index e4cf4ea2dd9c..e739efe601b1 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -203,6 +203,7 @@ typedef struct VFIOConfigMirrorQuirk { uint32_t offset; uint8_t bar; MemoryRegion *mem; + uint8_t data[]; } VFIOConfigMirrorQuirk; =20 static uint64_t vfio_generic_quirk_mirror_read(void *opaque, @@ -297,6 +298,50 @@ static void vfio_ioeventfd_exit(VFIOIOEventFD *ioevent= fd) g_free(ioeventfd); } =20 +static void vfio_ioeventfd_handler(void *opaque) +{ + VFIOIOEventFD *ioeventfd =3D opaque; + + if (event_notifier_test_and_clear(&ioeventfd->e)) { + vfio_region_write(ioeventfd->region, ioeventfd->region_addr, + ioeventfd->data, ioeventfd->size); + } +} + +static VFIOIOEventFD *vfio_ioeventfd_init(VFIOPCIDevice *vdev, + MemoryRegion *mr, hwaddr addr, + unsigned size, uint64_t data, + VFIORegion *region, + hwaddr region_addr) +{ + VFIOIOEventFD *ioeventfd =3D g_malloc0(sizeof(*ioeventfd)); + + if (event_notifier_init(&ioeventfd->e, 0)) { + g_free(ioeventfd); + return NULL; + } + + ioeventfd->mr =3D mr; + ioeventfd->addr =3D addr; + ioeventfd->size =3D size; + ioeventfd->match_data =3D true; + ioeventfd->data =3D data; + ioeventfd->region =3D region; + ioeventfd->region_addr =3D region_addr; + + qemu_set_fd_handler(event_notifier_get_fd(&ioeventfd->e), + vfio_ioeventfd_handler, NULL, ioeventfd); + memory_region_add_eventfd(ioeventfd->mr, ioeventfd->addr, + ioeventfd->size, ioeventfd->match_data, + ioeventfd->data, &ioeventfd->e); + + info_report("Enabled automatic ioeventfd acceleration for %s region %d= , " + "offset 0x%"HWADDR_PRIx", data 0x%"PRIx64", size %u", + vdev->vbasedev.name, region->nr, region_addr, data, size); + + return ioeventfd; +} + static void vfio_vga_probe_ati_3c3_quirk(VFIOPCIDevice *vdev) { VFIOQuirk *quirk; @@ -732,6 +777,13 @@ static void vfio_probe_nvidia_bar5_quirk(VFIOPCIDevice= *vdev, int nr) trace_vfio_quirk_nvidia_bar5_probe(vdev->vbasedev.name); } =20 +typedef struct LastDataSet { + hwaddr addr; + uint64_t data; + unsigned size; + int count; +} LastDataSet; + /* * Finally, BAR0 itself. We want to redirect any accesses to either * 0x1800 or 0x88000 through the PCI config space access functions. @@ -742,6 +794,7 @@ static void vfio_nvidia_quirk_mirror_write(void *opaque= , hwaddr addr, VFIOConfigMirrorQuirk *mirror =3D opaque; VFIOPCIDevice *vdev =3D mirror->vdev; PCIDevice *pdev =3D &vdev->pdev; + LastDataSet *last =3D (LastDataSet *)&mirror->data; =20 vfio_generic_quirk_mirror_write(opaque, addr, data, size); =20 @@ -756,6 +809,38 @@ static void vfio_nvidia_quirk_mirror_write(void *opaqu= e, hwaddr addr, addr + mirror->offset, data, size); trace_vfio_quirk_nvidia_bar0_msi_ack(vdev->vbasedev.name); } + + /* + * Automatically add an ioeventfd to handle any repeated write with the + * same data and size above the standard PCI config space header. Thi= s is + * primarily expected to accelerate the MSI-ACK behavior, such as noted + * above. Current hardware/drivers should trigger an ioeventfd at con= fig + * offset 0x704 (region offset 0x88704), with data 0x0, size 4. + */ + if (addr > PCI_STD_HEADER_SIZEOF) { + if (addr !=3D last->addr || data !=3D last->data || size !=3D last= ->size) { + last->addr =3D addr; + last->data =3D data; + last->size =3D size; + last->count =3D 1; + } else if (++last->count > 10) { + VFIOIOEventFD *ioeventfd; + + ioeventfd =3D vfio_ioeventfd_init(vdev, mirror->mem, addr, siz= e, data, + &vdev->bars[mirror->bar].regio= n, + mirror->offset + addr); + if (ioeventfd) { + VFIOQuirk *quirk; + + QLIST_FOREACH(quirk, &vdev->bars[mirror->bar].quirks, next= ) { + if (quirk->data =3D=3D mirror) { + QLIST_INSERT_HEAD(&quirk->ioeventfds, ioeventfd, n= ext); + break; + } + } + } + } + } } =20 static const MemoryRegionOps vfio_nvidia_mirror_quirk =3D { @@ -776,7 +861,7 @@ static void vfio_probe_nvidia_bar0_quirk(VFIOPCIDevice = *vdev, int nr) } =20 quirk =3D vfio_quirk_alloc(1); - mirror =3D quirk->data =3D g_malloc0(sizeof(*mirror)); + mirror =3D quirk->data =3D g_malloc0(sizeof(*mirror) + sizeof(LastData= Set)); mirror->mem =3D quirk->mem; mirror->vdev =3D vdev; mirror->offset =3D 0x88000; @@ -794,7 +879,7 @@ static void vfio_probe_nvidia_bar0_quirk(VFIOPCIDevice = *vdev, int nr) /* The 0x1800 offset mirror only seems to get used by legacy VGA */ if (vdev->vga) { quirk =3D vfio_quirk_alloc(1); - mirror =3D quirk->data =3D g_malloc0(sizeof(*mirror)); + mirror =3D quirk->data =3D g_malloc0(sizeof(*mirror) + sizeof(Last= DataSet)); mirror->mem =3D quirk->mem; mirror->vdev =3D vdev; mirror->offset =3D 0x1800; diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index 146065c2f715..ec53b9935725 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -32,6 +32,8 @@ typedef struct VFIOIOEventFD { bool match_data; uint64_t data; EventNotifier e; + VFIORegion *region; + hwaddr region_addr; } VFIOIOEventFD; =20 typedef struct VFIOQuirk {