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Violators will be prosecuted; Tue, 6 Feb 2018 14:15:59 -0500 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w16JFwKg41877738; Tue, 6 Feb 2018 19:15:58 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 19D6DAC040; Tue, 6 Feb 2018 14:17:19 -0500 (EST) Received: from localhost (unknown [9.80.97.150]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP id CCC16AC041; Tue, 6 Feb 2018 14:17:18 -0500 (EST) From: Michael Roth To: qemu-devel@nongnu.org Date: Tue, 6 Feb 2018 13:15:00 -0600 X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180206191515.25830-1-mdroth@linux.vnet.ibm.com> References: <20180206191515.25830-1-mdroth@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18020619-2213-0000-0000-0000026884E7 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008485; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000248; SDB=6.00985885; UDB=6.00500282; IPR=6.00765253; BA=6.00005813; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00019407; XFM=3.00000015; UTC=2018-02-06 19:16:00 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18020619-2214-0000-0000-00005905BD40 Message-Id: <20180206191515.25830-40-mdroth@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-06_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1802060241 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH 39/54] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-stable@nongnu.org, christian.ehrhardt@canonical.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: David Gibson This adds an spapr capability bit for Hardware Transactional Memory. It is enabled by default for pseries-2.11 and earlier machine types. with POWER8 or later CPUs (as it must be, since earlier qemu versions would implicitly allow it). However it is disabled by default for the latest pseries-2.12 machine type. This means that with the latest machine type, HTM will not be available, regardless of CPU, unless it is explicitly enabled on the command line. That change is made on the basis that: * This way running with -M pseries,accel=3Dtcg will start with whatever cpu and will provide the same guest visible model as with accel=3Dkvm. - More specifically, this means existing make check tests don't have to be modified to use cap-htm=3Doff in order to run with TCG * We hope to add a new "HTM without suspend" feature in the not too distant future which could work on both POWER8 and POWER9 cpus, and could be enabled by default. * Best guesses suggest that future POWER cpus may well only support the HTM-without-suspend model, not the (frankly, horribly overcomplicated) POWER8 style HTM with suspend. * Anecdotal evidence suggests problems with HTM being enabled when it wasn't wanted are more common than being missing when it was. Signed-off-by: David Gibson Reviewed-by: Greg Kurz (cherry picked from commit ee76a09fc72cfbfab2bb5529320ef7e460adffd8) Signed-off-by: Michael Roth --- hw/ppc/spapr.c | 15 ++++++++++----- hw/ppc/spapr_caps.c | 29 ++++++++++++++++++++++++++++- include/hw/ppc/spapr.h | 3 +++ 3 files changed, 41 insertions(+), 6 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 958d894add..08e4a14340 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -253,7 +253,9 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int offse= t, PowerPCCPU *cpu) } =20 /* Populate the "ibm,pa-features" property */ -static void spapr_populate_pa_features(PowerPCCPU *cpu, void *fdt, int off= set, +static void spapr_populate_pa_features(sPAPRMachineState *spapr, + PowerPCCPU *cpu, + void *fdt, int offset, bool legacy_guest) { CPUPPCState *env =3D &cpu->env; @@ -318,7 +320,7 @@ static void spapr_populate_pa_features(PowerPCCPU *cpu,= void *fdt, int offset, */ pa_features[3] |=3D 0x20; } - if (kvmppc_has_cap_htm() && pa_size > 24) { + if (spapr_has_cap(spapr, SPAPR_CAP_HTM) && pa_size > 24) { pa_features[24] |=3D 0x80; /* Transactional memory support */ } if (legacy_guest && pa_size > 40) { @@ -384,8 +386,8 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineSt= ate *spapr) return ret; } =20 - spapr_populate_pa_features(cpu, fdt, offset, - spapr->cas_legacy_guest_workaroun= d); + spapr_populate_pa_features(spapr, cpu, fdt, offset, + spapr->cas_legacy_guest_workaround); } return ret; } @@ -579,7 +581,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, page_sizes_prop, page_sizes_prop_size))); } =20 - spapr_populate_pa_features(cpu, fdt, offset, false); + spapr_populate_pa_features(spapr, cpu, fdt, offset, false); =20 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", cs->cpu_index / vcpus_per_socket))); @@ -3749,7 +3751,10 @@ static void spapr_machine_2_11_instance_options(Mach= ineState *machine) =20 static void spapr_machine_2_11_class_options(MachineClass *mc) { + sPAPRMachineClass *smc =3D SPAPR_MACHINE_CLASS(mc); + spapr_machine_2_12_class_options(mc); + smc->default_caps =3D spapr_caps(SPAPR_CAP_HTM); SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); } =20 diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 968ba7b857..3b35b91a5b 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -24,6 +24,10 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "sysemu/hw_accel.h" +#include "target/ppc/cpu.h" +#include "cpu-models.h" +#include "kvm_ppc.h" =20 #include "hw/ppc/spapr.h" =20 @@ -40,18 +44,41 @@ typedef struct sPAPRCapabilityInfo { void (*disallow)(sPAPRMachineState *spapr, Error **errp); } sPAPRCapabilityInfo; =20 +static void cap_htm_allow(sPAPRMachineState *spapr, Error **errp) +{ + if (tcg_enabled()) { + error_setg(errp, + "No Transactional Memory support in TCG, try cap-htm=3D= off"); + } else if (kvm_enabled() && !kvmppc_has_cap_htm()) { + error_setg(errp, +"KVM implementation does not support Transactional Memory, try cap-htm=3Do= ff" + ); + } +} + static sPAPRCapabilityInfo capability_table[] =3D { + { + .name =3D "htm", + .description =3D "Allow Hardware Transactional Memory (HTM)", + .flag =3D SPAPR_CAP_HTM, + .allow =3D cap_htm_allow, + /* TODO: add cap_htm_disallow */ + }, }; =20 static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr, CPUState *cs) { sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + PowerPCCPU *cpu =3D POWERPC_CPU(cs); sPAPRCapabilities caps; =20 caps =3D smc->default_caps; =20 - /* TODO: clamp according to cpu model */ + if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, + 0, spapr->max_compat_pvr)) { + caps.mask &=3D ~SPAPR_CAP_HTM; + } =20 return caps; } diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index c8852dfbba..72422690bd 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -54,6 +54,9 @@ typedef enum { * Capabilities */ =20 +/* Hardware Transactional Memory */ +#define SPAPR_CAP_HTM 0x0000000000000001ULL + typedef struct sPAPRCapabilities sPAPRCapabilities; struct sPAPRCapabilities { uint64_t mask; --=20 2.11.0