From nobody Tue Feb 10 21:40:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517936578508249.61077012758358; Tue, 6 Feb 2018 09:02:58 -0800 (PST) Received: from localhost ([::1]:38109 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6e1-0005D5-F1 for importer@patchew.org; Tue, 06 Feb 2018 12:02:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33618) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6Q8-0000fT-26 for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ej6Q6-00056x-81 for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:36 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:36275) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ej6Q5-00056d-UR for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:34 -0500 Received: by mail-wm0-x242.google.com with SMTP id f3so5164904wmc.1 for ; Tue, 06 Feb 2018 08:48:33 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id e67sm22959860wmf.7.2018.02.06.08.48.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Feb 2018 08:48:24 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 80D233E0239; Tue, 6 Feb 2018 16:48:16 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D4pDJEnOgHOmstbqR+pmy5DTC8NVaaqrBRWWAk1Lzzc=; b=i18maw7Ujt38NzALoRIG4DQkv35CIdUdh345R1sPj0WAygKQBIJ/4TqLB9WVWdt0Fi 44sufAPaybJBZC3IAz8zdQ6AslighMAzCiIFYCX6c4q8Sif4vG9D2Z9jSbL9b7KnGld2 fY/s7DZewEgmZCzBcnYdzlcXWBs+9NHSnMnHA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D4pDJEnOgHOmstbqR+pmy5DTC8NVaaqrBRWWAk1Lzzc=; b=qd7TTeqFSvo3MIGy+WQRyE1kautIvqsL9tJ71aPBKP1hSY0qJX8wrqmezUYacjWqWF 22ePU3drcoxMcVhsugM6RorkyVVcUAe3I6iejnGN7LN2HU4DyqxW+Giat3lrL6BFsjl+ TLag9WxD0wJToacMDZOBgzjjGFJZc4X6LVhDpcSD3TILMSI6h6f75ZVcsfjkaSWkcQEm D206fx2CNw5P15JfM74H2/1NQVkB0ujjCJPPKN3XOQAo72Tudn2y1x4qC/UotvJASDip GQfWlGCJ9Yv6ak44C4ZRNgJaYwKKxQmxObyuQo1fZG29/BWku66EJv1Z3TJahyT6zQWT 2aIw== X-Gm-Message-State: APf1xPCtrmp5CzqFQkiKGrCMTj7XVb/nKUAAnnKfAnFH/tm8Lj0SctcH Dq3CF0jSrI8lBsOo9QkWHQ+tbQ== X-Google-Smtp-Source: AH8x226Aq3DbM4EytwmltWMOjK2rqYTtamlMb631skzfArWgbzM+mhpwRu0GIgM4kEMxrTBDzv8sIw== X-Received: by 10.28.173.130 with SMTP id w124mr2180434wme.18.1517935712547; Tue, 06 Feb 2018 08:48:32 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org, peter.maydell@linaro.org, laurent@vivier.eu, bharata@linux.vnet.ibm.com, andrew@andrewdutcher.com Date: Tue, 6 Feb 2018 16:48:09 +0000 Message-Id: <20180206164815.10084-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180206164815.10084-1-alex.bennee@linaro.org> References: <20180206164815.10084-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v4 16/22] fpu/softfloat: re-factor round_to_int X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We can now add float16_round_to_int and use the common round_decomposed and canonicalize functions to have a single implementation for float16/32/64 round_to_int functions. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3 - rename structures and functions v4 - move NaN handling to return NaN --- fpu/softfloat.c | 322 ++++++++++++++++++++++----------------------= ---- include/fpu/softfloat.h | 1 + 2 files changed, 148 insertions(+), 175 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ae4ba6de51..5d04e65538 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -560,7 +560,26 @@ static bool is_qnan(FloatClass c) return c =3D=3D float_class_qnan; } =20 -static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) +static inline FloatParts return_nan(FloatParts a, float_status *s) +{ + switch (a.cls) { + case float_class_snan: + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_msnan; + /* FALLTHRU */ + case float_class_qnan: + if (s->default_nan_mode) { + a.cls =3D float_class_dnan; + } + break; + + default: + g_assert_not_reached(); + } + return a; +} + +static inline FloatParts pick_nan(FloatParts a, FloatParts b, float_status= *s) { if (is_snan(a.cls) || is_snan(b.cls)) { s->float_exception_flags |=3D float_flag_invalid; @@ -1175,6 +1194,133 @@ float64 float64_div(float64 a, float64 b, float_sta= tus *status) return float64_round_pack_canonical(pr, status); } =20 +/* + * Rounds the floating-point value `a' to an integer, and returns the + * result as a floating-point value. The operation is performed + * according to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic. + */ + +static FloatParts round_to_int(FloatParts a, int rounding_mode, float_stat= us *s) +{ + if (is_nan(a.cls)) { + return return_nan(a, s); + } + + switch (a.cls) { + case float_class_zero: + case float_class_inf: + case float_class_qnan: + /* already "integral" */ + break; + case float_class_normal: + if (a.exp >=3D DECOMPOSED_BINARY_POINT) { + /* already integral */ + break; + } + if (a.exp < 0) { + bool one; + /* all fractional */ + s->float_exception_flags |=3D float_flag_inexact; + switch (rounding_mode) { + case float_round_nearest_even: + one =3D a.exp =3D=3D -1 && a.frac > DECOMPOSED_IMPLICIT_BI= T; + break; + case float_round_ties_away: + one =3D a.exp =3D=3D -1 && a.frac >=3D DECOMPOSED_IMPLICIT= _BIT; + break; + case float_round_to_zero: + one =3D false; + break; + case float_round_up: + one =3D !a.sign; + break; + case float_round_down: + one =3D a.sign; + break; + default: + g_assert_not_reached(); + } + + if (one) { + a.frac =3D DECOMPOSED_IMPLICIT_BIT; + a.exp =3D 0; + } else { + a.cls =3D float_class_zero; + } + } else { + uint64_t frac_lsb, frac_lsbm1, round_mask, roundeven_mask, inc; + + frac_lsb =3D DECOMPOSED_IMPLICIT_BIT >> a.exp; + frac_lsbm1 =3D frac_lsb >> 1; + roundeven_mask =3D (frac_lsb - 1) | frac_lsb; + round_mask =3D roundeven_mask >> 1; + + switch (rounding_mode) { + case float_round_nearest_even: + inc =3D ((a.frac & roundeven_mask) !=3D frac_lsbm1 ? frac_= lsbm1 : 0); + break; + case float_round_ties_away: + inc =3D frac_lsbm1; + break; + case float_round_to_zero: + inc =3D 0; + break; + case float_round_up: + inc =3D a.sign ? 0 : round_mask; + break; + case float_round_down: + inc =3D a.sign ? round_mask : 0; + break; + default: + g_assert_not_reached(); + } + + if (a.frac & round_mask) { + s->float_exception_flags |=3D float_flag_inexact; + a.frac +=3D inc; + a.frac &=3D ~round_mask; + if (a.frac & DECOMPOSED_OVERFLOW_BIT) { + a.frac >>=3D 1; + a.exp++; + } + } + } + break; + default: + g_assert_not_reached(); + } + return a; +} + +float16 float16_round_to_int(float16 a, float_status *s) +{ + FloatParts pa =3D float16_unpack_canonical(a, s); + FloatParts pr =3D round_to_int(pa, s->float_rounding_mode, s); + return float16_round_pack_canonical(pr, s); +} + +float32 float32_round_to_int(float32 a, float_status *s) +{ + FloatParts pa =3D float32_unpack_canonical(a, s); + FloatParts pr =3D round_to_int(pa, s->float_rounding_mode, s); + return float32_round_pack_canonical(pr, s); +} + +float64 float64_round_to_int(float64 a, float_status *s) +{ + FloatParts pa =3D float64_unpack_canonical(a, s); + FloatParts pr =3D round_to_int(pa, s->float_rounding_mode, s); + return float64_round_pack_canonical(pr, s); +} + +float64 float64_trunc_to_int(float64 a, float_status *s) +{ + FloatParts pa =3D float64_unpack_canonical(a, s); + FloatParts pr =3D round_to_int(pa, float_round_to_zero, s); + return float64_round_pack_canonical(pr, s); +} + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the @@ -2905,87 +3051,6 @@ float128 float32_to_float128(float32 a, float_status= *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Rounds the single-precision floating-point value `a' to an integer, and -| returns the result as a single-precision floating-point value. The -| operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_round_to_int(float32 a, float_status *status) -{ - flag aSign; - int aExp; - uint32_t lastBitMask, roundBitsMask; - uint32_t z; - a =3D float32_squash_input_denormal(a, status); - - aExp =3D extractFloat32Exp( a ); - if ( 0x96 <=3D aExp ) { - if ( ( aExp =3D=3D 0xFF ) && extractFloat32Frac( a ) ) { - return propagateFloat32NaN(a, a, status); - } - return a; - } - if ( aExp <=3D 0x7E ) { - if ( (uint32_t) ( float32_val(a)<<1 ) =3D=3D 0 ) return a; - status->float_exception_flags |=3D float_flag_inexact; - aSign =3D extractFloat32Sign( a ); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - if ( ( aExp =3D=3D 0x7E ) && extractFloat32Frac( a ) ) { - return packFloat32( aSign, 0x7F, 0 ); - } - break; - case float_round_ties_away: - if (aExp =3D=3D 0x7E) { - return packFloat32(aSign, 0x7F, 0); - } - break; - case float_round_down: - return make_float32(aSign ? 0xBF800000 : 0); - case float_round_up: - return make_float32(aSign ? 0x80000000 : 0x3F800000); - } - return packFloat32( aSign, 0, 0 ); - } - lastBitMask =3D 1; - lastBitMask <<=3D 0x96 - aExp; - roundBitsMask =3D lastBitMask - 1; - z =3D float32_val(a); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - z +=3D lastBitMask>>1; - if ((z & roundBitsMask) =3D=3D 0) { - z &=3D ~lastBitMask; - } - break; - case float_round_ties_away: - z +=3D lastBitMask >> 1; - break; - case float_round_to_zero: - break; - case float_round_up: - if (!extractFloat32Sign(make_float32(z))) { - z +=3D roundBitsMask; - } - break; - case float_round_down: - if (extractFloat32Sign(make_float32(z))) { - z +=3D roundBitsMask; - } - break; - default: - abort(); - } - z &=3D ~ roundBitsMask; - if (z !=3D float32_val(a)) { - status->float_exception_flags |=3D float_flag_inexact; - } - return make_float32(z); - -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the single-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -4129,99 +4194,6 @@ float128 float64_to_float128(float64 a, float_status= *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Rounds the double-precision floating-point value `a' to an integer, and -| returns the result as a double-precision floating-point value. The -| operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_round_to_int(float64 a, float_status *status) -{ - flag aSign; - int aExp; - uint64_t lastBitMask, roundBitsMask; - uint64_t z; - a =3D float64_squash_input_denormal(a, status); - - aExp =3D extractFloat64Exp( a ); - if ( 0x433 <=3D aExp ) { - if ( ( aExp =3D=3D 0x7FF ) && extractFloat64Frac( a ) ) { - return propagateFloat64NaN(a, a, status); - } - return a; - } - if ( aExp < 0x3FF ) { - if ( (uint64_t) ( float64_val(a)<<1 ) =3D=3D 0 ) return a; - status->float_exception_flags |=3D float_flag_inexact; - aSign =3D extractFloat64Sign( a ); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - if ( ( aExp =3D=3D 0x3FE ) && extractFloat64Frac( a ) ) { - return packFloat64( aSign, 0x3FF, 0 ); - } - break; - case float_round_ties_away: - if (aExp =3D=3D 0x3FE) { - return packFloat64(aSign, 0x3ff, 0); - } - break; - case float_round_down: - return make_float64(aSign ? LIT64( 0xBFF0000000000000 ) : 0); - case float_round_up: - return make_float64( - aSign ? LIT64( 0x8000000000000000 ) : LIT64( 0x3FF000000000000= 0 )); - } - return packFloat64( aSign, 0, 0 ); - } - lastBitMask =3D 1; - lastBitMask <<=3D 0x433 - aExp; - roundBitsMask =3D lastBitMask - 1; - z =3D float64_val(a); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - z +=3D lastBitMask >> 1; - if ((z & roundBitsMask) =3D=3D 0) { - z &=3D ~lastBitMask; - } - break; - case float_round_ties_away: - z +=3D lastBitMask >> 1; - break; - case float_round_to_zero: - break; - case float_round_up: - if (!extractFloat64Sign(make_float64(z))) { - z +=3D roundBitsMask; - } - break; - case float_round_down: - if (extractFloat64Sign(make_float64(z))) { - z +=3D roundBitsMask; - } - break; - default: - abort(); - } - z &=3D ~ roundBitsMask; - if (z !=3D float64_val(a)) { - status->float_exception_flags |=3D float_flag_inexact; - } - return make_float64(z); - -} - -float64 float64_trunc_to_int(float64 a, float_status *status) -{ - int oldmode; - float64 res; - oldmode =3D status->float_rounding_mode; - status->float_rounding_mode =3D float_round_to_zero; - res =3D float64_round_to_int(a, status); - status->float_rounding_mode =3D oldmode; - return res; -} - =20 /*------------------------------------------------------------------------= ---- | Returns the remainder of the double-precision floating-point value `a' diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 65bc7442d2..4650758c23 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -237,6 +237,7 @@ float64 float16_to_float64(float16 a, flag ieee, float_= status *status); | Software half-precision operations. *-------------------------------------------------------------------------= ---*/ =20 +float16 float16_round_to_int(float16, float_status *status); float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); float16 float16_mul(float16, float16, float_status *status); --=20 2.15.1