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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v4 13/22] fpu/softfloat: re-factor mul X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We can now add float16_mul and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 versions. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3 - mul compile fixes for new names - remove duplicate s-o-b - more explicit inf * zero check v4 - use is_nan - pick_nan_parts/pick_nan --- fpu/softfloat.c | 209 +++++++++++++++++++-------------------------= ---- include/fpu/softfloat.h | 1 + 2 files changed, 82 insertions(+), 128 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 2190e7de56..6d29e1a103 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -735,6 +735,87 @@ float64 __attribute__((flatten)) float64_sub(float64 a= , float64 b, return float64_round_pack_canonical(pr, status); } =20 +/* + * Returns the result of multiplying the floating-point values `a' and + * `b'. The operation is performed according to the IEC/IEEE Standard + * for Binary Floating-Point Arithmetic. + */ + +static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s) +{ + bool sign =3D a.sign ^ b.sign; + + if (a.cls =3D=3D float_class_normal && b.cls =3D=3D float_class_normal= ) { + uint64_t hi, lo; + int exp =3D a.exp + b.exp; + + mul64To128(a.frac, b.frac, &hi, &lo); + shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi, &lo); + if (lo & DECOMPOSED_OVERFLOW_BIT) { + shift64RightJamming(lo, 1, &lo); + exp +=3D 1; + } + + /* Re-use a */ + a.exp =3D exp; + a.sign =3D sign; + a.frac =3D lo; + return a; + } + /* handle all the NaN cases */ + if (is_nan(a.cls) || is_nan(b.cls)) { + return pick_nan(a, b, s); + } + /* Inf * Zero =3D=3D NaN */ + if ((a.cls =3D=3D float_class_inf && b.cls =3D=3D float_class_zero) || + (a.cls =3D=3D float_class_zero && b.cls =3D=3D float_class_inf)) { + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_dnan; + a.sign =3D sign; + return a; + } + /* Multiply by 0 or Inf */ + if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { + a.sign =3D sign; + return a; + } + if (b.cls =3D=3D float_class_inf || b.cls =3D=3D float_class_zero) { + b.sign =3D sign; + return b; + } + g_assert_not_reached(); +} + +float16 __attribute__((flatten)) float16_mul(float16 a, float16 b, + float_status *status) +{ + FloatParts pa =3D float16_unpack_canonical(a, status); + FloatParts pb =3D float16_unpack_canonical(b, status); + FloatParts pr =3D mul_floats(pa, pb, status); + + return float16_round_pack_canonical(pr, status); +} + +float32 __attribute__((flatten)) float32_mul(float32 a, float32 b, + float_status *status) +{ + FloatParts pa =3D float32_unpack_canonical(a, status); + FloatParts pb =3D float32_unpack_canonical(b, status); + FloatParts pr =3D mul_floats(pa, pb, status); + + return float32_round_pack_canonical(pr, status); +} + +float64 __attribute__((flatten)) float64_mul(float64 a, float64 b, + float_status *status) +{ + FloatParts pa =3D float64_unpack_canonical(a, status); + FloatParts pb =3D float64_unpack_canonical(b, status); + FloatParts pr =3D mul_floats(pa, pb, status); + + return float64_round_pack_canonical(pr, status); +} + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the @@ -2546,70 +2627,6 @@ float32 float32_round_to_int(float32 a, float_status= *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of multiplying the single-precision floating-point va= lues -| `a' and `b'. The operation is performed according to the IEC/IEEE Stand= ard -| for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_mul(float32 a, float32 b, float_status *status) -{ - flag aSign, bSign, zSign; - int aExp, bExp, zExp; - uint32_t aSig, bSig; - uint64_t zSig64; - uint32_t zSig; - - a =3D float32_squash_input_denormal(a, status); - b =3D float32_squash_input_denormal(b, status); - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - bSig =3D extractFloat32Frac( b ); - bExp =3D extractFloat32Exp( b ); - bSign =3D extractFloat32Sign( b ); - zSign =3D aSign ^ bSign; - if ( aExp =3D=3D 0xFF ) { - if ( aSig || ( ( bExp =3D=3D 0xFF ) && bSig ) ) { - return propagateFloat32NaN(a, b, status); - } - if ( ( bExp | bSig ) =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - return packFloat32( zSign, 0xFF, 0 ); - } - if ( bExp =3D=3D 0xFF ) { - if (bSig) { - return propagateFloat32NaN(a, b, status); - } - if ( ( aExp | aSig ) =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - return packFloat32( zSign, 0xFF, 0 ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat32( zSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - if ( bExp =3D=3D 0 ) { - if ( bSig =3D=3D 0 ) return packFloat32( zSign, 0, 0 ); - normalizeFloat32Subnormal( bSig, &bExp, &bSig ); - } - zExp =3D aExp + bExp - 0x7F; - aSig =3D ( aSig | 0x00800000 )<<7; - bSig =3D ( bSig | 0x00800000 )<<8; - shift64RightJamming( ( (uint64_t) aSig ) * bSig, 32, &zSig64 ); - zSig =3D zSig64; - if ( 0 <=3D (int32_t) ( zSig<<1 ) ) { - zSig <<=3D 1; - --zExp; - } - return roundAndPackFloat32(zSign, zExp, zSig, status); - -} =20 /*------------------------------------------------------------------------= ---- | Returns the result of dividing the single-precision floating-point value= `a' @@ -4142,70 +4159,6 @@ float64 float64_trunc_to_int(float64 a, float_status= *status) return res; } =20 - -/*------------------------------------------------------------------------= ---- -| Returns the result of multiplying the double-precision floating-point va= lues -| `a' and `b'. The operation is performed according to the IEC/IEEE Stand= ard -| for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_mul(float64 a, float64 b, float_status *status) -{ - flag aSign, bSign, zSign; - int aExp, bExp, zExp; - uint64_t aSig, bSig, zSig0, zSig1; - - a =3D float64_squash_input_denormal(a, status); - b =3D float64_squash_input_denormal(b, status); - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - bSig =3D extractFloat64Frac( b ); - bExp =3D extractFloat64Exp( b ); - bSign =3D extractFloat64Sign( b ); - zSign =3D aSign ^ bSign; - if ( aExp =3D=3D 0x7FF ) { - if ( aSig || ( ( bExp =3D=3D 0x7FF ) && bSig ) ) { - return propagateFloat64NaN(a, b, status); - } - if ( ( bExp | bSig ) =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - return packFloat64( zSign, 0x7FF, 0 ); - } - if ( bExp =3D=3D 0x7FF ) { - if (bSig) { - return propagateFloat64NaN(a, b, status); - } - if ( ( aExp | aSig ) =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - return packFloat64( zSign, 0x7FF, 0 ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat64( zSign, 0, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - if ( bExp =3D=3D 0 ) { - if ( bSig =3D=3D 0 ) return packFloat64( zSign, 0, 0 ); - normalizeFloat64Subnormal( bSig, &bExp, &bSig ); - } - zExp =3D aExp + bExp - 0x3FF; - aSig =3D ( aSig | LIT64( 0x0010000000000000 ) )<<10; - bSig =3D ( bSig | LIT64( 0x0010000000000000 ) )<<11; - mul64To128( aSig, bSig, &zSig0, &zSig1 ); - zSig0 |=3D ( zSig1 !=3D 0 ); - if ( 0 <=3D (int64_t) ( zSig0<<1 ) ) { - zSig0 <<=3D 1; - --zExp; - } - return roundAndPackFloat64(zSign, zExp, zSig0, status); - -} - /*------------------------------------------------------------------------= ---- | Returns the result of dividing the double-precision floating-point value= `a' | by the corresponding value `b'. The operation is performed according to diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 693ece0974..7fc63dd60f 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -239,6 +239,7 @@ float64 float16_to_float64(float16 a, flag ieee, float_= status *status); =20 float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); +float16 float16_mul(float16, float16, float_status *status); =20 int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); --=20 2.15.1