From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517935840690692.0097111703429; Tue, 6 Feb 2018 08:50:40 -0800 (PST) Received: from localhost ([::1]:37447 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6S7-0001vd-IE for importer@patchew.org; Tue, 06 Feb 2018 11:50:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33392) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6Pu-0000T7-5b for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ej6Pq-0004fE-Ol for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:22 -0500 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:41050) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ej6Pq-0004dQ-IY for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:18 -0500 Received: by mail-wr0-x242.google.com with SMTP id v15so2649510wrb.8 for ; Tue, 06 Feb 2018 08:48:18 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id k3sm23125266wmk.3.2018.02.06.08.48.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Feb 2018 08:48:16 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 2DC043E025C; Tue, 6 Feb 2018 16:48:15 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h31NeeUXL9yU7R2Yb4mynZARITWdaJeJqTMLzgQtKsM=; b=UBW3sjxXiaaaSup07qEIjhv3D24YUUTp1qMVT6dWyOK8yMxuAvrRpPriPaPkN7/QIR F8c3ptyo9zA0G/Butz/BuTuUSlI7O9YvjGIZt8ZnsJlWrqgd+4+B7kdvNdxkFSEMC+IK mehiytcGxrYWr3DIq7RuE7SBRQ87dSN5gTdcI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h31NeeUXL9yU7R2Yb4mynZARITWdaJeJqTMLzgQtKsM=; b=syKM9/LJm3qSrTPYdHikAJCRHHyJ2zbEM3B9/nLemCB7IezhwGCpJCMM5pdnQ1Ztbv XGtFbtW5+uIAd9wiIQF8gkY3NzqjqeO1k8Cn3KtOXZvOkChyZJ7ROmjjBVUvzCPTicxk aUcwwuMAW4tacjsNqA44T7PrlKvg/MBvsn7TXThS4YSwEat06NTvkuZw/tv6vTG7GHhB 7sFgTY8OO3VAkKcfh8m2zGqPsq0/ASMH2q3+LpNRIFJD3sEyhe5h1xvncCDAZn4p8NVM QQG9kZM+urGJH2Y2B9Am8CjOf8xoWs4kWvvroMFjqJmZAGpQBAY0msnQiHZqyaPdN6nA LZRA== X-Gm-Message-State: APf1xPCS7wbCeG73bhE3Ohf2IZ37+ortmu/zG7dKjn1+eyHEOg8XQnOP WRnGx4ISpN47v+AEvJanMglsXA== X-Google-Smtp-Source: AH8x225DF5FnqV9UQZH7cdb9Lx2hViWy2iysGl+YiodM0sjjd77sD5eqzeTfe8j2CRRQZSHuMt5Vsw== X-Received: by 10.223.163.207 with SMTP id m15mr2968527wrb.174.1517935697375; Tue, 06 Feb 2018 08:48:17 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org, peter.maydell@linaro.org, laurent@vivier.eu, bharata@linux.vnet.ibm.com, andrew@andrewdutcher.com Date: Tue, 6 Feb 2018 16:47:54 +0000 Message-Id: <20180206164815.10084-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180206164815.10084-1-alex.bennee@linaro.org> References: <20180206164815.10084-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v4 01/22] fpu/softfloat: implement float16_squash_input_denormal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell --- fpu/softfloat.c | 15 +++++++++++++++ include/fpu/softfloat.h | 1 + 2 files changed, 16 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 433c5dad2d..3a4ab1355f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3488,6 +3488,21 @@ static float16 roundAndPackFloat16(flag zSign, int z= Exp, return packFloat16(zSign, zExp, zSig >> 13); } =20 +/*------------------------------------------------------------------------= ---- +| If `a' is denormal and we are in flush-to-zero mode then set the +| input-denormal exception and return zero. Otherwise just return the valu= e. +*-------------------------------------------------------------------------= ---*/ +float16 float16_squash_input_denormal(float16 a, float_status *status) +{ + if (status->flush_inputs_to_zero) { + if (extractFloat16Exp(a) =3D=3D 0 && extractFloat16Frac(a) !=3D 0)= { + float_raise(float_flag_input_denormal, status); + return make_float16(float16_val(a) & 0x8000); + } + } + return a; +} + static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr, uint32_t *zSigPtr) { diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 0f96a0edd1..d5e99667b6 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -277,6 +277,7 @@ void float_raise(uint8_t flags, float_status *status); | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the valu= e. *-------------------------------------------------------------------------= ---*/ +float16 float16_squash_input_denormal(float16 a, float_status *status); float32 float32_squash_input_denormal(float32 a, float_status *status); float64 float64_squash_input_denormal(float64 a, float_status *status); =20 --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517936025597415.27579403018603; Tue, 6 Feb 2018 08:53:45 -0800 (PST) Received: from localhost ([::1]:37476 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6V2-0004sb-Lw for importer@patchew.org; Tue, 06 Feb 2018 11:53:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33390) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6Pu-0000T5-50 for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ej6Ps-0004hi-4i for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:22 -0500 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:55163) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ej6Pr-0004g3-UG for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:20 -0500 Received: by mail-wm0-x244.google.com with SMTP id i186so4987193wmi.4 for ; Tue, 06 Feb 2018 08:48:19 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id r188sm10454338wmb.40.2018.02.06.08.48.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Feb 2018 08:48:16 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 3F4833E027B; Tue, 6 Feb 2018 16:48:15 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BAFRdaYLrQzoTHM/D56Ivrx3doxZ9W9pIAbUfGIwFy4=; b=WQywmFVMtMeYVZDpgBQ8fAyw1Ex0TGldi35YeCRUq491n0Mo6/tgY7dIMRykyvvWTj cgyK47YfI7SErenlw6zRs6qmGweLI7taNX1d57dmu28k+xkXeMcKlnSR3JcxJAg03VX3 qs3v7FrMm2TFfdBjz70lydjQyCN6QNvtwbgU0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BAFRdaYLrQzoTHM/D56Ivrx3doxZ9W9pIAbUfGIwFy4=; b=PUsE/GgDzYK6fSpYXFVZZ7nNJ2vPuxOkLjzCS3VomjmOHzdIobFPM1zFA7tmv9xpvz NM29Aoh9LDvTkM0/8TrhyqstpT2de9m9DUnLQ+lqFoMw2ZwlgjpKKbPxV1jGaNqbr4n8 BcQkYNS9e50/zAj3ivZnq6o9pHvyB253RlSd8+YGRdLgoyC6CUqA52Nz1KuHaMJ6iDC8 aErmfuUgY3LNOvE7gNttB1390YlCP+gX32gJy2ciVpPshnmQQIMusc7gnFjhHC7886Nm k+dcjJ4sPN6a1FdxFZUt3/tP0hP3bUM2ufh7iklDLRpD67pgiOdzVKilO2FjXPRs6Qqj OR5w== X-Gm-Message-State: APf1xPCjkco8aflq+amBp3FycbMLv3WZE1sHWOGDegqQpN9TOq7cQuIS SiCzL3KX1pEuC9MykBpwwph13g== X-Google-Smtp-Source: AH8x225wEuv0Mc7avmTDvW4BF99DkWvs8DJoXhDSsXLGDSk300bkwMo67pC3PSrQxw0XNyE5xOEqNA== X-Received: by 10.28.88.129 with SMTP id m123mr2366811wmb.64.1517935698666; Tue, 06 Feb 2018 08:48:18 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org, peter.maydell@linaro.org, laurent@vivier.eu, bharata@linux.vnet.ibm.com, andrew@andrewdutcher.com Date: Tue, 6 Feb 2018 16:47:55 +0000 Message-Id: <20180206164815.10084-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180206164815.10084-1-alex.bennee@linaro.org> References: <20180206164815.10084-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v4 02/22] include/fpu/softfloat: remove USE_SOFTFLOAT_STRUCT_TYPES X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 It's not actively built and when enabled things fail to compile. I'm not sure the type-checking is really helping here. Seeing as we "own" our softfloat now lets remove the cruft. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/fpu/softfloat.h | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index d5e99667b6..52af1412de 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -103,32 +103,6 @@ enum { /*------------------------------------------------------------------------= ---- | Software IEC/IEEE floating-point types. *-------------------------------------------------------------------------= ---*/ -/* Use structures for soft-float types. This prevents accidentally mixing - them with native int/float types. A sufficiently clever compiler and - sane ABI should be able to see though these structs. However - x86/gcc 3.x seems to struggle a bit, so leave them disabled by default.= */ -//#define USE_SOFTFLOAT_STRUCT_TYPES -#ifdef USE_SOFTFLOAT_STRUCT_TYPES -typedef struct { - uint16_t v; -} float16; -#define float16_val(x) (((float16)(x)).v) -#define make_float16(x) __extension__ ({ float16 f16_val =3D {x}; f16_val;= }) -#define const_float16(x) { x } -typedef struct { - uint32_t v; -} float32; -/* The cast ensures an error if the wrong type is passed. */ -#define float32_val(x) (((float32)(x)).v) -#define make_float32(x) __extension__ ({ float32 f32_val =3D {x}; f32_val;= }) -#define const_float32(x) { x } -typedef struct { - uint64_t v; -} float64; -#define float64_val(x) (((float64)(x)).v) -#define make_float64(x) __extension__ ({ float64 f64_val =3D {x}; f64_val;= }) -#define const_float64(x) { x } -#else typedef uint16_t float16; typedef uint32_t float32; typedef uint64_t float64; @@ -141,7 +115,6 @@ typedef uint64_t float64; #define const_float16(x) (x) #define const_float32(x) (x) #define const_float64(x) (x) -#endif typedef struct { uint64_t low; uint16_t high; --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517935846045569.5339593363234; Tue, 6 Feb 2018 08:50:46 -0800 (PST) Received: from localhost ([::1]:37451 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6SD-00023p-7j for importer@patchew.org; Tue, 06 Feb 2018 11:50:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33406) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6Pu-0000TQ-Oa for qemu-devel@nongnu.org; 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Tue, 06 Feb 2018 08:48:19 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org, peter.maydell@linaro.org, laurent@vivier.eu, bharata@linux.vnet.ibm.com, andrew@andrewdutcher.com Date: Tue, 6 Feb 2018 16:47:56 +0000 Message-Id: <20180206164815.10084-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180206164815.10084-1-alex.bennee@linaro.org> References: <20180206164815.10084-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v4 03/22] fpu/softfloat-types: new header to prevent excessive re-builds X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The main culprit here is bswap.h which pulled in softfloat.h so it could use the types in its CPU_Float* and ldfl/stfql functions. As bswap.h is very widely included this added a compile dependency every time we touch softfloat.h. Move the typedefs for each float type into their own file so we don't re-build the world every time we tweak the main softfloat.h header. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - new in v3 --- include/fpu/softfloat-types.h | 115 ++++++++++++++++++++++++++++++++++++++= ++++ include/fpu/softfloat.h | 31 +----------- include/qemu/bswap.h | 2 +- 3 files changed, 117 insertions(+), 31 deletions(-) create mode 100644 include/fpu/softfloat-types.h diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h new file mode 100644 index 0000000000..8210a94ea1 --- /dev/null +++ b/include/fpu/softfloat-types.h @@ -0,0 +1,115 @@ +/* + * QEMU float support + * + * The code in this source file is derived from release 2a of the SoftFloat + * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and + * some later contributions) are provided under that license, as detailed = below. + * It has subsequently been modified by contributors to the QEMU Project, + * so some portions are provided under: + * the SoftFloat-2a license + * the BSD license + * GPL-v2-or-later + * + * This header holds definitions for code that might be dealing with + * softfloat types but not need access to the actual library functions. + */ +/* +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +This C header file is part of the SoftFloat IEC/IEEE Floating-point +Arithmetic Package, Release 2a. + +Written by John R. Hauser. This work was made possible in part by the +International Computer Science Institute, located at Suite 600, 1947 Center +Street, Berkeley, California 94704. Funding was partially provided by the +National Science Foundation under grant MIP-9311980. The original version +of this code was written as part of a project to build a fixed-point vector +processor in collaboration with the University of California at Berkeley, +overseen by Profs. Nelson Morgan and John Wawrzynek. More information +is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ +arithmetic/SoftFloat.html'. + +THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort +has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT +TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO +PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY +AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. + +Derivative works are acceptable, even for commercial purposes, so long as +(1) they include prominent notice that the work is derivative, and (2) they +include prominent notice akin to these four paragraphs for those parts of +this code that are retained. + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +*/ + +/* BSD licensing: + * Copyright (c) 2006, Fabrice Bellard + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are = met: + * + * 1. Redistributions of source code must retain the above copyright notic= e, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright no= tice, + * this list of conditions and the following disclaimer in the documentati= on + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contri= butors + * may be used to endorse or promote products derived from this software w= ithout + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS= IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, T= HE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP= OSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS = BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Portions of this work are licensed under the terms of the GNU GPL, + * version 2 or later. See the COPYING file in the top-level directory. + */ + +#ifndef SOFTFLOAT_TYPES_H +#define SOFTFLOAT_TYPES_H + +/* + * Software IEC/IEEE floating-point types. + */ + +typedef uint16_t float16; +typedef uint32_t float32; +typedef uint64_t float64; +#define float16_val(x) (x) +#define float32_val(x) (x) +#define float64_val(x) (x) +#define make_float16(x) (x) +#define make_float32(x) (x) +#define make_float64(x) (x) +#define const_float16(x) (x) +#define const_float32(x) (x) +#define const_float64(x) (x) +typedef struct { + uint64_t low; + uint16_t high; +} floatx80; +#define make_floatx80(exp, mant) ((floatx80) { mant, exp }) +#define make_floatx80_init(exp, mant) { .low =3D mant, .high =3D exp } +typedef struct { +#ifdef HOST_WORDS_BIGENDIAN + uint64_t high, low; +#else + uint64_t low, high; +#endif +} float128; +#define make_float128(high_, low_) ((float128) { .high =3D high_, .low =3D= low_ }) +#define make_float128_init(high_, low_) { .high =3D high_, .low =3D low_ } + +#endif /* SOFTFLOAT_TYPES_H */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 52af1412de..4e16e22e58 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -100,36 +100,7 @@ enum { float_relation_unordered =3D 2 }; =20 -/*------------------------------------------------------------------------= ---- -| Software IEC/IEEE floating-point types. -*-------------------------------------------------------------------------= ---*/ -typedef uint16_t float16; -typedef uint32_t float32; -typedef uint64_t float64; -#define float16_val(x) (x) -#define float32_val(x) (x) -#define float64_val(x) (x) -#define make_float16(x) (x) -#define make_float32(x) (x) -#define make_float64(x) (x) -#define const_float16(x) (x) -#define const_float32(x) (x) -#define const_float64(x) (x) -typedef struct { - uint64_t low; - uint16_t high; -} floatx80; -#define make_floatx80(exp, mant) ((floatx80) { mant, exp }) -#define make_floatx80_init(exp, mant) { .low =3D mant, .high =3D exp } -typedef struct { -#ifdef HOST_WORDS_BIGENDIAN - uint64_t high, low; -#else - uint64_t low, high; -#endif -} float128; -#define make_float128(high_, low_) ((float128) { .high =3D high_, .low =3D= low_ }) -#define make_float128_init(high_, low_) { .high =3D high_, .low =3D low_ } +#include "fpu/softfloat-types.h" =20 /*------------------------------------------------------------------------= ---- | Software IEC/IEEE floating-point underflow tininess-detection mode. diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index 09c78fd28a..3f28f661b1 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -1,7 +1,7 @@ #ifndef BSWAP_H #define BSWAP_H =20 -#include "fpu/softfloat.h" +#include "fpu/softfloat-types.h" =20 #ifdef CONFIG_MACHINE_BSWAP_H # include --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v4 04/22] target/*/cpu.h: remove softfloat.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Guan Xuetao , Eduardo Habkost , Bastian Koppelmann , Anthony Green , Chris Wulff , Mark Cave-Ayland , qemu-devel@nongnu.org, Alexander Graf , Max Filippov , "open list:S390" , "open list:ARM" , "open list:PowerPC" , Artyom Tarasenko , "Edgar E. Iglesias" , Paolo Bonzini , Stafford Horne , David Gibson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson [For PPC parts] Acked-by: David Gibson --- include/fpu/softfloat-types.h | 64 +++++++++++++++++++++++++++++++++++++= ++++ include/fpu/softfloat.h | 53 ---------------------------------- target/alpha/cpu.h | 2 -- target/arm/cpu.c | 1 + target/arm/cpu.h | 2 -- target/arm/helper-a64.c | 1 + target/arm/helper.c | 1 + target/arm/neon_helper.c | 1 + target/hppa/cpu.c | 1 + target/hppa/cpu.h | 1 - target/hppa/op_helper.c | 2 +- target/i386/cpu.h | 4 --- target/i386/fpu_helper.c | 1 + target/m68k/cpu.c | 2 +- target/m68k/cpu.h | 1 - target/m68k/fpu_helper.c | 1 + target/m68k/helper.c | 1 + target/m68k/translate.c | 2 ++ target/microblaze/cpu.c | 1 + target/microblaze/cpu.h | 2 +- target/microblaze/op_helper.c | 1 + target/moxie/cpu.h | 1 - target/nios2/cpu.h | 1 - target/openrisc/cpu.h | 1 - target/openrisc/fpu_helper.c | 1 + target/ppc/cpu.h | 1 - target/ppc/fpu_helper.c | 1 + target/ppc/int_helper.c | 1 + target/ppc/translate_init.c | 1 + target/s390x/cpu.c | 1 + target/s390x/cpu.h | 2 -- target/s390x/fpu_helper.c | 1 + target/sh4/cpu.c | 1 + target/sh4/cpu.h | 2 -- target/sh4/op_helper.c | 1 + target/sparc/cpu.h | 2 -- target/sparc/fop_helper.c | 1 + target/tricore/cpu.h | 1 - target/tricore/fpu_helper.c | 1 + target/tricore/helper.c | 1 + target/unicore32/cpu.c | 1 + target/unicore32/cpu.h | 1 - target/unicore32/ucf64_helper.c | 1 + target/xtensa/cpu.h | 1 - target/xtensa/op_helper.c | 1 + 45 files changed, 93 insertions(+), 79 deletions(-) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8210a94ea1..4e378cb612 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -80,6 +80,12 @@ this code that are retained. #ifndef SOFTFLOAT_TYPES_H #define SOFTFLOAT_TYPES_H =20 +/* This 'flag' type must be able to hold at least 0 and 1. It should + * probably be replaced with 'bool' but the uses would need to be audited + * to check that they weren't accidentally relying on it being a larger ty= pe. + */ +typedef uint8_t flag; + /* * Software IEC/IEEE floating-point types. */ @@ -112,4 +118,62 @@ typedef struct { #define make_float128(high_, low_) ((float128) { .high =3D high_, .low =3D= low_ }) #define make_float128_init(high_, low_) { .high =3D high_, .low =3D low_ } =20 +/* + * Software IEC/IEEE floating-point underflow tininess-detection mode. + */ + +enum { + float_tininess_after_rounding =3D 0, + float_tininess_before_rounding =3D 1 +}; + +/* + *Software IEC/IEEE floating-point rounding mode. + */ + +enum { + float_round_nearest_even =3D 0, + float_round_down =3D 1, + float_round_up =3D 2, + float_round_to_zero =3D 3, + float_round_ties_away =3D 4, + /* Not an IEEE rounding mode: round to the closest odd mantissa value = */ + float_round_to_odd =3D 5, +}; + +/* + * Software IEC/IEEE floating-point exception flags. + */ + +enum { + float_flag_invalid =3D 1, + float_flag_divbyzero =3D 4, + float_flag_overflow =3D 8, + float_flag_underflow =3D 16, + float_flag_inexact =3D 32, + float_flag_input_denormal =3D 64, + float_flag_output_denormal =3D 128 +}; + + +/* + * Floating Point Status. Individual architectures may maintain + * several versions of float_status for different functions. The + * correct status for the operation is then passed by reference to + * most of the softfloat functions. + */ + +typedef struct float_status { + signed char float_detect_tininess; + signed char float_rounding_mode; + uint8_t float_exception_flags; + signed char floatx80_rounding_precision; + /* should denormalised results go to zero and set the inexact flag? */ + flag flush_to_zero; + /* should denormalised inputs go to zero and set the input_denormal fl= ag? */ + flag flush_inputs_to_zero; + flag default_nan_mode; + flag snan_bit_is_one; +} float_status; + #endif /* SOFTFLOAT_TYPES_H */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 4e16e22e58..f3b9008f78 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -82,12 +82,6 @@ this code that are retained. #ifndef SOFTFLOAT_H #define SOFTFLOAT_H =20 -/* This 'flag' type must be able to hold at least 0 and 1. It should - * probably be replaced with 'bool' but the uses would need to be audited - * to check that they weren't accidentally relying on it being a larger ty= pe. - */ -typedef uint8_t flag; - #define LIT64( a ) a##LL =20 /*------------------------------------------------------------------------= ---- @@ -102,53 +96,6 @@ enum { =20 #include "fpu/softfloat-types.h" =20 -/*------------------------------------------------------------------------= ---- -| Software IEC/IEEE floating-point underflow tininess-detection mode. -*-------------------------------------------------------------------------= ---*/ -enum { - float_tininess_after_rounding =3D 0, - float_tininess_before_rounding =3D 1 -}; - -/*------------------------------------------------------------------------= ---- -| Software IEC/IEEE floating-point rounding mode. -*-------------------------------------------------------------------------= ---*/ -enum { - float_round_nearest_even =3D 0, - float_round_down =3D 1, - float_round_up =3D 2, - float_round_to_zero =3D 3, - float_round_ties_away =3D 4, - /* Not an IEEE rounding mode: round to the closest odd mantissa value = */ - float_round_to_odd =3D 5, -}; - -/*------------------------------------------------------------------------= ---- -| Software IEC/IEEE floating-point exception flags. -*-------------------------------------------------------------------------= ---*/ -enum { - float_flag_invalid =3D 1, - float_flag_divbyzero =3D 4, - float_flag_overflow =3D 8, - float_flag_underflow =3D 16, - float_flag_inexact =3D 32, - float_flag_input_denormal =3D 64, - float_flag_output_denormal =3D 128 -}; - -typedef struct float_status { - signed char float_detect_tininess; - signed char float_rounding_mode; - uint8_t float_exception_flags; - signed char floatx80_rounding_precision; - /* should denormalised results go to zero and set the inexact flag? */ - flag flush_to_zero; - /* should denormalised inputs go to zero and set the input_denormal fl= ag? */ - flag flush_inputs_to_zero; - flag default_nan_mode; - flag snan_bit_is_one; -} float_status; - static inline void set_float_detect_tininess(int val, float_status *status) { status->float_detect_tininess =3D val; diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 09720c2f3b..a79fc2e780 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -33,8 +33,6 @@ =20 #include "exec/cpu-defs.h" =20 -#include "fpu/softfloat.h" - #define ICACHE_LINE_SIZE 32 #define DCACHE_LINE_SIZE 32 =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9da6ea505c..2d6ac054bd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -34,6 +34,7 @@ #include "sysemu/hw_accel.h" #include "kvm_arm.h" #include "disas/capstone.h" +#include "fpu/softfloat.h" =20 static void arm_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d2bb59eded..c7c922d79b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -39,8 +39,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#include "fpu/softfloat.h" - #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 06fd321fae..10e08bdc1f 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -31,6 +31,7 @@ #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "tcg.h" +#include "fpu/softfloat.h" #include /* For crc32 */ =20 /* C2.4.7 Multiply and divide */ diff --git a/target/arm/helper.c b/target/arm/helper.c index bfce09643b..4ef99882c4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -15,6 +15,7 @@ #include /* For crc32 */ #include "exec/semihost.h" #include "sysemu/kvm.h" +#include "fpu/softfloat.h" =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ =20 diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index 689491cad3..a1ec6537eb 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -11,6 +11,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "fpu/softfloat.h" =20 #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 5213347720..9224331165 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "qemu-common.h" #include "exec/exec-all.h" +#include "fpu/softfloat.h" =20 =20 static void hppa_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7640c81221..c88d844938 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -51,7 +51,6 @@ #define CPUArchState struct CPUHPPAState =20 #include "exec/cpu-defs.h" -#include "fpu/softfloat.h" =20 #define TARGET_PAGE_BITS 12 =20 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 4ee936bf86..a3af62daf7 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -24,7 +24,7 @@ #include "exec/cpu_ldst.h" #include "sysemu/sysemu.h" #include "qemu/timer.h" - +#include "fpu/softfloat.h" =20 void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f91e37d25d..faf39ec1ce 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -52,10 +52,6 @@ =20 #define CPUArchState struct CPUX86State =20 -#ifdef CONFIG_TCG -#include "fpu/softfloat.h" -#endif - enum { R_EAX =3D 0, R_ECX =3D 1, diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c index 9014b6f88a..ea5a0c4861 100644 --- a/target/i386/fpu_helper.c +++ b/target/i386/fpu_helper.c @@ -24,6 +24,7 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "fpu/softfloat.h" =20 #define FPU_RC_MASK 0xc00 #define FPU_RC_NEAR 0x000 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 98919b358b..cbd5f08ce8 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -24,7 +24,7 @@ #include "qemu-common.h" #include "migration/vmstate.h" #include "exec/exec-all.h" - +#include "fpu/softfloat.h" =20 static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 627fb787b6..e250dc5278 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -28,7 +28,6 @@ #include "qemu-common.h" #include "exec/cpu-defs.h" #include "cpu-qom.h" -#include "fpu/softfloat.h" =20 #define OS_BYTE 0 #define OS_WORD 1 diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 665e7609af..3c5a82aaa0 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "fpu/softfloat.h" =20 /* Undefined offsets may be different on various FPU. * On 68040 they return 0.0 (floatx80_zero) diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 20155c7801..917d46efcc 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -24,6 +24,7 @@ #include "exec/gdbstub.h" =20 #include "exec/helper-proto.h" +#include "fpu/softfloat.h" =20 #define SIGNBIT (1u << 31) =20 diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 34db97b8a0..bbbc3d8a0e 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -32,6 +32,8 @@ =20 #include "trace-tcg.h" #include "exec/log.h" +#include "fpu/softfloat.h" + =20 //#define DEBUG_DISPATCH 1 =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 5700652e06..393520f3ef 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -28,6 +28,7 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "exec/exec-all.h" +#include "fpu/softfloat.h" =20 static const struct { const char *name; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f3e7405a62..1fe21c8539 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -28,7 +28,7 @@ #define CPUArchState struct CPUMBState =20 #include "exec/cpu-defs.h" -#include "fpu/softfloat.h" +#include "fpu/softfloat-types.h" struct CPUMBState; typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 869072a2d1..1b4fe796e7 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -24,6 +24,7 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "fpu/softfloat.h" =20 #define D(x) =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index a01f480821..d85e1fc061 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -34,7 +34,6 @@ #define MOXIE_EX_BREAK 16 =20 #include "exec/cpu-defs.h" -#include "fpu/softfloat.h" =20 #define TARGET_PAGE_BITS 12 /* 4k */ =20 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 204b39add7..cd4e40d1b4 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -27,7 +27,6 @@ #define CPUArchState struct CPUNios2State =20 #include "exec/cpu-defs.h" -#include "fpu/softfloat.h" #include "qom/cpu.h" struct CPUNios2State; typedef struct CPUNios2State CPUNios2State; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index fb46cc9986..5050b1135c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -29,7 +29,6 @@ struct OpenRISCCPU; =20 #include "qemu-common.h" #include "exec/cpu-defs.h" -#include "fpu/softfloat.h" #include "qom/cpu.h" =20 #define TYPE_OPENRISC_CPU "or1k-cpu" diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index 1375cea948..977a1e8e55 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exception.h" +#include "fpu/softfloat.h" =20 static inline uint32_t ieee_ex_to_openrisc(OpenRISCCPU *cpu, int fexcp) { diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 9f8cbbe7aa..7bde1884a1 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -79,7 +79,6 @@ =20 #include "exec/cpu-defs.h" #include "cpu-qom.h" -#include "fpu/softfloat.h" =20 #if defined (TARGET_PPC64) #define PPC_ELF_MACHINE EM_PPC64 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c4dab159e4..9ae418a577 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -21,6 +21,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "internal.h" +#include "fpu/softfloat.h" =20 static inline float128 float128_snan_to_qnan(float128 x) { diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 3a50f1e1b7..35bdf09773 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -23,6 +23,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "crypto/aes.h" +#include "fpu/softfloat.h" =20 #include "helper_regs.h" /*************************************************************************= ****/ diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 55c99c97e3..54ec2e122a 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -36,6 +36,7 @@ #include "sysemu/qtest.h" #include "qemu/cutils.h" #include "disas/capstone.h" +#include "fpu/softfloat.h" =20 //#define PPC_DUMP_CPU //#define PPC_DEBUG_SPR diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d2e6b9f5c7..7acb827f1b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -42,6 +42,7 @@ #include "sysemu/arch_init.h" #include "sysemu/sysemu.h" #endif +#include "fpu/softfloat.h" =20 #define CR0_RESET 0xE0UL #define CR14_RESET 0xC2000000UL; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index a1123ad621..96264ad4cb 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -41,8 +41,6 @@ =20 #include "exec/cpu-all.h" =20 -#include "fpu/softfloat.h" - #define NB_MMU_MODES 4 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index 334159119f..43f8bf1c94 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "fpu/softfloat.h" =20 /* #define DEBUG_HELPER */ #ifdef DEBUG_HELPER diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index e0b99fbc89..4f8c830fe3 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -25,6 +25,7 @@ #include "qemu-common.h" #include "migration/vmstate.h" #include "exec/exec-all.h" +#include "fpu/softfloat.h" =20 =20 static void superh_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 52a4568dd5..a649b68d78 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -40,8 +40,6 @@ =20 #include "exec/cpu-defs.h" =20 -#include "fpu/softfloat.h" - #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ =20 #define TARGET_PHYS_ADDR_SPACE_BITS 32 diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 4b8bbf63b4..4f825bae5a 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -21,6 +21,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "fpu/softfloat.h" =20 #ifndef CONFIG_USER_ONLY =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 3eaffb354e..9724134a5b 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -29,8 +29,6 @@ =20 #include "exec/cpu-defs.h" =20 -#include "fpu/softfloat.h" - /*#define EXCP_INTERRUPT 0x100*/ =20 /* trap definitions */ diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index c7fb176e4c..b6642fd1d7 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "fpu/softfloat.h" =20 #define QT0 (env->qt0) #define QT1 (env->qt1) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index f41d2ceb69..e7dfe4bcc6 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -24,7 +24,6 @@ #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" -#include "fpu/softfloat.h" =20 #define CPUArchState struct CPUTriCoreState =20 diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c index 7979bb6692..df162902d6 100644 --- a/target/tricore/fpu_helper.c +++ b/target/tricore/fpu_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "fpu/softfloat.h" =20 #define QUIET_NAN 0x7fc00000 #define ADD_NAN 0x7fc00001 diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 378c2a4a76..45276d3782 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -19,6 +19,7 @@ =20 #include "cpu.h" #include "exec/exec-all.h" +#include "fpu/softfloat.h" =20 enum { TLBRET_DIRTY =3D -4, diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 17dc1504d7..93cbae39d9 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -18,6 +18,7 @@ #include "qemu-common.h" #include "migration/vmstate.h" #include "exec/exec-all.h" +#include "fpu/softfloat.h" =20 static void uc32_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index a3cc71416d..42e1d52478 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -23,7 +23,6 @@ #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" -#include "fpu/softfloat.h" =20 #define NB_MMU_MODES 2 =20 diff --git a/target/unicore32/ucf64_helper.c b/target/unicore32/ucf64_helpe= r.c index 6c919010c3..fad3fa6618 100644 --- a/target/unicore32/ucf64_helper.c +++ b/target/unicore32/ucf64_helper.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "fpu/softfloat.h" =20 /* * The convention used for UniCore-F64 instructions: diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f300c02c07..49c2e3cf9a 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -36,7 +36,6 @@ #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" -#include "fpu/softfloat.h" #include "xtensa-isa.h" =20 #define NB_MMU_MODES 4 diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 43182b113e..7486b99799 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -34,6 +34,7 @@ #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" #include "qemu/timer.h" +#include "fpu/softfloat.h" =20 void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) 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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v4 05/22] include/fpu/softfloat: implement float16_abs helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- include/fpu/softfloat.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index f3b9008f78..1d34f2c3eb 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -265,6 +265,13 @@ static inline int float16_is_zero_or_denormal(float16 = a) return (float16_val(a) & 0x7c00) =3D=3D 0; } =20 +static inline float16 float16_abs(float16 a) +{ + /* Note that abs does *not* handle NaN specially, nor does + * it flush denormal inputs to zero. + */ + return make_float16(float16_val(a) & 0x7fff); +} /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517935845655529.1710207552851; Tue, 6 Feb 2018 08:50:45 -0800 (PST) Received: from localhost ([::1]:37449 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6SC-00022e-Qi for importer@patchew.org; Tue, 06 Feb 2018 11:50:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33440) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6Px-0000VM-8q for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ej6Pw-0004pq-Gr for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:25 -0500 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:39879) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ej6Pw-0004o2-A7 for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:24 -0500 Received: by mail-wm0-x244.google.com with SMTP id b21so5127961wme.4 for ; Tue, 06 Feb 2018 08:48:24 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id g8sm23408356wra.18.2018.02.06.08.48.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Feb 2018 08:48:21 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id B8BA73E0633; Tue, 6 Feb 2018 16:48:15 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bPH2w3PfFpdRcohbDu83KT6KDKSPHYODix9ErvUA+Fg=; b=Zdnz3y/a0bEZz3T6ywMOO5g0Dhi1EHPXLH3f07z1XSr6hkcNn+56LDZ/hJAZzSR+Ml 408TRUQTbri/QYZIJ+EABFLV2iTiyY4jPcnYD6i8F1GemagWeccmVaXn9DXgVbTJm6cF 6K2S9Zsin2qLsva6q2AY9yT/Pnhni6mdB8ekU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bPH2w3PfFpdRcohbDu83KT6KDKSPHYODix9ErvUA+Fg=; b=FbaLevVZawAMWPClX1yTFpLtyx6+WYi2xtcKWI6Uc0PJgAHk9H4wrf+AM4+GOgfbzS TJ0nqp2YkJvFp/mJ2U+wC913bxts246S/mPKglEHkCn5fgWcEkcOePQ0umVsE/KvtUnq waRA9krYz+DB3p0/QQaEiE5rePmm6H5637/mFjcrDxUYDrM6OJigyNkUcOik3G78dLh9 s4On4usimLDpHNtPu5CPdYzDj9NAe3sBwfFghiugmjH9Kq6yREDUellEDDYUr+eVm/a1 57OiMp0Xe83Hcerhwv3OmFbYF+ZRppe3o8D+VjJX43hSBdVpts8bwJuOywCgQr9jZ6K/ HPbQ== X-Gm-Message-State: APf1xPBKW1xGzy+hSLTT1GnbMFfqPqArQSOR+uhN/XrdbzIerYYLEFg9 tfFQ02wR83wFA7O0ozYY/uL7vw== X-Google-Smtp-Source: AH8x224EAqomSPYrxByZH0+4MnHd/5UmD2z5XkUrhuHLPSp39cpO2Ksn0ace0RME3s8IHNebboI1CA== X-Received: by 10.28.177.7 with SMTP id a7mr2305755wmf.143.1517935703182; Tue, 06 Feb 2018 08:48:23 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org, peter.maydell@linaro.org, laurent@vivier.eu, bharata@linux.vnet.ibm.com, andrew@andrewdutcher.com Date: Tue, 6 Feb 2018 16:47:59 +0000 Message-Id: <20180206164815.10084-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180206164815.10084-1-alex.bennee@linaro.org> References: <20180206164815.10084-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v4 06/22] include/fpu/softfloat: implement float16_chs helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell --- include/fpu/softfloat.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 1d34f2c3eb..f75aa59100 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -272,6 +272,15 @@ static inline float16 float16_abs(float16 a) */ return make_float16(float16_val(a) & 0x7fff); } + +static inline float16 float16_chs(float16 a) +{ + /* Note that chs does *not* handle NaN specially, nor does + * it flush denormal inputs to zero. + */ + return make_float16(float16_val(a) ^ 0x8000); +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517936228417637.8806928436578; Tue, 6 Feb 2018 08:57:08 -0800 (PST) Received: from localhost ([::1]:37835 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6YN-0008UW-FW for importer@patchew.org; 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Tue, 06 Feb 2018 08:48:27 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org, peter.maydell@linaro.org, laurent@vivier.eu, bharata@linux.vnet.ibm.com, andrew@andrewdutcher.com Date: Tue, 6 Feb 2018 16:48:00 +0000 Message-Id: <20180206164815.10084-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180206164815.10084-1-alex.bennee@linaro.org> References: <20180206164815.10084-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v4 07/22] include/fpu/softfloat: implement float16_set_sign helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/fpu/softfloat.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index f75aa59100..59c06ef192 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -281,6 +281,11 @@ static inline float16 float16_chs(float16 a) return make_float16(float16_val(a) ^ 0x8000); } =20 +static inline float16 float16_set_sign(float16 a, int sign) +{ + return make_float16((float16_val(a) & 0x7fff) | (sign << 15)); +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517935852081219.6047115358084; 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Tue, 06 Feb 2018 08:48:26 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org, peter.maydell@linaro.org, laurent@vivier.eu, bharata@linux.vnet.ibm.com, andrew@andrewdutcher.com Date: Tue, 6 Feb 2018 16:48:01 +0000 Message-Id: <20180206164815.10084-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180206164815.10084-1-alex.bennee@linaro.org> References: <20180206164815.10084-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v4 08/22] include/fpu/softfloat: add some float16 constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This defines the same set of common constants for float 16 as defined for 32 and 64 bit floats. These are often used by target helper functions. I've also removed constants that are not used by anybody. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- v2 - fixup constants, remove unused onces --- include/fpu/softfloat.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 59c06ef192..23824a3000 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -286,6 +286,11 @@ static inline float16 float16_set_sign(float16 a, int = sign) return make_float16((float16_val(a) & 0x7fff) | (sign << 15)); } =20 +#define float16_zero make_float16(0) +#define float16_one make_float16(0x3c00) +#define float16_half make_float16(0x3800) +#define float16_infinity make_float16(0x7c00) + /*------------------------------------------------------------------------= ---- | The pattern for a default generated half-precision NaN. *-------------------------------------------------------------------------= ---*/ @@ -392,8 +397,6 @@ static inline float32 float32_set_sign(float32 a, int s= ign) =20 #define float32_zero make_float32(0) #define float32_one make_float32(0x3f800000) -#define float32_ln2 make_float32(0x3f317218) -#define float32_pi make_float32(0x40490fdb) #define float32_half make_float32(0x3f000000) #define float32_infinity make_float32(0x7f800000) =20 @@ -506,7 +509,6 @@ static inline float64 float64_set_sign(float64 a, int s= ign) #define float64_zero make_float64(0) #define float64_one make_float64(0x3ff0000000000000LL) #define float64_ln2 make_float64(0x3fe62e42fefa39efLL) -#define float64_pi make_float64(0x400921fb54442d18LL) #define float64_half make_float64(0x3fe0000000000000LL) #define float64_infinity make_float64(0x7ff0000000000000LL) =20 --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v4 09/22] fpu/softfloat: improve comments on ARM NaN propagation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Mention the pseudo-code fragment from which this is based. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index de2c5d5702..4be0fb21ba 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -445,9 +445,10 @@ static float32 commonNaNToFloat32(commonNaNT a, float_= status *status) =20 #if defined(TARGET_ARM) static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) + flag aIsLargerSignificand) { - /* ARM mandated NaN propagation rules: take the first of: + /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take + * the first of: * 1. A if it is signaling * 2. B if it is signaling * 3. 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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v4 10/22] fpu/softfloat: move the extract functions to the top of the file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This is pure code-motion during re-factoring as the helpers will be needed earlier. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell --- v2 - fix minor white space nit --- fpu/softfloat.c | 120 +++++++++++++++++++++++++---------------------------= ---- 1 file changed, 54 insertions(+), 66 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 3a4ab1355f..297e48f5c9 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -132,6 +132,60 @@ static inline flag extractFloat16Sign(float16 a) return float16_val(a)>>15; } =20 +/*------------------------------------------------------------------------= ---- +| Returns the fraction bits of the single-precision floating-point value `= a'. +*-------------------------------------------------------------------------= ---*/ + +static inline uint32_t extractFloat32Frac(float32 a) +{ + return float32_val(a) & 0x007FFFFF; +} + +/*------------------------------------------------------------------------= ---- +| Returns the exponent bits of the single-precision floating-point value `= a'. +*-------------------------------------------------------------------------= ---*/ + +static inline int extractFloat32Exp(float32 a) +{ + return (float32_val(a) >> 23) & 0xFF; +} + +/*------------------------------------------------------------------------= ---- +| Returns the sign bit of the single-precision floating-point value `a'. +*-------------------------------------------------------------------------= ---*/ + +static inline flag extractFloat32Sign(float32 a) +{ + return float32_val(a) >> 31; +} + +/*------------------------------------------------------------------------= ---- +| Returns the fraction bits of the double-precision floating-point value `= a'. +*-------------------------------------------------------------------------= ---*/ + +static inline uint64_t extractFloat64Frac(float64 a) +{ + return float64_val(a) & LIT64(0x000FFFFFFFFFFFFF); +} + +/*------------------------------------------------------------------------= ---- +| Returns the exponent bits of the double-precision floating-point value `= a'. +*-------------------------------------------------------------------------= ---*/ + +static inline int extractFloat64Exp(float64 a) +{ + return (float64_val(a) >> 52) & 0x7FF; +} + +/*------------------------------------------------------------------------= ---- +| Returns the sign bit of the double-precision floating-point value `a'. +*-------------------------------------------------------------------------= ---*/ + +static inline flag extractFloat64Sign(float64 a) +{ + return float64_val(a) >> 63; +} + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the @@ -299,39 +353,6 @@ static int64_t roundAndPackUint64(flag zSign, uint64_t= absZ0, return absZ0; } =20 -/*------------------------------------------------------------------------= ---- -| Returns the fraction bits of the single-precision floating-point value `= a'. -*-------------------------------------------------------------------------= ---*/ - -static inline uint32_t extractFloat32Frac( float32 a ) -{ - - return float32_val(a) & 0x007FFFFF; - -} - -/*------------------------------------------------------------------------= ---- -| Returns the exponent bits of the single-precision floating-point value `= a'. -*-------------------------------------------------------------------------= ---*/ - -static inline int extractFloat32Exp(float32 a) -{ - - return ( float32_val(a)>>23 ) & 0xFF; - -} - -/*------------------------------------------------------------------------= ---- -| Returns the sign bit of the single-precision floating-point value `a'. -*-------------------------------------------------------------------------= ---*/ - -static inline flag extractFloat32Sign( float32 a ) -{ - - return float32_val(a)>>31; - -} - /*------------------------------------------------------------------------= ---- | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the valu= e. @@ -492,39 +513,6 @@ static float32 =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the fraction bits of the double-precision floating-point value `= a'. -*-------------------------------------------------------------------------= ---*/ - -static inline uint64_t extractFloat64Frac( float64 a ) -{ - - return float64_val(a) & LIT64( 0x000FFFFFFFFFFFFF ); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the exponent bits of the double-precision floating-point value `= a'. -*-------------------------------------------------------------------------= ---*/ - -static inline int extractFloat64Exp(float64 a) -{ - - return ( float64_val(a)>>52 ) & 0x7FF; - -} - -/*------------------------------------------------------------------------= ---- -| Returns the sign bit of the double-precision floating-point value `a'. -*-------------------------------------------------------------------------= ---*/ - -static inline flag extractFloat64Sign( float64 a ) -{ - - return float64_val(a)>>63; - -} - /*------------------------------------------------------------------------= ---- | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the valu= e. --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517936420024280.87872728688114; Tue, 6 Feb 2018 09:00:20 -0800 (PST) Received: from localhost ([::1]:37982 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6bM-00030F-4w for importer@patchew.org; Tue, 06 Feb 2018 12:00:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35804) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6Wc-0007DN-Ug for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:55:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ej6WY-0001Z1-5G for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:55:19 -0500 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:32773) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ej6WX-0001YK-Lp for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:55:14 -0500 Received: by mail-wm0-x243.google.com with SMTP id x4-v6so18722029wmc.0 for ; Tue, 06 Feb 2018 08:55:13 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id y55sm17962590wry.87.2018.02.06.08.55.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Feb 2018 08:55:11 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 1BF5A3E079E; Tue, 6 Feb 2018 16:48:16 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QSk7rvTnRN7zVjOz/qnoI6MD7fqHW+3DEcMId0sEPMc=; b=Krblsqv3PsaxUhoAsATH1m8cxStu/2Izs99DyFqZAaTdd9zVBWlWOj/qaAu/u8W/L5 5yA8kRrkY1nC0lzHHyVPfUHRDXMtFTsfy8Z5/8eevjOETgF9lDItkTN5m0T5EXcexU1B qr37gc6SnjClA/zsejfPvhlDthsmL2MRJvi7I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QSk7rvTnRN7zVjOz/qnoI6MD7fqHW+3DEcMId0sEPMc=; b=cjBsFD4lNTagZ1EanatKuwb7eZlEmJFGbc7bkLqcT1NuJ9asyvb1N62qJfvRWzlyBw xYdngUu8m1qJUPWFVkBI51utnZYM3UwQgUxm5UPWLUlqox9XKgF68uwocPb2JsYqTYfK V0HcydePakORszBFo+17SSWRfRxAB1sxAOMCQNs/E8xDrbe4qEDHLC4FYWvsNcVXnf0m InzhtJbS8NADfCumdA8HNGNXzodyCAk1d0Aoo2wRdWUTEu+BcldVTuyD/4W7yJ0TEUJO Ve+k88WeLqb2cq0lAZpEHSw8/MavGffKYoqiGlBSei+Du55XC476i6VBvMc1zpvSAbVd WwOQ== X-Gm-Message-State: APf1xPALVlThOmB5nLaYgN5ARQijJzMhPbtEXpoBusB6G9zIiPeDLvoA twWNaGRetjzk6EFL7Vji5yNTdg== X-Google-Smtp-Source: AH8x2245ETSrvn+FlDdlwk75Z+PSQ3lNsXut/+ZC+RIlpLbjFTKWbBZGNDs6r+8Edilrfpx5EF2KyA== X-Received: by 10.28.107.134 with SMTP id a6mr2424828wmi.136.1517936112496; Tue, 06 Feb 2018 08:55:12 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org, peter.maydell@linaro.org, laurent@vivier.eu, bharata@linux.vnet.ibm.com, andrew@andrewdutcher.com Date: Tue, 6 Feb 2018 16:48:04 +0000 Message-Id: <20180206164815.10084-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180206164815.10084-1-alex.bennee@linaro.org> References: <20180206164815.10084-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v4 11/22] fpu/softfloat: define decompose structures X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 These structures pave the way for generic softfloat helper routines that will operate on fully decomposed numbers. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v3 - comment box style - CamelCase structs - hide DECOMPOSED_BINARY_POINT - frac in macro - more comments - add exp_size, frac_size to FloatFmt - compute exp_bias and exp_max from FLOAT_PARAMS - remove include bitops (in next patch) --- fpu/softfloat.c | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 297e48f5c9..568d555595 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -83,7 +83,6 @@ this code that are retained. * target-dependent and needs the TARGET_* macros. */ #include "qemu/osdep.h" - #include "fpu/softfloat.h" =20 /* We only need stdlib for abort() */ @@ -186,6 +185,91 @@ static inline flag extractFloat64Sign(float64 a) return float64_val(a) >> 63; } =20 +/* + * Classify a floating point number. Everything above float_class_qnan + * is a NaN so cls >=3D float_class_qnan is any NaN. + */ + +typedef enum __attribute__ ((__packed__)) { + float_class_unclassified, + float_class_zero, + float_class_normal, + float_class_inf, + float_class_qnan, /* all NaNs from here */ + float_class_snan, + float_class_dnan, + float_class_msnan, /* maybe silenced */ +} FloatClass; + +/* + * Structure holding all of the decomposed parts of a float. The + * exponent is unbiased and the fraction is normalized. All + * calculations are done with a 64 bit fraction and then rounded as + * appropriate for the final format. + * + * Thanks to the packed FloatClass a decent compiler should be able to + * fit the whole structure into registers and avoid using the stack + * for parameter passing. + */ + +typedef struct { + uint64_t frac; + int32_t exp; + FloatClass cls; + bool sign; +} FloatParts; + +#define DECOMPOSED_BINARY_POINT (64 - 2) +#define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT) +#define DECOMPOSED_OVERFLOW_BIT (DECOMPOSED_IMPLICIT_BIT << 1) + +/* Structure holding all of the relevant parameters for a format. + * exp_size: the size of the exponent field + * exp_bias: the offset applied to the exponent field + * exp_max: the maximum normalised exponent + * frac_size: the size of the fraction field + * frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_PO= INT + * The following are computed based the size of fraction + * frac_lsb: least significant bit of fraction + * fram_lsbm1: the bit bellow the least significant bit (for rounding) + * round_mask/roundeven_mask: masks used for rounding + */ +typedef struct { + int exp_size; + int exp_bias; + int exp_max; + int frac_size; + int frac_shift; + uint64_t frac_lsb; + uint64_t frac_lsbm1; + uint64_t round_mask; + uint64_t roundeven_mask; +} FloatFmt; + +/* Expand fields based on the size of exponent and fraction */ +#define FLOAT_PARAMS(E, F) \ + .exp_size =3D E, \ + .exp_bias =3D ((1 << E) - 1) >> 1, \ + .exp_max =3D (1 << E) - 1, \ + .frac_size =3D F, \ + .frac_shift =3D DECOMPOSED_BINARY_POINT - F, \ + .frac_lsb =3D 1ull << (DECOMPOSED_BINARY_POINT - F), \ + .frac_lsbm1 =3D 1ull << ((DECOMPOSED_BINARY_POINT - F) - 1), \ + .round_mask =3D (1ull << (DECOMPOSED_BINARY_POINT - F)) - 1, \ + .roundeven_mask =3D (2ull << (DECOMPOSED_BINARY_POINT - F)) - 1 + +static const FloatFmt float16_params =3D { + FLOAT_PARAMS(5, 10) +}; + +static const FloatFmt float32_params =3D { + FLOAT_PARAMS(8, 23) +}; + +static const FloatFmt float64_params =3D { + FLOAT_PARAMS(11, 52) +}; + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v4 12/22] fpu/softfloat: re-factor add/sub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We can now add float16_add/sub and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 add and sub functions. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v3 - renames for FloatParts - shorten internal names - fix comment style - use FloatFmt values for for extract/deposit in raw_pack/unpack - move #include bitops from previous patch - add is_nan helper - avoid temp variables where we can v4 - fewer lines for pack_raw - is_nan/is_snan/is_qnan with unlikey() annotation for is_nan - pick_nan_parts -> pick_nan - __attribute__((flatten)) for public facing functions --- fpu/softfloat.c | 892 +++++++++++++++++++++++++-------------------= ---- include/fpu/softfloat.h | 4 + 2 files changed, 469 insertions(+), 427 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 568d555595..2190e7de56 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -83,6 +83,7 @@ this code that are retained. * target-dependent and needs the TARGET_* macros. */ #include "qemu/osdep.h" +#include "qemu/bitops.h" #include "fpu/softfloat.h" =20 /* We only need stdlib for abort() */ @@ -270,6 +271,470 @@ static const FloatFmt float64_params =3D { FLOAT_PARAMS(11, 52) }; =20 +/* Unpack a float to parts, but do not canonicalize. */ +static inline FloatParts unpack_raw(FloatFmt fmt, uint64_t raw) +{ + const int sign_pos =3D fmt.frac_size + fmt.exp_size; + + return (FloatParts) { + .cls =3D float_class_unclassified, + .sign =3D extract64(raw, sign_pos, 1), + .exp =3D extract64(raw, fmt.frac_size, fmt.exp_size), + .frac =3D extract64(raw, 0, fmt.frac_size), + }; +} + +static inline FloatParts float16_unpack_raw(float16 f) +{ + return unpack_raw(float16_params, f); +} + +static inline FloatParts float32_unpack_raw(float32 f) +{ + return unpack_raw(float32_params, f); +} + +static inline FloatParts float64_unpack_raw(float64 f) +{ + return unpack_raw(float64_params, f); +} + +/* Pack a float from parts, but do not canonicalize. */ +static inline uint64_t pack_raw(FloatFmt fmt, FloatParts p) +{ + const int sign_pos =3D fmt.frac_size + fmt.exp_size; + uint64_t ret =3D deposit64(p.frac, fmt.frac_size, fmt.exp_size, p.exp); + return deposit64(ret, sign_pos, 1, p.sign); +} + +static inline float16 float16_pack_raw(FloatParts p) +{ + return make_float16(pack_raw(float16_params, p)); +} + +static inline float32 float32_pack_raw(FloatParts p) +{ + return make_float32(pack_raw(float32_params, p)); +} + +static inline float64 float64_pack_raw(FloatParts p) +{ + return make_float64(pack_raw(float64_params, p)); +} + +/* Canonicalize EXP and FRAC, setting CLS. */ +static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, + float_status *status) +{ + if (part.exp =3D=3D parm->exp_max) { + if (part.frac =3D=3D 0) { + part.cls =3D float_class_inf; + } else { +#ifdef NO_SIGNALING_NANS + part.cls =3D float_class_qnan; +#else + int64_t msb =3D part.frac << (parm->frac_shift + 2); + if ((msb < 0) =3D=3D status->snan_bit_is_one) { + part.cls =3D float_class_snan; + } else { + part.cls =3D float_class_qnan; + } +#endif + } + } else if (part.exp =3D=3D 0) { + if (likely(part.frac =3D=3D 0)) { + part.cls =3D float_class_zero; + } else if (status->flush_inputs_to_zero) { + float_raise(float_flag_input_denormal, status); + part.cls =3D float_class_zero; + part.frac =3D 0; + } else { + int shift =3D clz64(part.frac) - 1; + part.cls =3D float_class_normal; + part.exp =3D parm->frac_shift - parm->exp_bias - shift + 1; + part.frac <<=3D shift; + } + } else { + part.cls =3D float_class_normal; + part.exp -=3D parm->exp_bias; + part.frac =3D DECOMPOSED_IMPLICIT_BIT + (part.frac << parm->frac_s= hift); + } + return part; +} + +/* Round and uncanonicalize a floating-point number by parts. There + * are FRAC_SHIFT bits that may require rounding at the bottom of the + * fraction; these bits will be removed. The exponent will be biased + * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0]. + */ + +static FloatParts round_canonical(FloatParts p, float_status *s, + const FloatFmt *parm) +{ + const uint64_t frac_lsbm1 =3D parm->frac_lsbm1; + const uint64_t round_mask =3D parm->round_mask; + const uint64_t roundeven_mask =3D parm->roundeven_mask; + const int exp_max =3D parm->exp_max; + const int frac_shift =3D parm->frac_shift; + uint64_t frac, inc; + int exp, flags =3D 0; + bool overflow_norm; + + frac =3D p.frac; + exp =3D p.exp; + + switch (p.cls) { + case float_class_normal: + switch (s->float_rounding_mode) { + case float_round_nearest_even: + overflow_norm =3D false; + inc =3D ((frac & roundeven_mask) !=3D frac_lsbm1 ? frac_lsbm1 = : 0); + break; + case float_round_ties_away: + overflow_norm =3D false; + inc =3D frac_lsbm1; + break; + case float_round_to_zero: + overflow_norm =3D true; + inc =3D 0; + break; + case float_round_up: + inc =3D p.sign ? 0 : round_mask; + overflow_norm =3D p.sign; + break; + case float_round_down: + inc =3D p.sign ? round_mask : 0; + overflow_norm =3D !p.sign; + break; + default: + g_assert_not_reached(); + } + + exp +=3D parm->exp_bias; + if (likely(exp > 0)) { + if (frac & round_mask) { + flags |=3D float_flag_inexact; + frac +=3D inc; + if (frac & DECOMPOSED_OVERFLOW_BIT) { + frac >>=3D 1; + exp++; + } + } + frac >>=3D frac_shift; + + if (unlikely(exp >=3D exp_max)) { + flags |=3D float_flag_overflow | float_flag_inexact; + if (overflow_norm) { + exp =3D exp_max - 1; + frac =3D -1; + } else { + p.cls =3D float_class_inf; + goto do_inf; + } + } + } else if (s->flush_to_zero) { + flags |=3D float_flag_output_denormal; + p.cls =3D float_class_zero; + goto do_zero; + } else { + bool is_tiny =3D (s->float_detect_tininess + =3D=3D float_tininess_before_rounding) + || (exp < 0) + || !((frac + inc) & DECOMPOSED_OVERFLOW_BIT); + + shift64RightJamming(frac, 1 - exp, &frac); + if (frac & round_mask) { + /* Need to recompute round-to-even. */ + if (s->float_rounding_mode =3D=3D float_round_nearest_even= ) { + inc =3D ((frac & roundeven_mask) !=3D frac_lsbm1 + ? frac_lsbm1 : 0); + } + flags |=3D float_flag_inexact; + frac +=3D inc; + } + + exp =3D (frac & DECOMPOSED_IMPLICIT_BIT ? 1 : 0); + frac >>=3D frac_shift; + + if (is_tiny && (flags & float_flag_inexact)) { + flags |=3D float_flag_underflow; + } + if (exp =3D=3D 0 && frac =3D=3D 0) { + p.cls =3D float_class_zero; + } + } + break; + + case float_class_zero: + do_zero: + exp =3D 0; + frac =3D 0; + break; + + case float_class_inf: + do_inf: + exp =3D exp_max; + frac =3D 0; + break; + + case float_class_qnan: + case float_class_snan: + exp =3D exp_max; + break; + + default: + g_assert_not_reached(); + } + + float_raise(flags, s); + p.exp =3D exp; + p.frac =3D frac; + return p; +} + +static FloatParts float16_unpack_canonical(float16 f, float_status *s) +{ + return canonicalize(float16_unpack_raw(f), &float16_params, s); +} + +static float16 float16_round_pack_canonical(FloatParts p, float_status *s) +{ + switch (p.cls) { + case float_class_dnan: + return float16_default_nan(s); + case float_class_msnan: + return float16_maybe_silence_nan(float16_pack_raw(p), s); + default: + p =3D round_canonical(p, s, &float16_params); + return float16_pack_raw(p); + } +} + +static FloatParts float32_unpack_canonical(float32 f, float_status *s) +{ + return canonicalize(float32_unpack_raw(f), &float32_params, s); +} + +static float32 float32_round_pack_canonical(FloatParts p, float_status *s) +{ + switch (p.cls) { + case float_class_dnan: + return float32_default_nan(s); + case float_class_msnan: + return float32_maybe_silence_nan(float32_pack_raw(p), s); + default: + p =3D round_canonical(p, s, &float32_params); + return float32_pack_raw(p); + } +} + +static FloatParts float64_unpack_canonical(float64 f, float_status *s) +{ + return canonicalize(float64_unpack_raw(f), &float64_params, s); +} + +static float64 float64_round_pack_canonical(FloatParts p, float_status *s) +{ + switch (p.cls) { + case float_class_dnan: + return float64_default_nan(s); + case float_class_msnan: + return float64_maybe_silence_nan(float64_pack_raw(p), s); + default: + p =3D round_canonical(p, s, &float64_params); + return float64_pack_raw(p); + } +} + +/* Simple helpers for checking if what NaN we have */ +static bool is_nan(FloatClass c) +{ + return unlikely(c >=3D float_class_qnan); +} +static bool is_snan(FloatClass c) +{ + return c =3D=3D float_class_snan; +} +static bool is_qnan(FloatClass c) +{ + return c =3D=3D float_class_qnan; +} + +static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) +{ + if (is_snan(a.cls) || is_snan(b.cls)) { + s->float_exception_flags |=3D float_flag_invalid; + } + + if (s->default_nan_mode) { + a.cls =3D float_class_dnan; + } else { + if (pickNaN(is_qnan(a.cls), is_snan(a.cls), + is_qnan(b.cls), is_snan(b.cls), + a.frac > b.frac || + (a.frac =3D=3D b.frac && a.sign < b.sign))) { + a =3D b; + } + a.cls =3D float_class_msnan; + } + return a; +} + +/* + * Returns the result of adding or subtracting the values of the + * floating-point values `a' and `b'. The operation is performed + * according to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic. + */ + +static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract, + float_status *s) +{ + bool a_sign =3D a.sign; + bool b_sign =3D b.sign ^ subtract; + + if (a_sign !=3D b_sign) { + /* Subtraction */ + + if (a.cls =3D=3D float_class_normal && b.cls =3D=3D float_class_no= rmal) { + if (a.exp > b.exp || (a.exp =3D=3D b.exp && a.frac >=3D b.frac= )) { + shift64RightJamming(b.frac, a.exp - b.exp, &b.frac); + a.frac =3D a.frac - b.frac; + } else { + shift64RightJamming(a.frac, b.exp - a.exp, &a.frac); + a.frac =3D b.frac - a.frac; + a.exp =3D b.exp; + a_sign ^=3D 1; + } + + if (a.frac =3D=3D 0) { + a.cls =3D float_class_zero; + a.sign =3D s->float_rounding_mode =3D=3D float_round_down; + } else { + int shift =3D clz64(a.frac) - 1; + a.frac =3D a.frac << shift; + a.exp =3D a.exp - shift; + a.sign =3D a_sign; + } + return a; + } + if (is_nan(a.cls) || is_nan(b.cls)) { + return pick_nan(a, b, s); + } + if (a.cls =3D=3D float_class_inf) { + if (b.cls =3D=3D float_class_inf) { + float_raise(float_flag_invalid, s); + a.cls =3D float_class_dnan; + } + return a; + } + if (a.cls =3D=3D float_class_zero && b.cls =3D=3D float_class_zero= ) { + a.sign =3D s->float_rounding_mode =3D=3D float_round_down; + return a; + } + if (a.cls =3D=3D float_class_zero || b.cls =3D=3D float_class_inf)= { + b.sign =3D a_sign ^ 1; + return b; + } + if (b.cls =3D=3D float_class_zero) { + return a; + } + } else { + /* Addition */ + if (a.cls =3D=3D float_class_normal && b.cls =3D=3D float_class_no= rmal) { + if (a.exp > b.exp) { + shift64RightJamming(b.frac, a.exp - b.exp, &b.frac); + } else if (a.exp < b.exp) { + shift64RightJamming(a.frac, b.exp - a.exp, &a.frac); + a.exp =3D b.exp; + } + a.frac +=3D b.frac; + if (a.frac & DECOMPOSED_OVERFLOW_BIT) { + a.frac >>=3D 1; + a.exp +=3D 1; + } + return a; + } + if (is_nan(a.cls) || is_nan(b.cls)) { + return pick_nan(a, b, s); + } + if (a.cls =3D=3D float_class_inf || b.cls =3D=3D float_class_zero)= { + return a; + } + if (b.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero)= { + b.sign =3D b_sign; + return b; + } + } + g_assert_not_reached(); +} + +/* + * Returns the result of adding or subtracting the floating-point + * values `a' and `b'. The operation is performed according to the + * IEC/IEEE Standard for Binary Floating-Point Arithmetic. + */ + +float16 __attribute__((flatten)) float16_add(float16 a, float16 b, + float_status *status) +{ + FloatParts pa =3D float16_unpack_canonical(a, status); + FloatParts pb =3D float16_unpack_canonical(b, status); + FloatParts pr =3D addsub_floats(pa, pb, false, status); + + return float16_round_pack_canonical(pr, status); +} + +float32 __attribute__((flatten)) float32_add(float32 a, float32 b, + float_status *status) +{ + FloatParts pa =3D float32_unpack_canonical(a, status); + FloatParts pb =3D float32_unpack_canonical(b, status); + FloatParts pr =3D addsub_floats(pa, pb, false, status); + + return float32_round_pack_canonical(pr, status); +} + +float64 __attribute__((flatten)) float64_add(float64 a, float64 b, + float_status *status) +{ + FloatParts pa =3D float64_unpack_canonical(a, status); + FloatParts pb =3D float64_unpack_canonical(b, status); + FloatParts pr =3D addsub_floats(pa, pb, false, status); + + return float64_round_pack_canonical(pr, status); +} + +float16 __attribute__((flatten)) float16_sub(float16 a, float16 b, + float_status *status) +{ + FloatParts pa =3D float16_unpack_canonical(a, status); + FloatParts pb =3D float16_unpack_canonical(b, status); + FloatParts pr =3D addsub_floats(pa, pb, true, status); + + return float16_round_pack_canonical(pr, status); +} + +float32 __attribute__((flatten)) float32_sub(float32 a, float32 b, + float_status *status) +{ + FloatParts pa =3D float32_unpack_canonical(a, status); + FloatParts pb =3D float32_unpack_canonical(b, status); + FloatParts pr =3D addsub_floats(pa, pb, true, status); + + return float32_round_pack_canonical(pr, status); +} + +float64 __attribute__((flatten)) float64_sub(float64 a, float64 b, + float_status *status) +{ + FloatParts pa =3D float64_unpack_canonical(a, status); + FloatParts pb =3D float64_unpack_canonical(b, status); + FloatParts pr =3D addsub_floats(pa, pb, true, status); + + return float64_round_pack_canonical(pr, status); +} + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the @@ -2081,220 +2546,6 @@ float32 float32_round_to_int(float32 a, float_statu= s *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of adding the absolute values of the single-precision -| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated -| before being returned. `zSign' is ignored if the result is a NaN. -| The addition is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -static float32 addFloat32Sigs(float32 a, float32 b, flag zSign, - float_status *status) -{ - int aExp, bExp, zExp; - uint32_t aSig, bSig, zSig; - int expDiff; - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - bSig =3D extractFloat32Frac( b ); - bExp =3D extractFloat32Exp( b ); - expDiff =3D aExp - bExp; - aSig <<=3D 6; - bSig <<=3D 6; - if ( 0 < expDiff ) { - if ( aExp =3D=3D 0xFF ) { - if (aSig) { - return propagateFloat32NaN(a, b, status); - } - return a; - } - if ( bExp =3D=3D 0 ) { - --expDiff; - } - else { - bSig |=3D 0x20000000; - } - shift32RightJamming( bSig, expDiff, &bSig ); - zExp =3D aExp; - } - else if ( expDiff < 0 ) { - if ( bExp =3D=3D 0xFF ) { - if (bSig) { - return propagateFloat32NaN(a, b, status); - } - return packFloat32( zSign, 0xFF, 0 ); - } - if ( aExp =3D=3D 0 ) { - ++expDiff; - } - else { - aSig |=3D 0x20000000; - } - shift32RightJamming( aSig, - expDiff, &aSig ); - zExp =3D bExp; - } - else { - if ( aExp =3D=3D 0xFF ) { - if (aSig | bSig) { - return propagateFloat32NaN(a, b, status); - } - return a; - } - if ( aExp =3D=3D 0 ) { - if (status->flush_to_zero) { - if (aSig | bSig) { - float_raise(float_flag_output_denormal, status); - } - return packFloat32(zSign, 0, 0); - } - return packFloat32( zSign, 0, ( aSig + bSig )>>6 ); - } - zSig =3D 0x40000000 + aSig + bSig; - zExp =3D aExp; - goto roundAndPack; - } - aSig |=3D 0x20000000; - zSig =3D ( aSig + bSig )<<1; - --zExp; - if ( (int32_t) zSig < 0 ) { - zSig =3D aSig + bSig; - ++zExp; - } - roundAndPack: - return roundAndPackFloat32(zSign, zExp, zSig, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of subtracting the absolute values of the single- -| precision floating-point values `a' and `b'. If `zSign' is 1, the -| difference is negated before being returned. `zSign' is ignored if the -| result is a NaN. The subtraction is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -static float32 subFloat32Sigs(float32 a, float32 b, flag zSign, - float_status *status) -{ - int aExp, bExp, zExp; - uint32_t aSig, bSig, zSig; - int expDiff; - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - bSig =3D extractFloat32Frac( b ); - bExp =3D extractFloat32Exp( b ); - expDiff =3D aExp - bExp; - aSig <<=3D 7; - bSig <<=3D 7; - if ( 0 < expDiff ) goto aExpBigger; - if ( expDiff < 0 ) goto bExpBigger; - if ( aExp =3D=3D 0xFF ) { - if (aSig | bSig) { - return propagateFloat32NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - if ( aExp =3D=3D 0 ) { - aExp =3D 1; - bExp =3D 1; - } - if ( bSig < aSig ) goto aBigger; - if ( aSig < bSig ) goto bBigger; - return packFloat32(status->float_rounding_mode =3D=3D float_round_down= , 0, 0); - bExpBigger: - if ( bExp =3D=3D 0xFF ) { - if (bSig) { - return propagateFloat32NaN(a, b, status); - } - return packFloat32( zSign ^ 1, 0xFF, 0 ); - } - if ( aExp =3D=3D 0 ) { - ++expDiff; - } - else { - aSig |=3D 0x40000000; - } - shift32RightJamming( aSig, - expDiff, &aSig ); - bSig |=3D 0x40000000; - bBigger: - zSig =3D bSig - aSig; - zExp =3D bExp; - zSign ^=3D 1; - goto normalizeRoundAndPack; - aExpBigger: - if ( aExp =3D=3D 0xFF ) { - if (aSig) { - return propagateFloat32NaN(a, b, status); - } - return a; - } - if ( bExp =3D=3D 0 ) { - --expDiff; - } - else { - bSig |=3D 0x40000000; - } - shift32RightJamming( bSig, expDiff, &bSig ); - aSig |=3D 0x40000000; - aBigger: - zSig =3D aSig - bSig; - zExp =3D aExp; - normalizeRoundAndPack: - --zExp; - return normalizeRoundAndPackFloat32(zSign, zExp, zSig, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of adding the single-precision floating-point values = `a' -| and `b'. The operation is performed according to the IEC/IEEE Standard = for -| Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_add(float32 a, float32 b, float_status *status) -{ - flag aSign, bSign; - a =3D float32_squash_input_denormal(a, status); - b =3D float32_squash_input_denormal(b, status); - - aSign =3D extractFloat32Sign( a ); - bSign =3D extractFloat32Sign( b ); - if ( aSign =3D=3D bSign ) { - return addFloat32Sigs(a, b, aSign, status); - } - else { - return subFloat32Sigs(a, b, aSign, status); - } - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of subtracting the single-precision floating-point va= lues -| `a' and `b'. The operation is performed according to the IEC/IEEE Stand= ard -| for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_sub(float32 a, float32 b, float_status *status) -{ - flag aSign, bSign; - a =3D float32_squash_input_denormal(a, status); - b =3D float32_squash_input_denormal(b, status); - - aSign =3D extractFloat32Sign( a ); - bSign =3D extractFloat32Sign( b ); - if ( aSign =3D=3D bSign ) { - return subFloat32Sigs(a, b, aSign, status); - } - else { - return addFloat32Sigs(a, b, aSign, status); - } - -} - /*------------------------------------------------------------------------= ---- | Returns the result of multiplying the single-precision floating-point va= lues | `a' and `b'. The operation is performed according to the IEC/IEEE Stand= ard @@ -3891,219 +4142,6 @@ float64 float64_trunc_to_int(float64 a, float_statu= s *status) return res; } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of adding the absolute values of the double-precision -| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated -| before being returned. `zSign' is ignored if the result is a NaN. -| The addition is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -static float64 addFloat64Sigs(float64 a, float64 b, flag zSign, - float_status *status) -{ - int aExp, bExp, zExp; - uint64_t aSig, bSig, zSig; - int expDiff; - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - bSig =3D extractFloat64Frac( b ); - bExp =3D extractFloat64Exp( b ); - expDiff =3D aExp - bExp; - aSig <<=3D 9; - bSig <<=3D 9; - if ( 0 < expDiff ) { - if ( aExp =3D=3D 0x7FF ) { - if (aSig) { - return propagateFloat64NaN(a, b, status); - } - return a; - } - if ( bExp =3D=3D 0 ) { - --expDiff; - } - else { - bSig |=3D LIT64( 0x2000000000000000 ); - } - shift64RightJamming( bSig, expDiff, &bSig ); - zExp =3D aExp; - } - else if ( expDiff < 0 ) { - if ( bExp =3D=3D 0x7FF ) { - if (bSig) { - return propagateFloat64NaN(a, b, status); - } - return packFloat64( zSign, 0x7FF, 0 ); - } - if ( aExp =3D=3D 0 ) { - ++expDiff; - } - else { - aSig |=3D LIT64( 0x2000000000000000 ); - } - shift64RightJamming( aSig, - expDiff, &aSig ); - zExp =3D bExp; - } - else { - if ( aExp =3D=3D 0x7FF ) { - if (aSig | bSig) { - return propagateFloat64NaN(a, b, status); - } - return a; - } - if ( aExp =3D=3D 0 ) { - if (status->flush_to_zero) { - if (aSig | bSig) { - float_raise(float_flag_output_denormal, status); - } - return packFloat64(zSign, 0, 0); - } - return packFloat64( zSign, 0, ( aSig + bSig )>>9 ); - } - zSig =3D LIT64( 0x4000000000000000 ) + aSig + bSig; - zExp =3D aExp; - goto roundAndPack; - } - aSig |=3D LIT64( 0x2000000000000000 ); - zSig =3D ( aSig + bSig )<<1; - --zExp; - if ( (int64_t) zSig < 0 ) { - zSig =3D aSig + bSig; - ++zExp; - } - roundAndPack: - return roundAndPackFloat64(zSign, zExp, zSig, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of subtracting the absolute values of the double- -| precision floating-point values `a' and `b'. If `zSign' is 1, the -| difference is negated before being returned. `zSign' is ignored if the -| result is a NaN. The subtraction is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -static float64 subFloat64Sigs(float64 a, float64 b, flag zSign, - float_status *status) -{ - int aExp, bExp, zExp; - uint64_t aSig, bSig, zSig; - int expDiff; - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - bSig =3D extractFloat64Frac( b ); - bExp =3D extractFloat64Exp( b ); - expDiff =3D aExp - bExp; - aSig <<=3D 10; - bSig <<=3D 10; - if ( 0 < expDiff ) goto aExpBigger; - if ( expDiff < 0 ) goto bExpBigger; - if ( aExp =3D=3D 0x7FF ) { - if (aSig | bSig) { - return propagateFloat64NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - if ( aExp =3D=3D 0 ) { - aExp =3D 1; - bExp =3D 1; - } - if ( bSig < aSig ) goto aBigger; - if ( aSig < bSig ) goto bBigger; - return packFloat64(status->float_rounding_mode =3D=3D float_round_down= , 0, 0); - bExpBigger: - if ( bExp =3D=3D 0x7FF ) { - if (bSig) { - return propagateFloat64NaN(a, b, status); - } - return packFloat64( zSign ^ 1, 0x7FF, 0 ); - } - if ( aExp =3D=3D 0 ) { - ++expDiff; - } - else { - aSig |=3D LIT64( 0x4000000000000000 ); - } - shift64RightJamming( aSig, - expDiff, &aSig ); - bSig |=3D LIT64( 0x4000000000000000 ); - bBigger: - zSig =3D bSig - aSig; - zExp =3D bExp; - zSign ^=3D 1; - goto normalizeRoundAndPack; - aExpBigger: - if ( aExp =3D=3D 0x7FF ) { - if (aSig) { - return propagateFloat64NaN(a, b, status); - } - return a; - } - if ( bExp =3D=3D 0 ) { - --expDiff; - } - else { - bSig |=3D LIT64( 0x4000000000000000 ); - } - shift64RightJamming( bSig, expDiff, &bSig ); - aSig |=3D LIT64( 0x4000000000000000 ); - aBigger: - zSig =3D aSig - bSig; - zExp =3D aExp; - normalizeRoundAndPack: - --zExp; - return normalizeRoundAndPackFloat64(zSign, zExp, zSig, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of adding the double-precision floating-point values = `a' -| and `b'. The operation is performed according to the IEC/IEEE Standard = for -| Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_add(float64 a, float64 b, float_status *status) -{ - flag aSign, bSign; - a =3D float64_squash_input_denormal(a, status); - b =3D float64_squash_input_denormal(b, status); - - aSign =3D extractFloat64Sign( a ); - bSign =3D extractFloat64Sign( b ); - if ( aSign =3D=3D bSign ) { - return addFloat64Sigs(a, b, aSign, status); - } - else { - return subFloat64Sigs(a, b, aSign, status); - } - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of subtracting the double-precision floating-point va= lues -| `a' and `b'. The operation is performed according to the IEC/IEEE Stand= ard -| for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_sub(float64 a, float64 b, float_status *status) -{ - flag aSign, bSign; - a =3D float64_squash_input_denormal(a, status); - b =3D float64_squash_input_denormal(b, status); - - aSign =3D extractFloat64Sign( a ); - bSign =3D extractFloat64Sign( b ); - if ( aSign =3D=3D bSign ) { - return subFloat64Sigs(a, b, aSign, status); - } - else { - return addFloat64Sigs(a, b, aSign, status); - } - -} =20 /*------------------------------------------------------------------------= ---- | Returns the result of multiplying the double-precision floating-point va= lues diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 23824a3000..693ece0974 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -236,6 +236,10 @@ float64 float16_to_float64(float16 a, flag ieee, float= _status *status); /*------------------------------------------------------------------------= ---- | Software half-precision operations. *-------------------------------------------------------------------------= ---*/ + +float16 float16_add(float16, float16, float_status *status); +float16 float16_sub(float16, float16, float_status *status); + int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); float16 float16_maybe_silence_nan(float16, float_status *status); --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v4 13/22] fpu/softfloat: re-factor mul X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We can now add float16_mul and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 versions. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3 - mul compile fixes for new names - remove duplicate s-o-b - more explicit inf * zero check v4 - use is_nan - pick_nan_parts/pick_nan --- fpu/softfloat.c | 209 +++++++++++++++++++-------------------------= ---- include/fpu/softfloat.h | 1 + 2 files changed, 82 insertions(+), 128 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 2190e7de56..6d29e1a103 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -735,6 +735,87 @@ float64 __attribute__((flatten)) float64_sub(float64 a= , float64 b, return float64_round_pack_canonical(pr, status); } =20 +/* + * Returns the result of multiplying the floating-point values `a' and + * `b'. The operation is performed according to the IEC/IEEE Standard + * for Binary Floating-Point Arithmetic. + */ + +static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s) +{ + bool sign =3D a.sign ^ b.sign; + + if (a.cls =3D=3D float_class_normal && b.cls =3D=3D float_class_normal= ) { + uint64_t hi, lo; + int exp =3D a.exp + b.exp; + + mul64To128(a.frac, b.frac, &hi, &lo); + shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi, &lo); + if (lo & DECOMPOSED_OVERFLOW_BIT) { + shift64RightJamming(lo, 1, &lo); + exp +=3D 1; + } + + /* Re-use a */ + a.exp =3D exp; + a.sign =3D sign; + a.frac =3D lo; + return a; + } + /* handle all the NaN cases */ + if (is_nan(a.cls) || is_nan(b.cls)) { + return pick_nan(a, b, s); + } + /* Inf * Zero =3D=3D NaN */ + if ((a.cls =3D=3D float_class_inf && b.cls =3D=3D float_class_zero) || + (a.cls =3D=3D float_class_zero && b.cls =3D=3D float_class_inf)) { + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_dnan; + a.sign =3D sign; + return a; + } + /* Multiply by 0 or Inf */ + if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { + a.sign =3D sign; + return a; + } + if (b.cls =3D=3D float_class_inf || b.cls =3D=3D float_class_zero) { + b.sign =3D sign; + return b; + } + g_assert_not_reached(); +} + +float16 __attribute__((flatten)) float16_mul(float16 a, float16 b, + float_status *status) +{ + FloatParts pa =3D float16_unpack_canonical(a, status); + FloatParts pb =3D float16_unpack_canonical(b, status); + FloatParts pr =3D mul_floats(pa, pb, status); + + return float16_round_pack_canonical(pr, status); +} + +float32 __attribute__((flatten)) float32_mul(float32 a, float32 b, + float_status *status) +{ + FloatParts pa =3D float32_unpack_canonical(a, status); + FloatParts pb =3D float32_unpack_canonical(b, status); + FloatParts pr =3D mul_floats(pa, pb, status); + + return float32_round_pack_canonical(pr, status); +} + +float64 __attribute__((flatten)) float64_mul(float64 a, float64 b, + float_status *status) +{ + FloatParts pa =3D float64_unpack_canonical(a, status); + FloatParts pb =3D float64_unpack_canonical(b, status); + FloatParts pr =3D mul_floats(pa, pb, status); + + return float64_round_pack_canonical(pr, status); +} + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the @@ -2546,70 +2627,6 @@ float32 float32_round_to_int(float32 a, float_status= *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of multiplying the single-precision floating-point va= lues -| `a' and `b'. The operation is performed according to the IEC/IEEE Stand= ard -| for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_mul(float32 a, float32 b, float_status *status) -{ - flag aSign, bSign, zSign; - int aExp, bExp, zExp; - uint32_t aSig, bSig; - uint64_t zSig64; - uint32_t zSig; - - a =3D float32_squash_input_denormal(a, status); - b =3D float32_squash_input_denormal(b, status); - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - bSig =3D extractFloat32Frac( b ); - bExp =3D extractFloat32Exp( b ); - bSign =3D extractFloat32Sign( b ); - zSign =3D aSign ^ bSign; - if ( aExp =3D=3D 0xFF ) { - if ( aSig || ( ( bExp =3D=3D 0xFF ) && bSig ) ) { - return propagateFloat32NaN(a, b, status); - } - if ( ( bExp | bSig ) =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - return packFloat32( zSign, 0xFF, 0 ); - } - if ( bExp =3D=3D 0xFF ) { - if (bSig) { - return propagateFloat32NaN(a, b, status); - } - if ( ( aExp | aSig ) =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - return packFloat32( zSign, 0xFF, 0 ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat32( zSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - if ( bExp =3D=3D 0 ) { - if ( bSig =3D=3D 0 ) return packFloat32( zSign, 0, 0 ); - normalizeFloat32Subnormal( bSig, &bExp, &bSig ); - } - zExp =3D aExp + bExp - 0x7F; - aSig =3D ( aSig | 0x00800000 )<<7; - bSig =3D ( bSig | 0x00800000 )<<8; - shift64RightJamming( ( (uint64_t) aSig ) * bSig, 32, &zSig64 ); - zSig =3D zSig64; - if ( 0 <=3D (int32_t) ( zSig<<1 ) ) { - zSig <<=3D 1; - --zExp; - } - return roundAndPackFloat32(zSign, zExp, zSig, status); - -} =20 /*------------------------------------------------------------------------= ---- | Returns the result of dividing the single-precision floating-point value= `a' @@ -4142,70 +4159,6 @@ float64 float64_trunc_to_int(float64 a, float_status= *status) return res; } =20 - -/*------------------------------------------------------------------------= ---- -| Returns the result of multiplying the double-precision floating-point va= lues -| `a' and `b'. The operation is performed according to the IEC/IEEE Stand= ard -| for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_mul(float64 a, float64 b, float_status *status) -{ - flag aSign, bSign, zSign; - int aExp, bExp, zExp; - uint64_t aSig, bSig, zSig0, zSig1; - - a =3D float64_squash_input_denormal(a, status); - b =3D float64_squash_input_denormal(b, status); - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - bSig =3D extractFloat64Frac( b ); - bExp =3D extractFloat64Exp( b ); - bSign =3D extractFloat64Sign( b ); - zSign =3D aSign ^ bSign; - if ( aExp =3D=3D 0x7FF ) { - if ( aSig || ( ( bExp =3D=3D 0x7FF ) && bSig ) ) { - return propagateFloat64NaN(a, b, status); - } - if ( ( bExp | bSig ) =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - return packFloat64( zSign, 0x7FF, 0 ); - } - if ( bExp =3D=3D 0x7FF ) { - if (bSig) { - return propagateFloat64NaN(a, b, status); - } - if ( ( aExp | aSig ) =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - return packFloat64( zSign, 0x7FF, 0 ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat64( zSign, 0, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - if ( bExp =3D=3D 0 ) { - if ( bSig =3D=3D 0 ) return packFloat64( zSign, 0, 0 ); - normalizeFloat64Subnormal( bSig, &bExp, &bSig ); - } - zExp =3D aExp + bExp - 0x3FF; - aSig =3D ( aSig | LIT64( 0x0010000000000000 ) )<<10; - bSig =3D ( bSig | LIT64( 0x0010000000000000 ) )<<11; - mul64To128( aSig, bSig, &zSig0, &zSig1 ); - zSig0 |=3D ( zSig1 !=3D 0 ); - if ( 0 <=3D (int64_t) ( zSig0<<1 ) ) { - zSig0 <<=3D 1; - --zExp; - } - return roundAndPackFloat64(zSign, zExp, zSig0, status); - -} - /*------------------------------------------------------------------------= ---- | Returns the result of dividing the double-precision floating-point value= `a' | by the corresponding value `b'. The operation is performed according to diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 693ece0974..7fc63dd60f 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -239,6 +239,7 @@ float64 float16_to_float64(float16 a, flag ieee, float_= status *status); =20 float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); +float16 float16_mul(float16, float16, float_status *status); =20 int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517936593359140.04731266709928; Tue, 6 Feb 2018 09:03:13 -0800 (PST) Received: from localhost ([::1]:38119 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6eG-0005OF-Ah for importer@patchew.org; Tue, 06 Feb 2018 12:03:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33611) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6Q7-0000ex-Ds for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ej6Q5-00056Y-9N for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:35 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:55164) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ej6Q4-00054U-VF for qemu-devel@nongnu.org; Tue, 06 Feb 2018 11:48:33 -0500 Received: by mail-wm0-x242.google.com with SMTP id i186so4988468wmi.4 for ; Tue, 06 Feb 2018 08:48:32 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id m11sm22541416wrf.75.2018.02.06.08.48.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Feb 2018 08:48:23 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 57D4B3E0946; Tue, 6 Feb 2018 16:48:16 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8HsFvyiGvdyq9W8Io7SzbAjMdYcYQbYTsxX5ab8g1rQ=; b=NnzIp3xNWhyKPHRnhVmTYEHIOcsxRlys5TMAxGEYgH9boU5vJuPaweN90scQDuAUbT iStz5oVJ3dfOW7fbzcxxuc1qzC+ejCukNlnBcuQ9hk5zol2qmXw7MQqRElIvMYJPVwG0 aXay6hfpmRj19qBfeeool/83bAUrv7/M5jyOQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8HsFvyiGvdyq9W8Io7SzbAjMdYcYQbYTsxX5ab8g1rQ=; b=PQmP1Dx++qG4iqsUW/0SA6+31S4p9i6oJDCIjAv/FpdLxuv1wr6KEywE0fHTGn4Rwg XUIIwE3VxLKniYiXmfKl+d/Gkl8kZlYuDFnc3AmTTv93wx8rm6AXmxWK2q+C9zmHhxn1 PWZPRwYoORJyLyy45Y2bHHBkjk5wKtk2bavFbzPMJ1rsni3/CBML/HKpm/wxJriW1byO sdCVlAAIZm5W6xr20AoyVjJ0fv4w1BwOfZuTUt23sJ2ChUfIV3i4EL4BkJro1oQUs8I9 xA/pnl29y1Diaoj1BbeyFSLnzVqakpd/fD51Rho+8hFTTOvdKp01OZW3dWZkbxmv6Fgs YaEA== X-Gm-Message-State: APf1xPCapMDB5SG0Ezq0TKAA7nGYhLwY8w4X6MiEOPx+ITgT790dN1TJ Wb0LjGLmoc4lsotkzSBRgzm2ZA== X-Google-Smtp-Source: AH8x227LC9Exh1mMg5htP8FB9ET/oJ4779EOsQ6AzGWGj71hOTp/06+HjLz4qR2bBVmaSNtGHS9vGQ== X-Received: by 10.28.168.8 with SMTP id r8mr2558009wme.157.1517935711683; Tue, 06 Feb 2018 08:48:31 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org, peter.maydell@linaro.org, laurent@vivier.eu, bharata@linux.vnet.ibm.com, andrew@andrewdutcher.com Date: Tue, 6 Feb 2018 16:48:07 +0000 Message-Id: <20180206164815.10084-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180206164815.10084-1-alex.bennee@linaro.org> References: <20180206164815.10084-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v4 14/22] fpu/softfloat: re-factor div X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We can now add float16_div and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 versions. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3 - rename functions and structures v4 - use is_nan - better attribution for div128To64 - pick_nan_parts->pick_nan --- fpu/softfloat-macros.h | 48 ++++++++++ fpu/softfloat.c | 236 ++++++++++++++++++--------------------------= ---- include/fpu/softfloat.h | 1 + 3 files changed, 137 insertions(+), 148 deletions(-) diff --git a/fpu/softfloat-macros.h b/fpu/softfloat-macros.h index 9cc6158cb4..c45a23193e 100644 --- a/fpu/softfloat-macros.h +++ b/fpu/softfloat-macros.h @@ -625,6 +625,54 @@ static uint64_t estimateDiv128To64( uint64_t a0, uint6= 4_t a1, uint64_t b ) =20 } =20 +/* From the GNU Multi Precision Library - longlong.h __udiv_qrnnd + * (https://gmplib.org/repo/gmp/file/tip/longlong.h) + * + * Licensed under the GPLv2/LGPLv3 + */ +static uint64_t div128To64(uint64_t n0, uint64_t n1, uint64_t d) +{ + uint64_t d0, d1, q0, q1, r1, r0, m; + + d0 =3D (uint32_t)d; + d1 =3D d >> 32; + + r1 =3D n1 % d1; + q1 =3D n1 / d1; + m =3D q1 * d0; + r1 =3D (r1 << 32) | (n0 >> 32); + if (r1 < m) { + q1 -=3D 1; + r1 +=3D d; + if (r1 >=3D d) { + if (r1 < m) { + q1 -=3D 1; + r1 +=3D d; + } + } + } + r1 -=3D m; + + r0 =3D r1 % d1; + q0 =3D r1 / d1; + m =3D q0 * d0; + r0 =3D (r0 << 32) | (uint32_t)n0; + if (r0 < m) { + q0 -=3D 1; + r0 +=3D d; + if (r0 >=3D d) { + if (r0 < m) { + q0 -=3D 1; + r0 +=3D d; + } + } + } + r0 -=3D m; + + /* Return remainder in LSB */ + return (q1 << 32) | q0 | (r0 !=3D 0); +} + /*------------------------------------------------------------------------= ---- | Returns an approximation to the square root of the 32-bit significand gi= ven | by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 = of diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6d29e1a103..4a859b2721 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -816,6 +816,94 @@ float64 __attribute__((flatten)) float64_mul(float64 a= , float64 b, return float64_round_pack_canonical(pr, status); } =20 +/* + * Returns the result of dividing the floating-point value `a' by the + * corresponding value `b'. The operation is performed according to + * the IEC/IEEE Standard for Binary Floating-Point Arithmetic. + */ + +static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s) +{ + bool sign =3D a.sign ^ b.sign; + + if (a.cls =3D=3D float_class_normal && b.cls =3D=3D float_class_normal= ) { + uint64_t temp_lo, temp_hi; + int exp =3D a.exp - b.exp; + if (a.frac < b.frac) { + exp -=3D 1; + shortShift128Left(0, a.frac, DECOMPOSED_BINARY_POINT + 1, + &temp_hi, &temp_lo); + } else { + shortShift128Left(0, a.frac, DECOMPOSED_BINARY_POINT, + &temp_hi, &temp_lo); + } + /* LSB of quot is set if inexact which roundandpack will use + * to set flags. Yet again we re-use a for the result */ + a.frac =3D div128To64(temp_lo, temp_hi, b.frac); + a.sign =3D sign; + a.exp =3D exp; + return a; + } + /* handle all the NaN cases */ + if (is_nan(a.cls) || is_nan(b.cls)) { + return pick_nan(a, b, s); + } + /* 0/0 or Inf/Inf */ + if (a.cls =3D=3D b.cls + && + (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero)) { + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_dnan; + return a; + } + /* Div 0 =3D> Inf */ + if (b.cls =3D=3D float_class_zero) { + s->float_exception_flags |=3D float_flag_divbyzero; + a.cls =3D float_class_inf; + a.sign =3D sign; + return a; + } + /* Inf / x or 0 / x */ + if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { + a.sign =3D sign; + return a; + } + /* Div by Inf */ + if (b.cls =3D=3D float_class_inf) { + a.cls =3D float_class_zero; + a.sign =3D sign; + return a; + } + g_assert_not_reached(); +} + +float16 float16_div(float16 a, float16 b, float_status *status) +{ + FloatParts pa =3D float16_unpack_canonical(a, status); + FloatParts pb =3D float16_unpack_canonical(b, status); + FloatParts pr =3D div_floats(pa, pb, status); + + return float16_round_pack_canonical(pr, status); +} + +float32 float32_div(float32 a, float32 b, float_status *status) +{ + FloatParts pa =3D float32_unpack_canonical(a, status); + FloatParts pb =3D float32_unpack_canonical(b, status); + FloatParts pr =3D div_floats(pa, pb, status); + + return float32_round_pack_canonical(pr, status); +} + +float64 float64_div(float64 a, float64 b, float_status *status) +{ + FloatParts pa =3D float64_unpack_canonical(a, status); + FloatParts pb =3D float64_unpack_canonical(b, status); + FloatParts pr =3D div_floats(pa, pb, status); + + return float64_round_pack_canonical(pr, status); +} + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the @@ -2627,77 +2715,6 @@ float32 float32_round_to_int(float32 a, float_status= *status) =20 } =20 - -/*------------------------------------------------------------------------= ---- -| Returns the result of dividing the single-precision floating-point value= `a' -| by the corresponding value `b'. The operation is performed according to= the -| IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_div(float32 a, float32 b, float_status *status) -{ - flag aSign, bSign, zSign; - int aExp, bExp, zExp; - uint32_t aSig, bSig, zSig; - a =3D float32_squash_input_denormal(a, status); - b =3D float32_squash_input_denormal(b, status); - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - bSig =3D extractFloat32Frac( b ); - bExp =3D extractFloat32Exp( b ); - bSign =3D extractFloat32Sign( b ); - zSign =3D aSign ^ bSign; - if ( aExp =3D=3D 0xFF ) { - if (aSig) { - return propagateFloat32NaN(a, b, status); - } - if ( bExp =3D=3D 0xFF ) { - if (bSig) { - return propagateFloat32NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - return packFloat32( zSign, 0xFF, 0 ); - } - if ( bExp =3D=3D 0xFF ) { - if (bSig) { - return propagateFloat32NaN(a, b, status); - } - return packFloat32( zSign, 0, 0 ); - } - if ( bExp =3D=3D 0 ) { - if ( bSig =3D=3D 0 ) { - if ( ( aExp | aSig ) =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - float_raise(float_flag_divbyzero, status); - return packFloat32( zSign, 0xFF, 0 ); - } - normalizeFloat32Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat32( zSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - zExp =3D aExp - bExp + 0x7D; - aSig =3D ( aSig | 0x00800000 )<<7; - bSig =3D ( bSig | 0x00800000 )<<8; - if ( bSig <=3D ( aSig + aSig ) ) { - aSig >>=3D 1; - ++zExp; - } - zSig =3D ( ( (uint64_t) aSig )<<32 ) / bSig; - if ( ( zSig & 0x3F ) =3D=3D 0 ) { - zSig |=3D ( (uint64_t) bSig * zSig !=3D ( (uint64_t) aSig )<<32 ); - } - return roundAndPackFloat32(zSign, zExp, zSig, status); - -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the single-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -4159,83 +4176,6 @@ float64 float64_trunc_to_int(float64 a, float_status= *status) return res; } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of dividing the double-precision floating-point value= `a' -| by the corresponding value `b'. The operation is performed according to -| the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_div(float64 a, float64 b, float_status *status) -{ - flag aSign, bSign, zSign; - int aExp, bExp, zExp; - uint64_t aSig, bSig, zSig; - uint64_t rem0, rem1; - uint64_t term0, term1; - a =3D float64_squash_input_denormal(a, status); - b =3D float64_squash_input_denormal(b, status); - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - bSig =3D extractFloat64Frac( b ); - bExp =3D extractFloat64Exp( b ); - bSign =3D extractFloat64Sign( b ); - zSign =3D aSign ^ bSign; - if ( aExp =3D=3D 0x7FF ) { - if (aSig) { - return propagateFloat64NaN(a, b, status); - } - if ( bExp =3D=3D 0x7FF ) { - if (bSig) { - return propagateFloat64NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - return packFloat64( zSign, 0x7FF, 0 ); - } - if ( bExp =3D=3D 0x7FF ) { - if (bSig) { - return propagateFloat64NaN(a, b, status); - } - return packFloat64( zSign, 0, 0 ); - } - if ( bExp =3D=3D 0 ) { - if ( bSig =3D=3D 0 ) { - if ( ( aExp | aSig ) =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - float_raise(float_flag_divbyzero, status); - return packFloat64( zSign, 0x7FF, 0 ); - } - normalizeFloat64Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat64( zSign, 0, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - zExp =3D aExp - bExp + 0x3FD; - aSig =3D ( aSig | LIT64( 0x0010000000000000 ) )<<10; - bSig =3D ( bSig | LIT64( 0x0010000000000000 ) )<<11; - if ( bSig <=3D ( aSig + aSig ) ) { - aSig >>=3D 1; - ++zExp; - } - zSig =3D estimateDiv128To64( aSig, 0, bSig ); - if ( ( zSig & 0x1FF ) <=3D 2 ) { - mul64To128( bSig, zSig, &term0, &term1 ); - sub128( aSig, 0, term0, term1, &rem0, &rem1 ); - while ( (int64_t) rem0 < 0 ) { - --zSig; - add128( rem0, rem1, 0, bSig, &rem0, &rem1 ); - } - zSig |=3D ( rem1 !=3D 0 ); - } - return roundAndPackFloat64(zSign, zExp, zSig, status); - -} =20 /*------------------------------------------------------------------------= ---- | Returns the remainder of the double-precision floating-point value `a' diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 7fc63dd60f..85e4a74f1b 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -240,6 +240,7 @@ float64 float16_to_float64(float16 a, flag ieee, float_= status *status); float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); float16 float16_mul(float16, float16, float_status *status); +float16 float16_div(float16, float16, float_status *status); =20 int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c09::230 Subject: [Qemu-devel] [PATCH v4 15/22] fpu/softfloat: re-factor muladd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We can now add float16_muladd and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 muladd functions. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- v3 - rename functions and structures v4 - use is_nan - attribute(flatten) --- fpu/softfloat-specialize.h | 104 ------- fpu/softfloat.c | 742 +++++++++++++++++------------------------= ---- include/fpu/softfloat.h | 1 + 3 files changed, 272 insertions(+), 575 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 4be0fb21ba..e81ca001e1 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -729,58 +729,6 @@ static float32 propagateFloat32NaN(float32 a, float32 = b, float_status *status) } } =20 -/*------------------------------------------------------------------------= ---- -| Takes three single-precision floating-point values `a', `b' and `c', one= of -| which is a NaN, and returns the appropriate NaN result. If any of `a', -| `b' or `c' is a signaling NaN, the invalid exception is raised. -| The input infzero indicates whether a*b was 0*inf or inf*0 (in which case -| obviously c is a NaN, and whether to propagate c or some other NaN is -| implementation defined). -*-------------------------------------------------------------------------= ---*/ - -static float32 propagateFloat32MulAddNaN(float32 a, float32 b, - float32 c, flag infzero, - float_status *status) -{ - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - cIsQuietNaN, cIsSignalingNaN; - int which; - - aIsQuietNaN =3D float32_is_quiet_nan(a, status); - aIsSignalingNaN =3D float32_is_signaling_nan(a, status); - bIsQuietNaN =3D float32_is_quiet_nan(b, status); - bIsSignalingNaN =3D float32_is_signaling_nan(b, status); - cIsQuietNaN =3D float32_is_quiet_nan(c, status); - cIsSignalingNaN =3D float32_is_signaling_nan(c, status); - - if (aIsSignalingNaN | bIsSignalingNaN | cIsSignalingNaN) { - float_raise(float_flag_invalid, status); - } - - which =3D pickNaNMulAdd(aIsQuietNaN, aIsSignalingNaN, - bIsQuietNaN, bIsSignalingNaN, - cIsQuietNaN, cIsSignalingNaN, infzero, status); - - if (status->default_nan_mode) { - /* Note that this check is after pickNaNMulAdd so that function - * has an opportunity to set the Invalid flag. - */ - return float32_default_nan(status); - } - - switch (which) { - case 0: - return float32_maybe_silence_nan(a, status); - case 1: - return float32_maybe_silence_nan(b, status); - case 2: - return float32_maybe_silence_nan(c, status); - case 3: - default: - return float32_default_nan(status); - } -} - #ifdef NO_SIGNALING_NANS int float64_is_quiet_nan(float64 a_, float_status *status) { @@ -936,58 +884,6 @@ static float64 propagateFloat64NaN(float64 a, float64 = b, float_status *status) } } =20 -/*------------------------------------------------------------------------= ---- -| Takes three double-precision floating-point values `a', `b' and `c', one= of -| which is a NaN, and returns the appropriate NaN result. If any of `a', -| `b' or `c' is a signaling NaN, the invalid exception is raised. -| The input infzero indicates whether a*b was 0*inf or inf*0 (in which case -| obviously c is a NaN, and whether to propagate c or some other NaN is -| implementation defined). -*-------------------------------------------------------------------------= ---*/ - -static float64 propagateFloat64MulAddNaN(float64 a, float64 b, - float64 c, flag infzero, - float_status *status) -{ - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - cIsQuietNaN, cIsSignalingNaN; - int which; - - aIsQuietNaN =3D float64_is_quiet_nan(a, status); - aIsSignalingNaN =3D float64_is_signaling_nan(a, status); - bIsQuietNaN =3D float64_is_quiet_nan(b, status); - bIsSignalingNaN =3D float64_is_signaling_nan(b, status); - cIsQuietNaN =3D float64_is_quiet_nan(c, status); - cIsSignalingNaN =3D float64_is_signaling_nan(c, status); - - if (aIsSignalingNaN | bIsSignalingNaN | cIsSignalingNaN) { - float_raise(float_flag_invalid, status); - } - - which =3D pickNaNMulAdd(aIsQuietNaN, aIsSignalingNaN, - bIsQuietNaN, bIsSignalingNaN, - cIsQuietNaN, cIsSignalingNaN, infzero, status); - - if (status->default_nan_mode) { - /* Note that this check is after pickNaNMulAdd so that function - * has an opportunity to set the Invalid flag. - */ - return float64_default_nan(status); - } - - switch (which) { - case 0: - return float64_maybe_silence_nan(a, status); - case 1: - return float64_maybe_silence_nan(b, status); - case 2: - return float64_maybe_silence_nan(c, status); - case 3: - default: - return float64_default_nan(status); - } -} - #ifdef NO_SIGNALING_NANS int floatx80_is_quiet_nan(floatx80 a_, float_status *status) { diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4a859b2721..ae4ba6de51 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -580,6 +580,40 @@ static FloatParts pick_nan(FloatParts a, FloatParts b,= float_status *s) return a; } =20 +static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, + bool inf_zero, float_status *s) +{ + if (is_snan(a.cls) || is_snan(b.cls) || is_snan(c.cls)) { + s->float_exception_flags |=3D float_flag_invalid; + } + + if (s->default_nan_mode) { + a.cls =3D float_class_dnan; + } else { + switch (pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), + is_qnan(b.cls), is_snan(b.cls), + is_qnan(c.cls), is_snan(c.cls), + inf_zero, s)) { + case 0: + break; + case 1: + a =3D b; + break; + case 2: + a =3D c; + break; + case 3: + a.cls =3D float_class_dnan; + return a; + default: + g_assert_not_reached(); + } + + a.cls =3D float_class_msnan; + } + return a; +} + /* * Returns the result of adding or subtracting the values of the * floating-point values `a' and `b'. The operation is performed @@ -816,6 +850,243 @@ float64 __attribute__((flatten)) float64_mul(float64 = a, float64 b, return float64_round_pack_canonical(pr, status); } =20 +/* + * Returns the result of multiplying the floating-point values `a' and + * `b' then adding 'c', with no intermediate rounding step after the + * multiplication. The operation is performed according to the + * IEC/IEEE Standard for Binary Floating-Point Arithmetic 754-2008. + * The flags argument allows the caller to select negation of the + * addend, the intermediate product, or the final result. (The + * difference between this and having the caller do a separate + * negation is that negating externally will flip the sign bit on + * NaNs.) + */ + +static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, + int flags, float_status *s) +{ + bool inf_zero =3D ((1 << a.cls) | (1 << b.cls)) =3D=3D + ((1 << float_class_inf) | (1 << float_class_zero)); + bool p_sign; + bool sign_flip =3D flags & float_muladd_negate_result; + FloatClass p_class; + uint64_t hi, lo; + int p_exp; + + /* It is implementation-defined whether the cases of (0,inf,qnan) + * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN + * they return if they do), so we have to hand this information + * off to the target-specific pick-a-NaN routine. + */ + if (is_nan(a.cls) || is_nan(b.cls) || is_nan(c.cls)) { + return pick_nan_muladd(a, b, c, inf_zero, s); + } + + if (inf_zero) { + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_dnan; + return a; + } + + if (flags & float_muladd_negate_c) { + c.sign ^=3D 1; + } + + p_sign =3D a.sign ^ b.sign; + + if (flags & float_muladd_negate_product) { + p_sign ^=3D 1; + } + + if (a.cls =3D=3D float_class_inf || b.cls =3D=3D float_class_inf) { + p_class =3D float_class_inf; + } else if (a.cls =3D=3D float_class_zero || b.cls =3D=3D float_class_z= ero) { + p_class =3D float_class_zero; + } else { + p_class =3D float_class_normal; + } + + if (c.cls =3D=3D float_class_inf) { + if (p_class =3D=3D float_class_inf && p_sign !=3D c.sign) { + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_dnan; + } else { + a.cls =3D float_class_inf; + a.sign =3D c.sign ^ sign_flip; + } + return a; + } + + if (p_class =3D=3D float_class_inf) { + a.cls =3D float_class_inf; + a.sign =3D p_sign ^ sign_flip; + return a; + } + + if (p_class =3D=3D float_class_zero) { + if (c.cls =3D=3D float_class_zero) { + if (p_sign !=3D c.sign) { + p_sign =3D s->float_rounding_mode =3D=3D float_round_down; + } + c.sign =3D p_sign; + } else if (flags & float_muladd_halve_result) { + c.exp -=3D 1; + } + c.sign ^=3D sign_flip; + return c; + } + + /* a & b should be normals now... */ + assert(a.cls =3D=3D float_class_normal && + b.cls =3D=3D float_class_normal); + + p_exp =3D a.exp + b.exp; + + /* Multiply of 2 62-bit numbers produces a (2*62) =3D=3D 124-bit + * result. + */ + mul64To128(a.frac, b.frac, &hi, &lo); + /* binary point now at bit 124 */ + + /* check for overflow */ + if (hi & (1ULL << (DECOMPOSED_BINARY_POINT * 2 + 1 - 64))) { + shift128RightJamming(hi, lo, 1, &hi, &lo); + p_exp +=3D 1; + } + + /* + add/sub */ + if (c.cls =3D=3D float_class_zero) { + /* move binary point back to 62 */ + shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi, &lo); + } else { + int exp_diff =3D p_exp - c.exp; + if (p_sign =3D=3D c.sign) { + /* Addition */ + if (exp_diff <=3D 0) { + shift128RightJamming(hi, lo, + DECOMPOSED_BINARY_POINT - exp_diff, + &hi, &lo); + lo +=3D c.frac; + p_exp =3D c.exp; + } else { + uint64_t c_hi, c_lo; + /* shift c to the same binary point as the product (124) */ + c_hi =3D c.frac >> 2; + c_lo =3D 0; + shift128RightJamming(c_hi, c_lo, + exp_diff, + &c_hi, &c_lo); + add128(hi, lo, c_hi, c_lo, &hi, &lo); + /* move binary point back to 62 */ + shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi,= &lo); + } + + if (lo & DECOMPOSED_OVERFLOW_BIT) { + shift64RightJamming(lo, 1, &lo); + p_exp +=3D 1; + } + + } else { + /* Subtraction */ + uint64_t c_hi, c_lo; + /* make C binary point match product at bit 124 */ + c_hi =3D c.frac >> 2; + c_lo =3D 0; + + if (exp_diff <=3D 0) { + shift128RightJamming(hi, lo, -exp_diff, &hi, &lo); + if (exp_diff =3D=3D 0 + && + (hi > c_hi || (hi =3D=3D c_hi && lo >=3D c_lo))) { + sub128(hi, lo, c_hi, c_lo, &hi, &lo); + } else { + sub128(c_hi, c_lo, hi, lo, &hi, &lo); + p_sign ^=3D 1; + p_exp =3D c.exp; + } + } else { + shift128RightJamming(c_hi, c_lo, + exp_diff, + &c_hi, &c_lo); + sub128(hi, lo, c_hi, c_lo, &hi, &lo); + } + + if (hi =3D=3D 0 && lo =3D=3D 0) { + a.cls =3D float_class_zero; + a.sign =3D s->float_rounding_mode =3D=3D float_round_down; + a.sign ^=3D sign_flip; + return a; + } else { + int shift; + if (hi !=3D 0) { + shift =3D clz64(hi); + } else { + shift =3D clz64(lo) + 64; + } + /* Normalizing to a binary point of 124 is the + correct adjust for the exponent. However since we're + shifting, we might as well put the binary point back + at 62 where we really want it. Therefore shift as + if we're leaving 1 bit at the top of the word, but + adjust the exponent as if we're leaving 3 bits. */ + shift -=3D 1; + if (shift >=3D 64) { + lo =3D lo << (shift - 64); + } else { + hi =3D (hi << shift) | (lo >> (64 - shift)); + lo =3D hi | ((lo << shift) !=3D 0); + } + p_exp -=3D shift - 2; + } + } + } + + if (flags & float_muladd_halve_result) { + p_exp -=3D 1; + } + + /* finally prepare our result */ + a.cls =3D float_class_normal; + a.sign =3D p_sign ^ sign_flip; + a.exp =3D p_exp; + a.frac =3D lo; + + return a; +} + +float16 __attribute__((flatten)) float16_muladd(float16 a, float16 b, floa= t16 c, + int flags, float_status *s= tatus) +{ + FloatParts pa =3D float16_unpack_canonical(a, status); + FloatParts pb =3D float16_unpack_canonical(b, status); + FloatParts pc =3D float16_unpack_canonical(c, status); + FloatParts pr =3D muladd_floats(pa, pb, pc, flags, status); + + return float16_round_pack_canonical(pr, status); +} + +float32 __attribute__((flatten)) float32_muladd(float32 a, float32 b, floa= t32 c, + int flags, float_status *s= tatus) +{ + FloatParts pa =3D float32_unpack_canonical(a, status); + FloatParts pb =3D float32_unpack_canonical(b, status); + FloatParts pc =3D float32_unpack_canonical(c, status); + FloatParts pr =3D muladd_floats(pa, pb, pc, flags, status); + + return float32_round_pack_canonical(pr, status); +} + +float64 __attribute__((flatten)) float64_muladd(float64 a, float64 b, floa= t64 c, + int flags, float_status *s= tatus) +{ + FloatParts pa =3D float64_unpack_canonical(a, status); + FloatParts pb =3D float64_unpack_canonical(b, status); + FloatParts pc =3D float64_unpack_canonical(c, status); + FloatParts pr =3D muladd_floats(pa, pb, pc, flags, status); + + return float64_round_pack_canonical(pr, status); +} + /* * Returns the result of dividing the floating-point value `a' by the * corresponding value `b'. The operation is performed according to @@ -2817,231 +3088,6 @@ float32 float32_rem(float32 a, float32 b, float_sta= tus *status) return normalizeRoundAndPackFloat32(aSign ^ zSign, bExp, aSig, status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of multiplying the single-precision floating-point va= lues -| `a' and `b' then adding 'c', with no intermediate rounding step after the -| multiplication. The operation is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic 754-2008. -| The flags argument allows the caller to select negation of the -| addend, the intermediate product, or the final result. (The difference -| between this and having the caller do a separate negation is that negati= ng -| externally will flip the sign bit on NaNs.) -*-------------------------------------------------------------------------= ---*/ - -float32 float32_muladd(float32 a, float32 b, float32 c, int flags, - float_status *status) -{ - flag aSign, bSign, cSign, zSign; - int aExp, bExp, cExp, pExp, zExp, expDiff; - uint32_t aSig, bSig, cSig; - flag pInf, pZero, pSign; - uint64_t pSig64, cSig64, zSig64; - uint32_t pSig; - int shiftcount; - flag signflip, infzero; - - a =3D float32_squash_input_denormal(a, status); - b =3D float32_squash_input_denormal(b, status); - c =3D float32_squash_input_denormal(c, status); - aSig =3D extractFloat32Frac(a); - aExp =3D extractFloat32Exp(a); - aSign =3D extractFloat32Sign(a); - bSig =3D extractFloat32Frac(b); - bExp =3D extractFloat32Exp(b); - bSign =3D extractFloat32Sign(b); - cSig =3D extractFloat32Frac(c); - cExp =3D extractFloat32Exp(c); - cSign =3D extractFloat32Sign(c); - - infzero =3D ((aExp =3D=3D 0 && aSig =3D=3D 0 && bExp =3D=3D 0xff && bS= ig =3D=3D 0) || - (aExp =3D=3D 0xff && aSig =3D=3D 0 && bExp =3D=3D 0 && bSig= =3D=3D 0)); - - /* It is implementation-defined whether the cases of (0,inf,qnan) - * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN - * they return if they do), so we have to hand this information - * off to the target-specific pick-a-NaN routine. - */ - if (((aExp =3D=3D 0xff) && aSig) || - ((bExp =3D=3D 0xff) && bSig) || - ((cExp =3D=3D 0xff) && cSig)) { - return propagateFloat32MulAddNaN(a, b, c, infzero, status); - } - - if (infzero) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - - if (flags & float_muladd_negate_c) { - cSign ^=3D 1; - } - - signflip =3D (flags & float_muladd_negate_result) ? 1 : 0; - - /* Work out the sign and type of the product */ - pSign =3D aSign ^ bSign; - if (flags & float_muladd_negate_product) { - pSign ^=3D 1; - } - pInf =3D (aExp =3D=3D 0xff) || (bExp =3D=3D 0xff); - pZero =3D ((aExp | aSig) =3D=3D 0) || ((bExp | bSig) =3D=3D 0); - - if (cExp =3D=3D 0xff) { - if (pInf && (pSign ^ cSign)) { - /* addition of opposite-signed infinities =3D> InvalidOperatio= n */ - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - /* Otherwise generate an infinity of the same sign */ - return packFloat32(cSign ^ signflip, 0xff, 0); - } - - if (pInf) { - return packFloat32(pSign ^ signflip, 0xff, 0); - } - - if (pZero) { - if (cExp =3D=3D 0) { - if (cSig =3D=3D 0) { - /* Adding two exact zeroes */ - if (pSign =3D=3D cSign) { - zSign =3D pSign; - } else if (status->float_rounding_mode =3D=3D float_round_= down) { - zSign =3D 1; - } else { - zSign =3D 0; - } - return packFloat32(zSign ^ signflip, 0, 0); - } - /* Exact zero plus a denorm */ - if (status->flush_to_zero) { - float_raise(float_flag_output_denormal, status); - return packFloat32(cSign ^ signflip, 0, 0); - } - } - /* Zero plus something non-zero : just return the something */ - if (flags & float_muladd_halve_result) { - if (cExp =3D=3D 0) { - normalizeFloat32Subnormal(cSig, &cExp, &cSig); - } - /* Subtract one to halve, and one again because roundAndPackFl= oat32 - * wants one less than the true exponent. - */ - cExp -=3D 2; - cSig =3D (cSig | 0x00800000) << 7; - return roundAndPackFloat32(cSign ^ signflip, cExp, cSig, statu= s); - } - return packFloat32(cSign ^ signflip, cExp, cSig); - } - - if (aExp =3D=3D 0) { - normalizeFloat32Subnormal(aSig, &aExp, &aSig); - } - if (bExp =3D=3D 0) { - normalizeFloat32Subnormal(bSig, &bExp, &bSig); - } - - /* Calculate the actual result a * b + c */ - - /* Multiply first; this is easy. */ - /* NB: we subtract 0x7e where float32_mul() subtracts 0x7f - * because we want the true exponent, not the "one-less-than" - * flavour that roundAndPackFloat32() takes. - */ - pExp =3D aExp + bExp - 0x7e; - aSig =3D (aSig | 0x00800000) << 7; - bSig =3D (bSig | 0x00800000) << 8; - pSig64 =3D (uint64_t)aSig * bSig; - if ((int64_t)(pSig64 << 1) >=3D 0) { - pSig64 <<=3D 1; - pExp--; - } - - zSign =3D pSign ^ signflip; - - /* Now pSig64 is the significand of the multiply, with the explicit bi= t in - * position 62. - */ - if (cExp =3D=3D 0) { - if (!cSig) { - /* Throw out the special case of c being an exact zero now */ - shift64RightJamming(pSig64, 32, &pSig64); - pSig =3D pSig64; - if (flags & float_muladd_halve_result) { - pExp--; - } - return roundAndPackFloat32(zSign, pExp - 1, - pSig, status); - } - normalizeFloat32Subnormal(cSig, &cExp, &cSig); - } - - cSig64 =3D (uint64_t)cSig << (62 - 23); - cSig64 |=3D LIT64(0x4000000000000000); - expDiff =3D pExp - cExp; - - if (pSign =3D=3D cSign) { - /* Addition */ - if (expDiff > 0) { - /* scale c to match p */ - shift64RightJamming(cSig64, expDiff, &cSig64); - zExp =3D pExp; - } else if (expDiff < 0) { - /* scale p to match c */ - shift64RightJamming(pSig64, -expDiff, &pSig64); - zExp =3D cExp; - } else { - /* no scaling needed */ - zExp =3D cExp; - } - /* Add significands and make sure explicit bit ends up in posn 62 = */ - zSig64 =3D pSig64 + cSig64; - if ((int64_t)zSig64 < 0) { - shift64RightJamming(zSig64, 1, &zSig64); - } else { - zExp--; - } - } else { - /* Subtraction */ - if (expDiff > 0) { - shift64RightJamming(cSig64, expDiff, &cSig64); - zSig64 =3D pSig64 - cSig64; - zExp =3D pExp; - } else if (expDiff < 0) { - shift64RightJamming(pSig64, -expDiff, &pSig64); - zSig64 =3D cSig64 - pSig64; - zExp =3D cExp; - zSign ^=3D 1; - } else { - zExp =3D pExp; - if (cSig64 < pSig64) { - zSig64 =3D pSig64 - cSig64; - } else if (pSig64 < cSig64) { - zSig64 =3D cSig64 - pSig64; - zSign ^=3D 1; - } else { - /* Exact zero */ - zSign =3D signflip; - if (status->float_rounding_mode =3D=3D float_round_down) { - zSign ^=3D 1; - } - return packFloat32(zSign, 0, 0); - } - } - --zExp; - /* Normalize to put the explicit bit back into bit 62. */ - shiftcount =3D countLeadingZeros64(zSig64) - 1; - zSig64 <<=3D shiftcount; - zExp -=3D shiftcount; - } - if (flags & float_muladd_halve_result) { - zExp--; - } - - shift64RightJamming(zSig64, 32, &zSig64); - return roundAndPackFloat32(zSign, zExp, zSig64, status); -} - =20 /*------------------------------------------------------------------------= ---- | Returns the square root of the single-precision floating-point value `a'. @@ -4265,252 +4311,6 @@ float64 float64_rem(float64 a, float64 b, float_sta= tus *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of multiplying the double-precision floating-point va= lues -| `a' and `b' then adding 'c', with no intermediate rounding step after the -| multiplication. The operation is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic 754-2008. -| The flags argument allows the caller to select negation of the -| addend, the intermediate product, or the final result. (The difference -| between this and having the caller do a separate negation is that negati= ng -| externally will flip the sign bit on NaNs.) -*-------------------------------------------------------------------------= ---*/ - -float64 float64_muladd(float64 a, float64 b, float64 c, int flags, - float_status *status) -{ - flag aSign, bSign, cSign, zSign; - int aExp, bExp, cExp, pExp, zExp, expDiff; - uint64_t aSig, bSig, cSig; - flag pInf, pZero, pSign; - uint64_t pSig0, pSig1, cSig0, cSig1, zSig0, zSig1; - int shiftcount; - flag signflip, infzero; - - a =3D float64_squash_input_denormal(a, status); - b =3D float64_squash_input_denormal(b, status); - c =3D float64_squash_input_denormal(c, status); - aSig =3D extractFloat64Frac(a); - aExp =3D extractFloat64Exp(a); - aSign =3D extractFloat64Sign(a); - bSig =3D extractFloat64Frac(b); - bExp =3D extractFloat64Exp(b); - bSign =3D extractFloat64Sign(b); - cSig =3D extractFloat64Frac(c); - cExp =3D extractFloat64Exp(c); - cSign =3D extractFloat64Sign(c); - - infzero =3D ((aExp =3D=3D 0 && aSig =3D=3D 0 && bExp =3D=3D 0x7ff && b= Sig =3D=3D 0) || - (aExp =3D=3D 0x7ff && aSig =3D=3D 0 && bExp =3D=3D 0 && bSi= g =3D=3D 0)); - - /* It is implementation-defined whether the cases of (0,inf,qnan) - * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN - * they return if they do), so we have to hand this information - * off to the target-specific pick-a-NaN routine. - */ - if (((aExp =3D=3D 0x7ff) && aSig) || - ((bExp =3D=3D 0x7ff) && bSig) || - ((cExp =3D=3D 0x7ff) && cSig)) { - return propagateFloat64MulAddNaN(a, b, c, infzero, status); - } - - if (infzero) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - - if (flags & float_muladd_negate_c) { - cSign ^=3D 1; - } - - signflip =3D (flags & float_muladd_negate_result) ? 1 : 0; - - /* Work out the sign and type of the product */ - pSign =3D aSign ^ bSign; - if (flags & float_muladd_negate_product) { - pSign ^=3D 1; - } - pInf =3D (aExp =3D=3D 0x7ff) || (bExp =3D=3D 0x7ff); - pZero =3D ((aExp | aSig) =3D=3D 0) || ((bExp | bSig) =3D=3D 0); - - if (cExp =3D=3D 0x7ff) { - if (pInf && (pSign ^ cSign)) { - /* addition of opposite-signed infinities =3D> InvalidOperatio= n */ - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - /* Otherwise generate an infinity of the same sign */ - return packFloat64(cSign ^ signflip, 0x7ff, 0); - } - - if (pInf) { - return packFloat64(pSign ^ signflip, 0x7ff, 0); - } - - if (pZero) { - if (cExp =3D=3D 0) { - if (cSig =3D=3D 0) { - /* Adding two exact zeroes */ - if (pSign =3D=3D cSign) { - zSign =3D pSign; - } else if (status->float_rounding_mode =3D=3D float_round_= down) { - zSign =3D 1; - } else { - zSign =3D 0; - } - return packFloat64(zSign ^ signflip, 0, 0); - } - /* Exact zero plus a denorm */ - if (status->flush_to_zero) { - float_raise(float_flag_output_denormal, status); - return packFloat64(cSign ^ signflip, 0, 0); - } - } - /* Zero plus something non-zero : just return the something */ - if (flags & float_muladd_halve_result) { - if (cExp =3D=3D 0) { - normalizeFloat64Subnormal(cSig, &cExp, &cSig); - } - /* Subtract one to halve, and one again because roundAndPackFl= oat64 - * wants one less than the true exponent. - */ - cExp -=3D 2; - cSig =3D (cSig | 0x0010000000000000ULL) << 10; - return roundAndPackFloat64(cSign ^ signflip, cExp, cSig, statu= s); - } - return packFloat64(cSign ^ signflip, cExp, cSig); - } - - if (aExp =3D=3D 0) { - normalizeFloat64Subnormal(aSig, &aExp, &aSig); - } - if (bExp =3D=3D 0) { - normalizeFloat64Subnormal(bSig, &bExp, &bSig); - } - - /* Calculate the actual result a * b + c */ - - /* Multiply first; this is easy. */ - /* NB: we subtract 0x3fe where float64_mul() subtracts 0x3ff - * because we want the true exponent, not the "one-less-than" - * flavour that roundAndPackFloat64() takes. - */ - pExp =3D aExp + bExp - 0x3fe; - aSig =3D (aSig | LIT64(0x0010000000000000))<<10; - bSig =3D (bSig | LIT64(0x0010000000000000))<<11; - mul64To128(aSig, bSig, &pSig0, &pSig1); - if ((int64_t)(pSig0 << 1) >=3D 0) { - shortShift128Left(pSig0, pSig1, 1, &pSig0, &pSig1); - pExp--; - } - - zSign =3D pSign ^ signflip; - - /* Now [pSig0:pSig1] is the significand of the multiply, with the expl= icit - * bit in position 126. - */ - if (cExp =3D=3D 0) { - if (!cSig) { - /* Throw out the special case of c being an exact zero now */ - shift128RightJamming(pSig0, pSig1, 64, &pSig0, &pSig1); - if (flags & float_muladd_halve_result) { - pExp--; - } - return roundAndPackFloat64(zSign, pExp - 1, - pSig1, status); - } - normalizeFloat64Subnormal(cSig, &cExp, &cSig); - } - - /* Shift cSig and add the explicit bit so [cSig0:cSig1] is the - * significand of the addend, with the explicit bit in position 126. - */ - cSig0 =3D cSig << (126 - 64 - 52); - cSig1 =3D 0; - cSig0 |=3D LIT64(0x4000000000000000); - expDiff =3D pExp - cExp; - - if (pSign =3D=3D cSign) { - /* Addition */ - if (expDiff > 0) { - /* scale c to match p */ - shift128RightJamming(cSig0, cSig1, expDiff, &cSig0, &cSig1); - zExp =3D pExp; - } else if (expDiff < 0) { - /* scale p to match c */ - shift128RightJamming(pSig0, pSig1, -expDiff, &pSig0, &pSig1); - zExp =3D cExp; - } else { - /* no scaling needed */ - zExp =3D cExp; - } - /* Add significands and make sure explicit bit ends up in posn 126= */ - add128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1); - if ((int64_t)zSig0 < 0) { - shift128RightJamming(zSig0, zSig1, 1, &zSig0, &zSig1); - } else { - zExp--; - } - shift128RightJamming(zSig0, zSig1, 64, &zSig0, &zSig1); - if (flags & float_muladd_halve_result) { - zExp--; - } - return roundAndPackFloat64(zSign, zExp, zSig1, status); - } else { - /* Subtraction */ - if (expDiff > 0) { - shift128RightJamming(cSig0, cSig1, expDiff, &cSig0, &cSig1); - sub128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1); - zExp =3D pExp; - } else if (expDiff < 0) { - shift128RightJamming(pSig0, pSig1, -expDiff, &pSig0, &pSig1); - sub128(cSig0, cSig1, pSig0, pSig1, &zSig0, &zSig1); - zExp =3D cExp; - zSign ^=3D 1; - } else { - zExp =3D pExp; - if (lt128(cSig0, cSig1, pSig0, pSig1)) { - sub128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1); - } else if (lt128(pSig0, pSig1, cSig0, cSig1)) { - sub128(cSig0, cSig1, pSig0, pSig1, &zSig0, &zSig1); - zSign ^=3D 1; - } else { - /* Exact zero */ - zSign =3D signflip; - if (status->float_rounding_mode =3D=3D float_round_down) { - zSign ^=3D 1; - } - return packFloat64(zSign, 0, 0); - } - } - --zExp; - /* Do the equivalent of normalizeRoundAndPackFloat64() but - * starting with the significand in a pair of uint64_t. - */ - if (zSig0) { - shiftcount =3D countLeadingZeros64(zSig0) - 1; - shortShift128Left(zSig0, zSig1, shiftcount, &zSig0, &zSig1); - if (zSig1) { - zSig0 |=3D 1; - } - zExp -=3D shiftcount; - } else { - shiftcount =3D countLeadingZeros64(zSig1); - if (shiftcount =3D=3D 0) { - zSig0 =3D (zSig1 >> 1) | (zSig1 & 1); - zExp -=3D 63; - } else { - shiftcount--; - zSig0 =3D zSig1 << shiftcount; - zExp -=3D (shiftcount + 64); - } - } - if (flags & float_muladd_halve_result) { - zExp--; - } - return roundAndPackFloat64(zSign, zExp, zSig0, status); - } -} =20 /*------------------------------------------------------------------------= ---- | Returns the square root of the double-precision floating-point value `a'. diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 85e4a74f1b..65bc7442d2 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -240,6 +240,7 @@ float64 float16_to_float64(float16 a, flag ieee, float_= status *status); float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); float16 float16_mul(float16, float16, float_status *status); +float16 float16_muladd(float16, float16, float16, int, float_status *statu= s); float16 float16_div(float16, float16, float_status *status); =20 int float16_is_quiet_nan(float16, float_status *status); --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517936578508249.61077012758358; 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Tue, 06 Feb 2018 08:48:32 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org, peter.maydell@linaro.org, laurent@vivier.eu, bharata@linux.vnet.ibm.com, andrew@andrewdutcher.com Date: Tue, 6 Feb 2018 16:48:09 +0000 Message-Id: <20180206164815.10084-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180206164815.10084-1-alex.bennee@linaro.org> References: <20180206164815.10084-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v4 16/22] fpu/softfloat: re-factor round_to_int X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We can now add float16_round_to_int and use the common round_decomposed and canonicalize functions to have a single implementation for float16/32/64 round_to_int functions. Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3 - rename structures and functions v4 - move NaN handling to return NaN --- fpu/softfloat.c | 322 ++++++++++++++++++++++----------------------= ---- include/fpu/softfloat.h | 1 + 2 files changed, 148 insertions(+), 175 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ae4ba6de51..5d04e65538 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -560,7 +560,26 @@ static bool is_qnan(FloatClass c) return c =3D=3D float_class_qnan; } =20 -static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) +static inline FloatParts return_nan(FloatParts a, float_status *s) +{ + switch (a.cls) { + case float_class_snan: + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_msnan; + /* FALLTHRU */ + case float_class_qnan: + if (s->default_nan_mode) { + a.cls =3D float_class_dnan; + } + break; + + default: + g_assert_not_reached(); + } + return a; +} + +static inline FloatParts pick_nan(FloatParts a, FloatParts b, float_status= *s) { if (is_snan(a.cls) || is_snan(b.cls)) { s->float_exception_flags |=3D float_flag_invalid; @@ -1175,6 +1194,133 @@ float64 float64_div(float64 a, float64 b, float_sta= tus *status) return float64_round_pack_canonical(pr, status); } =20 +/* + * Rounds the floating-point value `a' to an integer, and returns the + * result as a floating-point value. The operation is performed + * according to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic. + */ + +static FloatParts round_to_int(FloatParts a, int rounding_mode, float_stat= us *s) +{ + if (is_nan(a.cls)) { + return return_nan(a, s); + } + + switch (a.cls) { + case float_class_zero: + case float_class_inf: + case float_class_qnan: + /* already "integral" */ + break; + case float_class_normal: + if (a.exp >=3D DECOMPOSED_BINARY_POINT) { + /* already integral */ + break; + } + if (a.exp < 0) { + bool one; + /* all fractional */ + s->float_exception_flags |=3D float_flag_inexact; + switch (rounding_mode) { + case float_round_nearest_even: + one =3D a.exp =3D=3D -1 && a.frac > DECOMPOSED_IMPLICIT_BI= T; + break; + case float_round_ties_away: + one =3D a.exp =3D=3D -1 && a.frac >=3D DECOMPOSED_IMPLICIT= _BIT; + break; + case float_round_to_zero: + one =3D false; + break; + case float_round_up: + one =3D !a.sign; + break; + case float_round_down: + one =3D a.sign; + break; + default: + g_assert_not_reached(); + } + + if (one) { + a.frac =3D DECOMPOSED_IMPLICIT_BIT; + a.exp =3D 0; + } else { + a.cls =3D float_class_zero; + } + } else { + uint64_t frac_lsb, frac_lsbm1, round_mask, roundeven_mask, inc; + + frac_lsb =3D DECOMPOSED_IMPLICIT_BIT >> a.exp; + frac_lsbm1 =3D frac_lsb >> 1; + roundeven_mask =3D (frac_lsb - 1) | frac_lsb; + round_mask =3D roundeven_mask >> 1; + + switch (rounding_mode) { + case float_round_nearest_even: + inc =3D ((a.frac & roundeven_mask) !=3D frac_lsbm1 ? frac_= lsbm1 : 0); + break; + case float_round_ties_away: + inc =3D frac_lsbm1; + break; + case float_round_to_zero: + inc =3D 0; + break; + case float_round_up: + inc =3D a.sign ? 0 : round_mask; + break; + case float_round_down: + inc =3D a.sign ? round_mask : 0; + break; + default: + g_assert_not_reached(); + } + + if (a.frac & round_mask) { + s->float_exception_flags |=3D float_flag_inexact; + a.frac +=3D inc; + a.frac &=3D ~round_mask; + if (a.frac & DECOMPOSED_OVERFLOW_BIT) { + a.frac >>=3D 1; + a.exp++; + } + } + } + break; + default: + g_assert_not_reached(); + } + return a; +} + +float16 float16_round_to_int(float16 a, float_status *s) +{ + FloatParts pa =3D float16_unpack_canonical(a, s); + FloatParts pr =3D round_to_int(pa, s->float_rounding_mode, s); + return float16_round_pack_canonical(pr, s); +} + +float32 float32_round_to_int(float32 a, float_status *s) +{ + FloatParts pa =3D float32_unpack_canonical(a, s); + FloatParts pr =3D round_to_int(pa, s->float_rounding_mode, s); + return float32_round_pack_canonical(pr, s); +} + +float64 float64_round_to_int(float64 a, float_status *s) +{ + FloatParts pa =3D float64_unpack_canonical(a, s); + FloatParts pr =3D round_to_int(pa, s->float_rounding_mode, s); + return float64_round_pack_canonical(pr, s); +} + +float64 float64_trunc_to_int(float64 a, float_status *s) +{ + FloatParts pa =3D float64_unpack_canonical(a, s); + FloatParts pr =3D round_to_int(pa, float_round_to_zero, s); + return float64_round_pack_canonical(pr, s); +} + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the @@ -2905,87 +3051,6 @@ float128 float32_to_float128(float32 a, float_status= *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Rounds the single-precision floating-point value `a' to an integer, and -| returns the result as a single-precision floating-point value. The -| operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_round_to_int(float32 a, float_status *status) -{ - flag aSign; - int aExp; - uint32_t lastBitMask, roundBitsMask; - uint32_t z; - a =3D float32_squash_input_denormal(a, status); - - aExp =3D extractFloat32Exp( a ); - if ( 0x96 <=3D aExp ) { - if ( ( aExp =3D=3D 0xFF ) && extractFloat32Frac( a ) ) { - return propagateFloat32NaN(a, a, status); - } - return a; - } - if ( aExp <=3D 0x7E ) { - if ( (uint32_t) ( float32_val(a)<<1 ) =3D=3D 0 ) return a; - status->float_exception_flags |=3D float_flag_inexact; - aSign =3D extractFloat32Sign( a ); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - if ( ( aExp =3D=3D 0x7E ) && extractFloat32Frac( a ) ) { - return packFloat32( aSign, 0x7F, 0 ); - } - break; - case float_round_ties_away: - if (aExp =3D=3D 0x7E) { - return packFloat32(aSign, 0x7F, 0); - } - break; - case float_round_down: - return make_float32(aSign ? 0xBF800000 : 0); - case float_round_up: - return make_float32(aSign ? 0x80000000 : 0x3F800000); - } - return packFloat32( aSign, 0, 0 ); - } - lastBitMask =3D 1; - lastBitMask <<=3D 0x96 - aExp; - roundBitsMask =3D lastBitMask - 1; - z =3D float32_val(a); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - z +=3D lastBitMask>>1; - if ((z & roundBitsMask) =3D=3D 0) { - z &=3D ~lastBitMask; - } - break; - case float_round_ties_away: - z +=3D lastBitMask >> 1; - break; - case float_round_to_zero: - break; - case float_round_up: - if (!extractFloat32Sign(make_float32(z))) { - z +=3D roundBitsMask; - } - break; - case float_round_down: - if (extractFloat32Sign(make_float32(z))) { - z +=3D roundBitsMask; - } - break; - default: - abort(); - } - z &=3D ~ roundBitsMask; - if (z !=3D float32_val(a)) { - status->float_exception_flags |=3D float_flag_inexact; - } - return make_float32(z); - -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the single-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -4129,99 +4194,6 @@ float128 float64_to_float128(float64 a, float_status= *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Rounds the double-precision floating-point value `a' to an integer, and -| returns the result as a double-precision floating-point value. The -| operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_round_to_int(float64 a, float_status *status) -{ - flag aSign; - int aExp; - uint64_t lastBitMask, roundBitsMask; - uint64_t z; - a =3D float64_squash_input_denormal(a, status); - - aExp =3D extractFloat64Exp( a ); - if ( 0x433 <=3D aExp ) { - if ( ( aExp =3D=3D 0x7FF ) && extractFloat64Frac( a ) ) { - return propagateFloat64NaN(a, a, status); - } - return a; - } - if ( aExp < 0x3FF ) { - if ( (uint64_t) ( float64_val(a)<<1 ) =3D=3D 0 ) return a; - status->float_exception_flags |=3D float_flag_inexact; - aSign =3D extractFloat64Sign( a ); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - if ( ( aExp =3D=3D 0x3FE ) && extractFloat64Frac( a ) ) { - return packFloat64( aSign, 0x3FF, 0 ); - } - break; - case float_round_ties_away: - if (aExp =3D=3D 0x3FE) { - return packFloat64(aSign, 0x3ff, 0); - } - break; - case float_round_down: - return make_float64(aSign ? LIT64( 0xBFF0000000000000 ) : 0); - case float_round_up: - return make_float64( - aSign ? LIT64( 0x8000000000000000 ) : LIT64( 0x3FF000000000000= 0 )); - } - return packFloat64( aSign, 0, 0 ); - } - lastBitMask =3D 1; - lastBitMask <<=3D 0x433 - aExp; - roundBitsMask =3D lastBitMask - 1; - z =3D float64_val(a); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - z +=3D lastBitMask >> 1; - if ((z & roundBitsMask) =3D=3D 0) { - z &=3D ~lastBitMask; - } - break; - case float_round_ties_away: - z +=3D lastBitMask >> 1; - break; - case float_round_to_zero: - break; - case float_round_up: - if (!extractFloat64Sign(make_float64(z))) { - z +=3D roundBitsMask; - } - break; - case float_round_down: - if (extractFloat64Sign(make_float64(z))) { - z +=3D roundBitsMask; - } - break; - default: - abort(); - } - z &=3D ~ roundBitsMask; - if (z !=3D float64_val(a)) { - status->float_exception_flags |=3D float_flag_inexact; - } - return make_float64(z); - -} - -float64 float64_trunc_to_int(float64 a, float_status *status) -{ - int oldmode; - float64 res; - oldmode =3D status->float_rounding_mode; - status->float_rounding_mode =3D float_round_to_zero; - res =3D float64_round_to_int(a, status); - status->float_rounding_mode =3D oldmode; - return res; -} - =20 /*------------------------------------------------------------------------= ---- | Returns the remainder of the double-precision floating-point value `a' diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 65bc7442d2..4650758c23 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -237,6 +237,7 @@ float64 float16_to_float64(float16 a, flag ieee, float_= status *status); | Software half-precision operations. *-------------------------------------------------------------------------= ---*/ =20 +float16 float16_round_to_int(float16, float_status *status); float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); float16 float16_mul(float16, float16, float_status *status); --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v4 17/22] fpu/softfloat: re-factor float to int/uint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We share the common int64/uint64_pack_decomposed function across all the helpers and simply limit the final result depending on the final size. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - apply float_flg_invalid fixes next patch v3 - re-factor to common round_to_int/uint_and_pack - save flag state so invalid can override inexact - float to int/uint naming fixes --- fpu/softfloat.c | 935 ++++++++++----------------------------------= ---- include/fpu/softfloat.h | 13 + 2 files changed, 193 insertions(+), 755 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 5d04e65538..216d60df6e 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1321,6 +1321,186 @@ float64 float64_trunc_to_int(float64 a, float_statu= s *s) return float64_round_pack_canonical(pr, s); } =20 +/* + * Returns the result of converting the floating-point value `a' to + * the two's complement integer format. The conversion is performed + * according to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic---which means in particular that the conversion is + * rounded according to the current rounding mode. If `a' is a NaN, + * the largest positive integer is returned. Otherwise, if the + * conversion overflows, the largest integer with the same sign as `a' + * is returned. +*/ + +static int64_t round_to_int_and_pack(FloatParts in, int rmode, + int64_t min, int64_t max, + float_status *s) +{ + uint64_t r; + int orig_flags =3D get_float_exception_flags(s); + FloatParts p =3D round_to_int(in, rmode, s); + + switch (p.cls) { + case float_class_snan: + case float_class_qnan: + return max; + case float_class_inf: + return p.sign ? min : max; + case float_class_zero: + return 0; + case float_class_normal: + if (p.exp < DECOMPOSED_BINARY_POINT) { + r =3D p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); + } else if (p.exp - DECOMPOSED_BINARY_POINT < 2) { + r =3D p.frac << (p.exp - DECOMPOSED_BINARY_POINT); + } else { + r =3D UINT64_MAX; + } + if (p.sign) { + if (r < -(uint64_t) min) { + return -r; + } else { + s->float_exception_flags =3D orig_flags | float_flag_inval= id; + return min; + } + } else { + if (r < max) { + return r; + } else { + s->float_exception_flags =3D orig_flags | float_flag_inval= id; + return max; + } + } + default: + g_assert_not_reached(); + } +} + +#define FLOAT_TO_INT(fsz, isz) \ +int ## isz ## _t float ## fsz ## _to_int ## isz(float ## fsz a, \ + float_status *s) \ +{ \ + FloatParts p =3D float ## fsz ## _unpack_canonical(a, s); \ + return round_to_int_and_pack(p, s->float_rounding_mode, \ + INT ## isz ## _MIN, INT ## isz ## _MAX,\ + s); \ +} \ + \ +int ## isz ## _t float ## fsz ## _to_int ## isz ## _round_to_zero \ + (float ## fsz a, float_status *s) \ +{ \ + FloatParts p =3D float ## fsz ## _unpack_canonical(a, s); \ + return round_to_int_and_pack(p, float_round_to_zero, \ + INT ## isz ## _MIN, INT ## isz ## _MAX,\ + s); \ +} + +FLOAT_TO_INT(16, 16) +FLOAT_TO_INT(16, 32) +FLOAT_TO_INT(16, 64) + +FLOAT_TO_INT(32, 16) +FLOAT_TO_INT(32, 32) +FLOAT_TO_INT(32, 64) + +FLOAT_TO_INT(64, 16) +FLOAT_TO_INT(64, 32) +FLOAT_TO_INT(64, 64) + +#undef FLOAT_TO_INT + +/* + * Returns the result of converting the floating-point value `a' to + * the unsigned integer format. The conversion is performed according + * to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic---which means in particular that the conversion is + * rounded according to the current rounding mode. If `a' is a NaN, + * the largest unsigned integer is returned. Otherwise, if the + * conversion overflows, the largest unsigned integer is returned. If + * the 'a' is negative, the result is rounded and zero is returned; + * values that do not round to zero will raise the inexact exception + * flag. + */ + +static uint64_t round_to_uint_and_pack(FloatParts in, int rmode, uint64_t = max, + float_status *s) +{ + int orig_flags =3D get_float_exception_flags(s); + FloatParts p =3D round_to_int(in, rmode, s); + + switch (p.cls) { + case float_class_snan: + case float_class_qnan: + s->float_exception_flags =3D orig_flags | float_flag_invalid; + return max; + case float_class_inf: + return p.sign ? 0 : max; + case float_class_zero: + return 0; + case float_class_normal: + { + uint64_t r; + if (p.sign) { + s->float_exception_flags =3D orig_flags | float_flag_invalid; + return 0; + } + + if (p.exp < DECOMPOSED_BINARY_POINT) { + r =3D p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); + } else if (p.exp - DECOMPOSED_BINARY_POINT < 2) { + r =3D p.frac << (p.exp - DECOMPOSED_BINARY_POINT); + } else { + s->float_exception_flags =3D orig_flags | float_flag_invalid; + return max; + } + + /* For uint64 this will never trip, but if p.exp is too large + * to shift a decomposed fraction we shall have exited via the + * 3rd leg above. + */ + if (r > max) { + s->float_exception_flags =3D orig_flags | float_flag_invalid; + return max; + } else { + return r; + } + } + default: + g_assert_not_reached(); + } +} + +#define FLOAT_TO_UINT(fsz, isz) \ +uint ## isz ## _t float ## fsz ## _to_uint ## isz(float ## fsz a, \ + float_status *s) \ +{ \ + FloatParts p =3D float ## fsz ## _unpack_canonical(a, s); \ + return round_to_uint_and_pack(p, s->float_rounding_mode, \ + UINT ## isz ## _MAX, s); \ +} \ + \ +uint ## isz ## _t float ## fsz ## _to_uint ## isz ## _round_to_zero \ + (float ## fsz a, float_status *s) \ +{ \ + FloatParts p =3D float ## fsz ## _unpack_canonical(a, s); \ + return round_to_uint_and_pack(p, s->float_rounding_mode, \ + UINT ## isz ## _MAX, s); \ +} + +FLOAT_TO_UINT(16, 16) +FLOAT_TO_UINT(16, 32) +FLOAT_TO_UINT(16, 64) + +FLOAT_TO_UINT(32, 16) +FLOAT_TO_UINT(32, 32) +FLOAT_TO_UINT(32, 64) + +FLOAT_TO_UINT(64, 16) +FLOAT_TO_UINT(64, 32) +FLOAT_TO_UINT(64, 64) + +#undef FLOAT_TO_UINT + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the @@ -2672,288 +2852,8 @@ float128 uint64_to_float128(uint64_t a, float_statu= s *status) return normalizeRoundAndPackFloat128(0, 0x406E, a, 0, status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point val= ue -| `a' to the 32-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. Otherwise, if the conversion overflows, t= he -| largest integer with the same sign as `a' is returned. -*-------------------------------------------------------------------------= ---*/ - -int32_t float32_to_int32(float32 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint32_t aSig; - uint64_t aSig64; - - a =3D float32_squash_input_denormal(a, status); - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - if ( ( aExp =3D=3D 0xFF ) && aSig ) aSign =3D 0; - if ( aExp ) aSig |=3D 0x00800000; - shiftCount =3D 0xAF - aExp; - aSig64 =3D aSig; - aSig64 <<=3D 32; - if ( 0 < shiftCount ) shift64RightJamming( aSig64, shiftCount, &aSig64= ); - return roundAndPackInt32(aSign, aSig64, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point val= ue -| `a' to the 32-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. -| If `a' is a NaN, the largest positive integer is returned. Otherwise, if -| the conversion overflows, the largest integer with the same sign as `a' = is -| returned. -*-------------------------------------------------------------------------= ---*/ =20 -int32_t float32_to_int32_round_to_zero(float32 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint32_t aSig; - int32_t z; - a =3D float32_squash_input_denormal(a, status); =20 - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - shiftCount =3D aExp - 0x9E; - if ( 0 <=3D shiftCount ) { - if ( float32_val(a) !=3D 0xCF000000 ) { - float_raise(float_flag_invalid, status); - if ( ! aSign || ( ( aExp =3D=3D 0xFF ) && aSig ) ) return 0x7F= FFFFFF; - } - return (int32_t) 0x80000000; - } - else if ( aExp <=3D 0x7E ) { - if (aExp | aSig) { - status->float_exception_flags |=3D float_flag_inexact; - } - return 0; - } - aSig =3D ( aSig | 0x00800000 )<<8; - z =3D aSig>>( - shiftCount ); - if ( (uint32_t) ( aSig<<( shiftCount & 31 ) ) ) { - status->float_exception_flags |=3D float_flag_inexact; - } - if ( aSign ) z =3D - z; - return z; - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point val= ue -| `a' to the 16-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. -| If `a' is a NaN, the largest positive integer is returned. Otherwise, if -| the conversion overflows, the largest integer with the same sign as `a' = is -| returned. -*-------------------------------------------------------------------------= ---*/ - -int16_t float32_to_int16_round_to_zero(float32 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint32_t aSig; - int32_t z; - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - shiftCount =3D aExp - 0x8E; - if ( 0 <=3D shiftCount ) { - if ( float32_val(a) !=3D 0xC7000000 ) { - float_raise(float_flag_invalid, status); - if ( ! aSign || ( ( aExp =3D=3D 0xFF ) && aSig ) ) { - return 0x7FFF; - } - } - return (int32_t) 0xffff8000; - } - else if ( aExp <=3D 0x7E ) { - if ( aExp | aSig ) { - status->float_exception_flags |=3D float_flag_inexact; - } - return 0; - } - shiftCount -=3D 0x10; - aSig =3D ( aSig | 0x00800000 )<<8; - z =3D aSig>>( - shiftCount ); - if ( (uint32_t) ( aSig<<( shiftCount & 31 ) ) ) { - status->float_exception_flags |=3D float_flag_inexact; - } - if ( aSign ) { - z =3D - z; - } - return z; - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point val= ue -| `a' to the 64-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. Otherwise, if the conversion overflows, t= he -| largest integer with the same sign as `a' is returned. -*-------------------------------------------------------------------------= ---*/ - -int64_t float32_to_int64(float32 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint32_t aSig; - uint64_t aSig64, aSigExtra; - a =3D float32_squash_input_denormal(a, status); - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - shiftCount =3D 0xBE - aExp; - if ( shiftCount < 0 ) { - float_raise(float_flag_invalid, status); - if ( ! aSign || ( ( aExp =3D=3D 0xFF ) && aSig ) ) { - return LIT64( 0x7FFFFFFFFFFFFFFF ); - } - return (int64_t) LIT64( 0x8000000000000000 ); - } - if ( aExp ) aSig |=3D 0x00800000; - aSig64 =3D aSig; - aSig64 <<=3D 40; - shift64ExtraRightJamming( aSig64, 0, shiftCount, &aSig64, &aSigExtra ); - return roundAndPackInt64(aSign, aSig64, aSigExtra, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point val= ue -| `a' to the 64-bit unsigned integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| unsigned integer is returned. Otherwise, if the conversion overflows, t= he -| largest unsigned integer is returned. If the 'a' is negative, the result -| is rounded and zero is returned; values that do not round to zero will -| raise the inexact exception flag. -*-------------------------------------------------------------------------= ---*/ - -uint64_t float32_to_uint64(float32 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint32_t aSig; - uint64_t aSig64, aSigExtra; - a =3D float32_squash_input_denormal(a, status); - - aSig =3D extractFloat32Frac(a); - aExp =3D extractFloat32Exp(a); - aSign =3D extractFloat32Sign(a); - if ((aSign) && (aExp > 126)) { - float_raise(float_flag_invalid, status); - if (float32_is_any_nan(a)) { - return LIT64(0xFFFFFFFFFFFFFFFF); - } else { - return 0; - } - } - shiftCount =3D 0xBE - aExp; - if (aExp) { - aSig |=3D 0x00800000; - } - if (shiftCount < 0) { - float_raise(float_flag_invalid, status); - return LIT64(0xFFFFFFFFFFFFFFFF); - } - - aSig64 =3D aSig; - aSig64 <<=3D 40; - shift64ExtraRightJamming(aSig64, 0, shiftCount, &aSig64, &aSigExtra); - return roundAndPackUint64(aSign, aSig64, aSigExtra, status); -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point val= ue -| `a' to the 64-bit unsigned integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. If -| `a' is a NaN, the largest unsigned integer is returned. Otherwise, if t= he -| conversion overflows, the largest unsigned integer is returned. If the -| 'a' is negative, the result is rounded and zero is returned; values that= do -| not round to zero will raise the inexact flag. -*-------------------------------------------------------------------------= ---*/ - -uint64_t float32_to_uint64_round_to_zero(float32 a, float_status *status) -{ - signed char current_rounding_mode =3D status->float_rounding_mode; - set_float_rounding_mode(float_round_to_zero, status); - int64_t v =3D float32_to_uint64(a, status); - set_float_rounding_mode(current_rounding_mode, status); - return v; -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point val= ue -| `a' to the 64-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. If -| `a' is a NaN, the largest positive integer is returned. Otherwise, if t= he -| conversion overflows, the largest integer with the same sign as `a' is -| returned. -*-------------------------------------------------------------------------= ---*/ - -int64_t float32_to_int64_round_to_zero(float32 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint32_t aSig; - uint64_t aSig64; - int64_t z; - a =3D float32_squash_input_denormal(a, status); - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - shiftCount =3D aExp - 0xBE; - if ( 0 <=3D shiftCount ) { - if ( float32_val(a) !=3D 0xDF000000 ) { - float_raise(float_flag_invalid, status); - if ( ! aSign || ( ( aExp =3D=3D 0xFF ) && aSig ) ) { - return LIT64( 0x7FFFFFFFFFFFFFFF ); - } - } - return (int64_t) LIT64( 0x8000000000000000 ); - } - else if ( aExp <=3D 0x7E ) { - if (aExp | aSig) { - status->float_exception_flags |=3D float_flag_inexact; - } - return 0; - } - aSig64 =3D aSig | 0x00800000; - aSig64 <<=3D 40; - z =3D aSig64>>( - shiftCount ); - if ( (uint64_t) ( aSig64<<( shiftCount & 63 ) ) ) { - status->float_exception_flags |=3D float_flag_inexact; - } - if ( aSign ) z =3D - z; - return z; - -} =20 /*------------------------------------------------------------------------= ---- | Returns the result of converting the single-precision floating-point val= ue @@ -3559,236 +3459,6 @@ int float32_unordered_quiet(float32 a, float32 b, f= loat_status *status) return 0; } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the double-precision floating-point val= ue -| `a' to the 32-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. Otherwise, if the conversion overflows, t= he -| largest integer with the same sign as `a' is returned. -*-------------------------------------------------------------------------= ---*/ - -int32_t float64_to_int32(float64 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint64_t aSig; - a =3D float64_squash_input_denormal(a, status); - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - if ( ( aExp =3D=3D 0x7FF ) && aSig ) aSign =3D 0; - if ( aExp ) aSig |=3D LIT64( 0x0010000000000000 ); - shiftCount =3D 0x42C - aExp; - if ( 0 < shiftCount ) shift64RightJamming( aSig, shiftCount, &aSig ); - return roundAndPackInt32(aSign, aSig, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the double-precision floating-point val= ue -| `a' to the 32-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. -| If `a' is a NaN, the largest positive integer is returned. Otherwise, if -| the conversion overflows, the largest integer with the same sign as `a' = is -| returned. -*-------------------------------------------------------------------------= ---*/ - -int32_t float64_to_int32_round_to_zero(float64 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint64_t aSig, savedASig; - int32_t z; - a =3D float64_squash_input_denormal(a, status); - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - if ( 0x41E < aExp ) { - if ( ( aExp =3D=3D 0x7FF ) && aSig ) aSign =3D 0; - goto invalid; - } - else if ( aExp < 0x3FF ) { - if (aExp || aSig) { - status->float_exception_flags |=3D float_flag_inexact; - } - return 0; - } - aSig |=3D LIT64( 0x0010000000000000 ); - shiftCount =3D 0x433 - aExp; - savedASig =3D aSig; - aSig >>=3D shiftCount; - z =3D aSig; - if ( aSign ) z =3D - z; - if ( ( z < 0 ) ^ aSign ) { - invalid: - float_raise(float_flag_invalid, status); - return aSign ? (int32_t) 0x80000000 : 0x7FFFFFFF; - } - if ( ( aSig<float_exception_flags |=3D float_flag_inexact; - } - return z; - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the double-precision floating-point val= ue -| `a' to the 16-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. -| If `a' is a NaN, the largest positive integer is returned. Otherwise, if -| the conversion overflows, the largest integer with the same sign as `a' = is -| returned. -*-------------------------------------------------------------------------= ---*/ - -int16_t float64_to_int16_round_to_zero(float64 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint64_t aSig, savedASig; - int32_t z; - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - if ( 0x40E < aExp ) { - if ( ( aExp =3D=3D 0x7FF ) && aSig ) { - aSign =3D 0; - } - goto invalid; - } - else if ( aExp < 0x3FF ) { - if ( aExp || aSig ) { - status->float_exception_flags |=3D float_flag_inexact; - } - return 0; - } - aSig |=3D LIT64( 0x0010000000000000 ); - shiftCount =3D 0x433 - aExp; - savedASig =3D aSig; - aSig >>=3D shiftCount; - z =3D aSig; - if ( aSign ) { - z =3D - z; - } - if ( ( (int16_t)z < 0 ) ^ aSign ) { - invalid: - float_raise(float_flag_invalid, status); - return aSign ? (int32_t) 0xffff8000 : 0x7FFF; - } - if ( ( aSig<float_exception_flags |=3D float_flag_inexact; - } - return z; -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the double-precision floating-point val= ue -| `a' to the 64-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. Otherwise, if the conversion overflows, t= he -| largest integer with the same sign as `a' is returned. -*-------------------------------------------------------------------------= ---*/ - -int64_t float64_to_int64(float64 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint64_t aSig, aSigExtra; - a =3D float64_squash_input_denormal(a, status); - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - if ( aExp ) aSig |=3D LIT64( 0x0010000000000000 ); - shiftCount =3D 0x433 - aExp; - if ( shiftCount <=3D 0 ) { - if ( 0x43E < aExp ) { - float_raise(float_flag_invalid, status); - if ( ! aSign - || ( ( aExp =3D=3D 0x7FF ) - && ( aSig !=3D LIT64( 0x0010000000000000 ) ) ) - ) { - return LIT64( 0x7FFFFFFFFFFFFFFF ); - } - return (int64_t) LIT64( 0x8000000000000000 ); - } - aSigExtra =3D 0; - aSig <<=3D - shiftCount; - } - else { - shift64ExtraRightJamming( aSig, 0, shiftCount, &aSig, &aSigExtra ); - } - return roundAndPackInt64(aSign, aSig, aSigExtra, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the double-precision floating-point val= ue -| `a' to the 64-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. -| If `a' is a NaN, the largest positive integer is returned. Otherwise, if -| the conversion overflows, the largest integer with the same sign as `a' = is -| returned. -*-------------------------------------------------------------------------= ---*/ - -int64_t float64_to_int64_round_to_zero(float64 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint64_t aSig; - int64_t z; - a =3D float64_squash_input_denormal(a, status); - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - if ( aExp ) aSig |=3D LIT64( 0x0010000000000000 ); - shiftCount =3D aExp - 0x433; - if ( 0 <=3D shiftCount ) { - if ( 0x43E <=3D aExp ) { - if ( float64_val(a) !=3D LIT64( 0xC3E0000000000000 ) ) { - float_raise(float_flag_invalid, status); - if ( ! aSign - || ( ( aExp =3D=3D 0x7FF ) - && ( aSig !=3D LIT64( 0x0010000000000000 ) ) ) - ) { - return LIT64( 0x7FFFFFFFFFFFFFFF ); - } - } - return (int64_t) LIT64( 0x8000000000000000 ); - } - z =3D aSig<float_exception_flags |=3D float_flag_inexact; - } - return 0; - } - z =3D aSig>>( - shiftCount ); - if ( (uint64_t) ( aSig<<( shiftCount & 63 ) ) ) { - status->float_exception_flags |=3D float_flag_inexact; - } - } - if ( aSign ) z =3D - z; - return z; - -} =20 /*------------------------------------------------------------------------= ---- | Returns the result of converting the double-precision floating-point val= ue @@ -7056,252 +6726,7 @@ float64 uint32_to_float64(uint32_t a, float_status = *status) return int64_to_float64(a, status); } =20 -uint32_t float32_to_uint32(float32 a, float_status *status) -{ - int64_t v; - uint32_t res; - int old_exc_flags =3D get_float_exception_flags(status); =20 - v =3D float32_to_int64(a, status); - if (v < 0) { - res =3D 0; - } else if (v > 0xffffffff) { - res =3D 0xffffffff; - } else { - return v; - } - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -uint32_t float32_to_uint32_round_to_zero(float32 a, float_status *status) -{ - int64_t v; - uint32_t res; - int old_exc_flags =3D get_float_exception_flags(status); - - v =3D float32_to_int64_round_to_zero(a, status); - if (v < 0) { - res =3D 0; - } else if (v > 0xffffffff) { - res =3D 0xffffffff; - } else { - return v; - } - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -int16_t float32_to_int16(float32 a, float_status *status) -{ - int32_t v; - int16_t res; - int old_exc_flags =3D get_float_exception_flags(status); - - v =3D float32_to_int32(a, status); - if (v < -0x8000) { - res =3D -0x8000; - } else if (v > 0x7fff) { - res =3D 0x7fff; - } else { - return v; - } - - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -uint16_t float32_to_uint16(float32 a, float_status *status) -{ - int32_t v; - uint16_t res; - int old_exc_flags =3D get_float_exception_flags(status); - - v =3D float32_to_int32(a, status); - if (v < 0) { - res =3D 0; - } else if (v > 0xffff) { - res =3D 0xffff; - } else { - return v; - } - - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -uint16_t float32_to_uint16_round_to_zero(float32 a, float_status *status) -{ - int64_t v; - uint16_t res; - int old_exc_flags =3D get_float_exception_flags(status); - - v =3D float32_to_int64_round_to_zero(a, status); - if (v < 0) { - res =3D 0; - } else if (v > 0xffff) { - res =3D 0xffff; - } else { - return v; - } - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -uint32_t float64_to_uint32(float64 a, float_status *status) -{ - uint64_t v; - uint32_t res; - int old_exc_flags =3D get_float_exception_flags(status); - - v =3D float64_to_uint64(a, status); - if (v > 0xffffffff) { - res =3D 0xffffffff; - } else { - return v; - } - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -uint32_t float64_to_uint32_round_to_zero(float64 a, float_status *status) -{ - uint64_t v; - uint32_t res; - int old_exc_flags =3D get_float_exception_flags(status); - - v =3D float64_to_uint64_round_to_zero(a, status); - if (v > 0xffffffff) { - res =3D 0xffffffff; - } else { - return v; - } - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -int16_t float64_to_int16(float64 a, float_status *status) -{ - int64_t v; - int16_t res; - int old_exc_flags =3D get_float_exception_flags(status); - - v =3D float64_to_int32(a, status); - if (v < -0x8000) { - res =3D -0x8000; - } else if (v > 0x7fff) { - res =3D 0x7fff; - } else { - return v; - } - - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -uint16_t float64_to_uint16(float64 a, float_status *status) -{ - int64_t v; - uint16_t res; - int old_exc_flags =3D get_float_exception_flags(status); - - v =3D float64_to_int32(a, status); - if (v < 0) { - res =3D 0; - } else if (v > 0xffff) { - res =3D 0xffff; - } else { - return v; - } - - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -uint16_t float64_to_uint16_round_to_zero(float64 a, float_status *status) -{ - int64_t v; - uint16_t res; - int old_exc_flags =3D get_float_exception_flags(status); - - v =3D float64_to_int64_round_to_zero(a, status); - if (v < 0) { - res =3D 0; - } else if (v > 0xffff) { - res =3D 0xffff; - } else { - return v; - } - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the double-precision floating-point val= ue -| `a' to the 64-bit unsigned integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. If the conversion overflows, the -| largest unsigned integer is returned. If 'a' is negative, the value is -| rounded and zero is returned; negative values that do not round to zero -| will raise the inexact exception. -*-------------------------------------------------------------------------= ---*/ - -uint64_t float64_to_uint64(float64 a, float_status *status) -{ - flag aSign; - int aExp; - int shiftCount; - uint64_t aSig, aSigExtra; - a =3D float64_squash_input_denormal(a, status); - - aSig =3D extractFloat64Frac(a); - aExp =3D extractFloat64Exp(a); - aSign =3D extractFloat64Sign(a); - if (aSign && (aExp > 1022)) { - float_raise(float_flag_invalid, status); - if (float64_is_any_nan(a)) { - return LIT64(0xFFFFFFFFFFFFFFFF); - } else { - return 0; - } - } - if (aExp) { - aSig |=3D LIT64(0x0010000000000000); - } - shiftCount =3D 0x433 - aExp; - if (shiftCount <=3D 0) { - if (0x43E < aExp) { - float_raise(float_flag_invalid, status); - return LIT64(0xFFFFFFFFFFFFFFFF); - } - aSigExtra =3D 0; - aSig <<=3D -shiftCount; - } else { - shift64ExtraRightJamming(aSig, 0, shiftCount, &aSig, &aSigExtra); - } - return roundAndPackUint64(aSign, aSig, aSigExtra, status); -} - -uint64_t float64_to_uint64_round_to_zero(float64 a, float_status *status) -{ - signed char current_rounding_mode =3D status->float_rounding_mode; - set_float_rounding_mode(float_round_to_zero, status); - uint64_t v =3D float64_to_uint64(a, status); - set_float_rounding_mode(current_rounding_mode, status); - return v; -} =20 #define COMPARE(s, nan_exp) = \ static inline int float ## s ## _compare_internal(float ## s a, float ## s= b,\ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 4650758c23..ec1e701c26 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -232,6 +232,19 @@ float16 float32_to_float16(float32, flag, float_status= *status); float32 float16_to_float32(float16, flag, float_status *status); float16 float64_to_float16(float64 a, flag ieee, float_status *status); float64 float16_to_float64(float16 a, flag ieee, float_status *status); +int16_t float16_to_int16(float16, float_status *status); +uint16_t float16_to_uint16(float16 a, float_status *status); +int16_t float16_to_int16_round_to_zero(float16, float_status *status); +uint16_t float16_to_uint16_round_to_zero(float16 a, float_status *status); +int32_t float16_to_int32(float16, float_status *status); +uint32_t float16_to_uint32(float16 a, float_status *status); +int32_t float16_to_int32_round_to_zero(float16, float_status *status); +uint32_t float16_to_uint32_round_to_zero(float16 a, float_status *status); +int64_t float16_to_int64(float16, float_status *status); +uint64_t float16_to_uint64(float16 a, float_status *status); +int64_t float16_to_int64_round_to_zero(float16, float_status *status); +uint64_t float16_to_uint64_round_to_zero(float16 a, float_status *status); +float16 int16_to_float16(int16_t a, float_status *status); =20 /*------------------------------------------------------------------------= ---- | Software half-precision operations. --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v4 18/22] fpu/softfloat: re-factor int/uint to float X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 These are considerably simpler as the lower order integers can just use the higher order conversion function. As the decomposed fractional part is a full 64 bit rounding and inexact handling comes from the pack functions. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - explicit setting of r.sign v3 - renaming of functions/structs --- fpu/softfloat.c | 322 ++++++++++++++++++++++++--------------------= ---- include/fpu/softfloat.h | 30 ++--- 2 files changed, 172 insertions(+), 180 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 216d60df6e..9f9f101d35 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1501,6 +1501,169 @@ FLOAT_TO_UINT(64, 64) =20 #undef FLOAT_TO_UINT =20 +/* + * Integer to float conversions + * + * Returns the result of converting the two's complement integer `a' + * to the floating-point format. The conversion is performed according + * to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. + */ + +static FloatParts int_to_float(int64_t a, float_status *status) +{ + FloatParts r; + if (a =3D=3D 0) { + r.cls =3D float_class_zero; + r.sign =3D false; + } else if (a =3D=3D (1ULL << 63)) { + r.cls =3D float_class_normal; + r.sign =3D true; + r.frac =3D DECOMPOSED_IMPLICIT_BIT; + r.exp =3D 63; + } else { + uint64_t f; + if (a < 0) { + f =3D -a; + r.sign =3D true; + } else { + f =3D a; + r.sign =3D false; + } + int shift =3D clz64(f) - 1; + r.cls =3D float_class_normal; + r.exp =3D (DECOMPOSED_BINARY_POINT - shift); + r.frac =3D f << shift; + } + + return r; +} + +float16 int64_to_float16(int64_t a, float_status *status) +{ + FloatParts pa =3D int_to_float(a, status); + return float16_round_pack_canonical(pa, status); +} + +float16 int32_to_float16(int32_t a, float_status *status) +{ + return int64_to_float16(a, status); +} + +float16 int16_to_float16(int16_t a, float_status *status) +{ + return int64_to_float16(a, status); +} + +float32 int64_to_float32(int64_t a, float_status *status) +{ + FloatParts pa =3D int_to_float(a, status); + return float32_round_pack_canonical(pa, status); +} + +float32 int32_to_float32(int32_t a, float_status *status) +{ + return int64_to_float32(a, status); +} + +float32 int16_to_float32(int16_t a, float_status *status) +{ + return int64_to_float32(a, status); +} + +float64 int64_to_float64(int64_t a, float_status *status) +{ + FloatParts pa =3D int_to_float(a, status); + return float64_round_pack_canonical(pa, status); +} + +float64 int32_to_float64(int32_t a, float_status *status) +{ + return int64_to_float64(a, status); +} + +float64 int16_to_float64(int16_t a, float_status *status) +{ + return int64_to_float64(a, status); +} + + +/* + * Unsigned Integer to float conversions + * + * Returns the result of converting the unsigned integer `a' to the + * floating-point format. The conversion is performed according to the + * IEC/IEEE Standard for Binary Floating-Point Arithmetic. + */ + +static FloatParts uint_to_float(uint64_t a, float_status *status) +{ + FloatParts r =3D { .sign =3D false}; + + if (a =3D=3D 0) { + r.cls =3D float_class_zero; + } else { + int spare_bits =3D clz64(a) - 1; + r.cls =3D float_class_normal; + r.exp =3D DECOMPOSED_BINARY_POINT - spare_bits; + if (spare_bits < 0) { + shift64RightJamming(a, -spare_bits, &a); + r.frac =3D a; + } else { + r.frac =3D a << spare_bits; + } + } + + return r; +} + +float16 uint64_to_float16(uint64_t a, float_status *status) +{ + FloatParts pa =3D uint_to_float(a, status); + return float16_round_pack_canonical(pa, status); +} + +float16 uint32_to_float16(uint32_t a, float_status *status) +{ + return uint64_to_float16(a, status); +} + +float16 uint16_to_float16(uint16_t a, float_status *status) +{ + return uint64_to_float16(a, status); +} + +float32 uint64_to_float32(uint64_t a, float_status *status) +{ + FloatParts pa =3D uint_to_float(a, status); + return float32_round_pack_canonical(pa, status); +} + +float32 uint32_to_float32(uint32_t a, float_status *status) +{ + return uint64_to_float32(a, status); +} + +float32 uint16_to_float32(uint16_t a, float_status *status) +{ + return uint64_to_float32(a, status); +} + +float64 uint64_to_float64(uint64_t a, float_status *status) +{ + FloatParts pa =3D uint_to_float(a, status); + return float64_round_pack_canonical(pa, status); +} + +float64 uint32_to_float64(uint32_t a, float_status *status) +{ + return uint64_to_float64(a, status); +} + +float64 uint16_to_float64(uint16_t a, float_status *status) +{ + return uint64_to_float64(a, status); +} + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the @@ -2592,43 +2755,6 @@ static float128 normalizeRoundAndPackFloat128(flag z= Sign, int32_t zExp, =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the 32-bit two's complement integer `a' -| to the single-precision floating-point format. The conversion is perfor= med -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 int32_to_float32(int32_t a, float_status *status) -{ - flag zSign; - - if ( a =3D=3D 0 ) return float32_zero; - if ( a =3D=3D (int32_t) 0x80000000 ) return packFloat32( 1, 0x9E, 0 ); - zSign =3D ( a < 0 ); - return normalizeRoundAndPackFloat32(zSign, 0x9C, zSign ? -a : a, statu= s); -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the 32-bit two's complement integer `a' -| to the double-precision floating-point format. The conversion is perfor= med -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 int32_to_float64(int32_t a, float_status *status) -{ - flag zSign; - uint32_t absA; - int8_t shiftCount; - uint64_t zSig; - - if ( a =3D=3D 0 ) return float64_zero; - zSign =3D ( a < 0 ); - absA =3D zSign ? - a : a; - shiftCount =3D countLeadingZeros32( absA ) + 21; - zSig =3D absA; - return packFloat64( zSign, 0x432 - shiftCount, zSig<=3D 0) { - return packFloat32(0, 0x95 - shiftcount, a << shiftcount); - } - /* Otherwise we need to do a round-and-pack. roundAndPackFloat32() - * expects the binary point between bits 30 and 29, hence the + 7. - */ - shiftcount +=3D 7; - if (shiftcount < 0) { - shift64RightJamming(a, -shiftcount, &a); - } else { - a <<=3D shiftcount; - } - - return roundAndPackFloat32(0, 0x9c - shiftcount, a, status); -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the 64-bit unsigned integer `a' -| to the double-precision floating-point format. The conversion is perfor= med -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 uint64_to_float64(uint64_t a, float_status *status) -{ - int exp =3D 0x43C; - int shiftcount; - - if (a =3D=3D 0) { - return float64_zero; - } - - shiftcount =3D countLeadingZeros64(a) - 1; - if (shiftcount < 0) { - shift64RightJamming(a, -shiftcount, &a); - } else { - a <<=3D shiftcount; - } - return roundAndPackFloat64(0, exp - shiftcount, a, status); -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the 64-bit unsigned integer `a' | to the quadruple-precision floating-point format. The conversion is per= formed @@ -6715,19 +6732,6 @@ int float128_unordered_quiet(float128 a, float128 b,= float_status *status) return 0; } =20 -/* misc functions */ -float32 uint32_to_float32(uint32_t a, float_status *status) -{ - return int64_to_float32(a, status); -} - -float64 uint32_to_float64(uint32_t a, float_status *status) -{ - return int64_to_float64(a, status); -} - - - #define COMPARE(s, nan_exp) = \ static inline int float ## s ## _compare_internal(float ## s a, float ## s= b,\ int is_quiet, float_status *status) = \ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index ec1e701c26..3e6fdd756a 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -190,9 +190,13 @@ enum { /*------------------------------------------------------------------------= ---- | Software IEC/IEEE integer-to-floating-point conversion routines. *-------------------------------------------------------------------------= ---*/ +float32 int16_to_float32(int16_t, float_status *status); float32 int32_to_float32(int32_t, float_status *status); +float64 int16_to_float64(int16_t, float_status *status); float64 int32_to_float64(int32_t, float_status *status); +float32 uint16_to_float32(uint16_t, float_status *status); float32 uint32_to_float32(uint32_t, float_status *status); +float64 uint16_to_float64(uint16_t, float_status *status); float64 uint32_to_float64(uint32_t, float_status *status); floatx80 int32_to_floatx80(int32_t, float_status *status); float128 int32_to_float128(int32_t, float_status *status); @@ -204,27 +208,6 @@ float32 uint64_to_float32(uint64_t, float_status *stat= us); float64 uint64_to_float64(uint64_t, float_status *status); float128 uint64_to_float128(uint64_t, float_status *status); =20 -/* We provide the int16 versions for symmetry of API with float-to-int */ -static inline float32 int16_to_float32(int16_t v, float_status *status) -{ - return int32_to_float32(v, status); -} - -static inline float32 uint16_to_float32(uint16_t v, float_status *status) -{ - return uint32_to_float32(v, status); -} - -static inline float64 int16_to_float64(int16_t v, float_status *status) -{ - return int32_to_float64(v, status); -} - -static inline float64 uint16_to_float64(uint16_t v, float_status *status) -{ - return uint32_to_float64(v, status); -} - /*------------------------------------------------------------------------= ---- | Software half-precision conversion routines. *-------------------------------------------------------------------------= ---*/ @@ -245,6 +228,11 @@ uint64_t float16_to_uint64(float16 a, float_status *st= atus); int64_t float16_to_int64_round_to_zero(float16, float_status *status); uint64_t float16_to_uint64_round_to_zero(float16 a, float_status *status); float16 int16_to_float16(int16_t a, float_status *status); +float16 int32_to_float16(int32_t a, float_status *status); +float16 int64_to_float16(int64_t a, float_status *status); +float16 uint16_to_float16(uint16_t a, float_status *status); +float16 uint32_to_float16(uint32_t a, float_status *status); +float16 uint64_to_float16(uint64_t a, float_status *status); =20 /*------------------------------------------------------------------------= ---- | Software half-precision operations. --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517936251454806.1246636613764; Tue, 6 Feb 2018 08:57:31 -0800 (PST) Received: from localhost ([::1]:37836 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej6Yk-0000N2-K2 for importer@patchew.org; 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v4 19/22] fpu/softfloat: re-factor scalbn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This is one of the simpler manipulations you could make to a floating point number. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - fix renames v4 - handle NaNs with return_nan - use unlikely(is_nan) --- fpu/softfloat.c | 106 +++++++++++++++-----------------------------= ---- include/fpu/softfloat.h | 1 + 2 files changed, 34 insertions(+), 73 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 9f9f101d35..558d37ecf9 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1664,6 +1664,39 @@ float64 uint16_to_float64(uint16_t a, float_status *= status) return uint64_to_float64(a, status); } =20 +/* Multiply A by 2 raised to the power N. */ +static FloatParts scalbn_decomposed(FloatParts a, int n, float_status *s) +{ + if (unlikely(is_nan(a.cls))) { + return return_nan(a, s); + } + if (a.cls =3D=3D float_class_normal) { + a.exp +=3D n; + } + return a; +} + +float16 float16_scalbn(float16 a, int n, float_status *status) +{ + FloatParts pa =3D float16_unpack_canonical(a, status); + FloatParts pr =3D scalbn_decomposed(pa, n, status); + return float16_round_pack_canonical(pr, status); +} + +float32 float32_scalbn(float32 a, int n, float_status *status) +{ + FloatParts pa =3D float32_unpack_canonical(a, status); + FloatParts pr =3D scalbn_decomposed(pa, n, status); + return float32_round_pack_canonical(pr, status); +} + +float64 float64_scalbn(float64 a, int n, float_status *status) +{ + FloatParts pa =3D float64_unpack_canonical(a, status); + FloatParts pr =3D scalbn_decomposed(pa, n, status); + return float64_round_pack_canonical(pr, status); +} + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the @@ -6987,79 +7020,6 @@ MINMAX(32) MINMAX(64) =20 =20 -/* Multiply A by 2 raised to the power N. */ -float32 float32_scalbn(float32 a, int n, float_status *status) -{ - flag aSign; - int16_t aExp; - uint32_t aSig; - - a =3D float32_squash_input_denormal(a, status); - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - - if ( aExp =3D=3D 0xFF ) { - if ( aSig ) { - return propagateFloat32NaN(a, a, status); - } - return a; - } - if (aExp !=3D 0) { - aSig |=3D 0x00800000; - } else if (aSig =3D=3D 0) { - return a; - } else { - aExp++; - } - - if (n > 0x200) { - n =3D 0x200; - } else if (n < -0x200) { - n =3D -0x200; - } - - aExp +=3D n - 1; - aSig <<=3D 7; - return normalizeRoundAndPackFloat32(aSign, aExp, aSig, status); -} - -float64 float64_scalbn(float64 a, int n, float_status *status) -{ - flag aSign; - int16_t aExp; - uint64_t aSig; - - a =3D float64_squash_input_denormal(a, status); - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - - if ( aExp =3D=3D 0x7FF ) { - if ( aSig ) { - return propagateFloat64NaN(a, a, status); - } - return a; - } - if (aExp !=3D 0) { - aSig |=3D LIT64( 0x0010000000000000 ); - } else if (aSig =3D=3D 0) { - return a; - } else { - aExp++; - } - - if (n > 0x1000) { - n =3D 0x1000; - } else if (n < -0x1000) { - n =3D -0x1000; - } - - aExp +=3D n - 1; - aSig <<=3D 10; - return normalizeRoundAndPackFloat64(aSign, aExp, aSig, status); -} - floatx80 floatx80_scalbn(floatx80 a, int n, float_status *status) { flag aSign; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 3e6fdd756a..52621e0b79 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -244,6 +244,7 @@ float16 float16_sub(float16, float16, float_status *sta= tus); float16 float16_mul(float16, float16, float_status *status); float16 float16_muladd(float16, float16, float16, int, float_status *statu= s); float16 float16_div(float16, float16, float_status *status); +float16 float16_scalbn(float16, int, float_status *status); =20 int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v4 20/22] fpu/softfloat: re-factor minmax X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Let's do the same re-factor treatment for minmax functions. I still use the MACRO trick to expand but now all the checking code is common. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - minor indentation fix v3 - fix merge conflicts from dropping MINMAX patch - fix naming of structs v4 - use is_nan/is_snan - pick_nan_parts->pick_nan - minmax_decomposed->minmax_floats --- fpu/softfloat.c | 227 +++++++++++++++++++++++++-------------------= ---- include/fpu/softfloat.h | 6 ++ 2 files changed, 126 insertions(+), 107 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 558d37ecf9..cb889a7a84 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1664,6 +1664,126 @@ float64 uint16_to_float64(uint16_t a, float_status = *status) return uint64_to_float64(a, status); } =20 +/* Float Min/Max */ +/* min() and max() functions. These can't be implemented as + * 'compare and pick one input' because that would mishandle + * NaNs and +0 vs -0. + * + * minnum() and maxnum() functions. These are similar to the min() + * and max() functions but if one of the arguments is a QNaN and + * the other is numerical then the numerical argument is returned. + * SNaNs will get quietened before being returned. + * minnum() and maxnum correspond to the IEEE 754-2008 minNum() + * and maxNum() operations. min() and max() are the typical min/max + * semantics provided by many CPUs which predate that specification. + * + * minnummag() and maxnummag() functions correspond to minNumMag() + * and minNumMag() from the IEEE-754 2008. + */ +static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin, + bool ieee, bool ismag, float_status *s) +{ + if (unlikely(is_nan(a.cls) || is_nan(b.cls))) { + if (ieee) { + /* Takes two floating-point values `a' and `b', one of + * which is a NaN, and returns the appropriate NaN + * result. If either `a' or `b' is a signaling NaN, + * the invalid exception is raised. + */ + if (is_snan(a.cls) || is_snan(b.cls)) { + return pick_nan(a, b, s); + } else if (is_nan(a.cls) && !is_nan(b.cls)) { + return b; + } else if (is_nan(b.cls) && !is_nan(a.cls)) { + return a; + } + } + return pick_nan(a, b, s); + } else { + int a_exp, b_exp; + bool a_sign, b_sign; + + switch (a.cls) { + case float_class_normal: + a_exp =3D a.exp; + break; + case float_class_inf: + a_exp =3D INT_MAX; + break; + case float_class_zero: + a_exp =3D INT_MIN; + break; + default: + g_assert_not_reached(); + break; + } + switch (b.cls) { + case float_class_normal: + b_exp =3D b.exp; + break; + case float_class_inf: + b_exp =3D INT_MAX; + break; + case float_class_zero: + b_exp =3D INT_MIN; + break; + default: + g_assert_not_reached(); + break; + } + + a_sign =3D a.sign; + b_sign =3D b.sign; + if (ismag) { + a_sign =3D b_sign =3D 0; + } + + if (a_sign =3D=3D b_sign) { + bool a_less =3D a_exp < b_exp; + if (a_exp =3D=3D b_exp) { + a_less =3D a.frac < b.frac; + } + return a_sign ^ a_less ^ ismin ? b : a; + } else { + return a_sign ^ ismin ? b : a; + } + } +} + +#define MINMAX(sz, name, ismin, isiee, ismag) \ +float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ + float_status *s) \ +{ \ + FloatParts pa =3D float ## sz ## _unpack_canonical(a, s); \ + FloatParts pb =3D float ## sz ## _unpack_canonical(b, s); \ + FloatParts pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); \ + \ + return float ## sz ## _round_pack_canonical(pr, s); \ +} + +MINMAX(16, min, true, false, false) +MINMAX(16, minnum, true, true, false) +MINMAX(16, minnummag, true, true, true) +MINMAX(16, max, false, false, false) +MINMAX(16, maxnum, false, true, false) +MINMAX(16, maxnummag, false, true, true) + +MINMAX(32, min, true, false, false) +MINMAX(32, minnum, true, true, false) +MINMAX(32, minnummag, true, true, true) +MINMAX(32, max, false, false, false) +MINMAX(32, maxnum, false, true, false) +MINMAX(32, maxnummag, false, true, true) + +MINMAX(64, min, true, false, false) +MINMAX(64, minnum, true, true, false) +MINMAX(64, minnummag, true, true, true) +MINMAX(64, max, false, false, false) +MINMAX(64, maxnum, false, true, false) +MINMAX(64, maxnummag, false, true, true) + +#undef MINMAX + /* Multiply A by 2 raised to the power N. */ static FloatParts scalbn_decomposed(FloatParts a, int n, float_status *s) { @@ -6913,113 +7033,6 @@ int float128_compare_quiet(float128 a, float128 b, = float_status *status) return float128_compare_internal(a, b, 1, status); } =20 -/* min() and max() functions. These can't be implemented as - * 'compare and pick one input' because that would mishandle - * NaNs and +0 vs -0. - * - * minnum() and maxnum() functions. These are similar to the min() - * and max() functions but if one of the arguments is a QNaN and - * the other is numerical then the numerical argument is returned. - * minnum() and maxnum correspond to the IEEE 754-2008 minNum() - * and maxNum() operations. min() and max() are the typical min/max - * semantics provided by many CPUs which predate that specification. - * - * minnummag() and maxnummag() functions correspond to minNumMag() - * and minNumMag() from the IEEE-754 2008. - */ -#define MINMAX(s) \ -static inline float ## s float ## s ## _minmax(float ## s a, float ## s b,= \ - int ismin, int isieee, \ - int ismag, \ - float_status *status) \ -{ \ - flag aSign, bSign; \ - uint ## s ## _t av, bv, aav, abv; \ - a =3D float ## s ## _squash_input_denormal(a, status); \ - b =3D float ## s ## _squash_input_denormal(b, status); \ - if (float ## s ## _is_any_nan(a) || \ - float ## s ## _is_any_nan(b)) { \ - if (isieee) { \ - if (float ## s ## _is_quiet_nan(a, status) && \ - !float ## s ##_is_any_nan(b)) { \ - return b; \ - } else if (float ## s ## _is_quiet_nan(b, status) && \ - !float ## s ## _is_any_nan(a)) { \ - return a; \ - } \ - } \ - return propagateFloat ## s ## NaN(a, b, status); \ - } \ - aSign =3D extractFloat ## s ## Sign(a); \ - bSign =3D extractFloat ## s ## Sign(b); \ - av =3D float ## s ## _val(a); \ - bv =3D float ## s ## _val(b); \ - if (ismag) { \ - aav =3D float ## s ## _abs(av); \ - abv =3D float ## s ## _abs(bv); \ - if (aav !=3D abv) { \ - if (ismin) { \ - return (aav < abv) ? a : b; \ - } else { \ - return (aav < abv) ? b : a; \ - } \ - } \ - } \ - if (aSign !=3D bSign) { \ - if (ismin) { \ - return aSign ? a : b; \ - } else { \ - return aSign ? b : a; \ - } \ - } else { \ - if (ismin) { \ - return (aSign ^ (av < bv)) ? a : b; \ - } else { \ - return (aSign ^ (av < bv)) ? b : a; \ - } \ - } \ -} \ - \ -float ## s float ## s ## _min(float ## s a, float ## s b, \ - float_status *status) \ -{ \ - return float ## s ## _minmax(a, b, 1, 0, 0, status); \ -} \ - \ -float ## s float ## s ## _max(float ## s a, float ## s b, \ - float_status *status) \ -{ \ - return float ## s ## _minmax(a, b, 0, 0, 0, status); \ -} \ - \ -float ## s float ## s ## _minnum(float ## s a, float ## s b, \ - float_status *status) \ -{ \ - return float ## s ## _minmax(a, b, 1, 1, 0, status); \ -} \ - \ -float ## s float ## s ## _maxnum(float ## s a, float ## s b, \ - float_status *status) \ -{ \ - return float ## s ## _minmax(a, b, 0, 1, 0, status); \ -} \ - \ -float ## s float ## s ## _minnummag(float ## s a, float ## s b, \ - float_status *status) \ -{ \ - return float ## s ## _minmax(a, b, 1, 1, 1, status); \ -} \ - \ -float ## s float ## s ## _maxnummag(float ## s a, float ## s b, \ - float_status *status) \ -{ \ - return float ## s ## _minmax(a, b, 0, 1, 1, status); \ -} - -MINMAX(32) -MINMAX(64) - - floatx80 floatx80_scalbn(floatx80 a, int n, float_status *status) { flag aSign; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 52621e0b79..35df225a55 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -245,6 +245,12 @@ float16 float16_mul(float16, float16, float_status *st= atus); float16 float16_muladd(float16, float16, float16, int, float_status *statu= s); float16 float16_div(float16, float16, float_status *status); float16 float16_scalbn(float16, int, float_status *status); +float16 float16_min(float16, float16, float_status *status); +float16 float16_max(float16, float16, float_status *status); +float16 float16_minnum(float16, float16, float_status *status); +float16 float16_maxnum(float16, float16, float_status *status); +float16 float16_minnummag(float16, float16, float_status *status); +float16 float16_maxnummag(float16, float16, float_status *status); =20 int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); --=20 2.15.1 From nobody Sun Apr 28 15:40:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PATCH v4 21/22] fpu/softfloat: re-factor compare X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The compare function was already expanded from a macro. I keep the macro expansion but move most of the logic into a compare_decomposed. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - minor re-factor for better inf handling v3 - fix renaming of structs/functions v4 - use is_nan --- fpu/softfloat.c | 134 +++++++++++++++++++++++++++++---------------= ---- include/fpu/softfloat.h | 2 + 2 files changed, 82 insertions(+), 54 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index cb889a7a84..8fc1c2a8d9 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1784,6 +1784,86 @@ MINMAX(64, maxnummag, false, true, true) =20 #undef MINMAX =20 +/* Floating point compare */ +static int compare_floats(FloatParts a, FloatParts b, bool is_quiet, + float_status *s) +{ + if (is_nan(a.cls) || is_nan(b.cls)) { + if (!is_quiet || + a.cls =3D=3D float_class_snan || + b.cls =3D=3D float_class_snan) { + s->float_exception_flags |=3D float_flag_invalid; + } + return float_relation_unordered; + } + + if (a.cls =3D=3D float_class_zero) { + if (b.cls =3D=3D float_class_zero) { + return float_relation_equal; + } + return b.sign ? float_relation_greater : float_relation_less; + } else if (b.cls =3D=3D float_class_zero) { + return a.sign ? float_relation_less : float_relation_greater; + } + + /* The only really important thing about infinity is its sign. If + * both are infinities the sign marks the smallest of the two. + */ + if (a.cls =3D=3D float_class_inf) { + if ((b.cls =3D=3D float_class_inf) && (a.sign =3D=3D b.sign)) { + return float_relation_equal; + } + return a.sign ? float_relation_less : float_relation_greater; + } else if (b.cls =3D=3D float_class_inf) { + return b.sign ? float_relation_greater : float_relation_less; + } + + if (a.sign !=3D b.sign) { + return a.sign ? float_relation_less : float_relation_greater; + } + + if (a.exp =3D=3D b.exp) { + if (a.frac =3D=3D b.frac) { + return float_relation_equal; + } + if (a.sign) { + return a.frac > b.frac ? + float_relation_less : float_relation_greater; + } else { + return a.frac > b.frac ? + float_relation_greater : float_relation_less; + } + } else { + if (a.sign) { + return a.exp > b.exp ? float_relation_less : float_relation_gr= eater; + } else { + return a.exp > b.exp ? float_relation_greater : float_relation= _less; + } + } +} + +#define COMPARE(sz) \ +int float ## sz ## _compare(float ## sz a, float ## sz b, \ + float_status *s) \ +{ \ + FloatParts pa =3D float ## sz ## _unpack_canonical(a, s); \ + FloatParts pb =3D float ## sz ## _unpack_canonical(b, s); \ + return compare_floats(pa, pb, false, s); \ +} \ +int float ## sz ## _compare_quiet(float ## sz a, float ## sz b, \ + float_status *s) \ +{ \ + FloatParts pa =3D float ## sz ## _unpack_canonical(a, s); \ + FloatParts pb =3D float ## sz ## _unpack_canonical(b, s); \ + return compare_floats(pa, pb, true, s); \ +} + +COMPARE(16) +COMPARE(32) +COMPARE(64) + +#undef COMPARE + /* Multiply A by 2 raised to the power N. */ static FloatParts scalbn_decomposed(FloatParts a, int n, float_status *s) { @@ -6885,60 +6965,6 @@ int float128_unordered_quiet(float128 a, float128 b,= float_status *status) return 0; } =20 -#define COMPARE(s, nan_exp) = \ -static inline int float ## s ## _compare_internal(float ## s a, float ## s= b,\ - int is_quiet, float_status *status) = \ -{ = \ - flag aSign, bSign; = \ - uint ## s ## _t av, bv; = \ - a =3D float ## s ## _squash_input_denormal(a, status); = \ - b =3D float ## s ## _squash_input_denormal(b, status); = \ - = \ - if (( ( extractFloat ## s ## Exp( a ) =3D=3D nan_exp ) && = \ - extractFloat ## s ## Frac( a ) ) || = \ - ( ( extractFloat ## s ## Exp( b ) =3D=3D nan_exp ) && = \ - extractFloat ## s ## Frac( b ) )) { = \ - if (!is_quiet || = \ - float ## s ## _is_signaling_nan(a, status) || = \ - float ## s ## _is_signaling_nan(b, status)) { \ - float_raise(float_flag_invalid, status); = \ - } = \ - return float_relation_unordered; = \ - } = \ - aSign =3D extractFloat ## s ## Sign( a ); = \ - bSign =3D extractFloat ## s ## Sign( b ); = \ - av =3D float ## s ## _val(a); = \ - bv =3D float ## s ## _val(b); = \ - if ( aSign !=3D bSign ) { = \ - if ( (uint ## s ## _t) ( ( av | bv )<<1 ) =3D=3D 0 ) { = \ - /* zero case */ = \ - return float_relation_equal; = \ - } else { = \ - return 1 - (2 * aSign); = \ - } = \ - } else { = \ - if (av =3D=3D bv) { = \ - return float_relation_equal; = \ - } else { = \ - return 1 - 2 * (aSign ^ ( av < bv )); = \ - } = \ - } = \ -} = \ - = \ -int float ## s ## _compare(float ## s a, float ## s b, float_status *statu= s) \ -{ = \ - return float ## s ## _compare_internal(a, b, 0, status); = \ -} = \ - = \ -int float ## s ## _compare_quiet(float ## s a, float ## s b, = \ - float_status *status) = \ -{ = \ - return float ## s ## _compare_internal(a, b, 1, status); = \ -} - -COMPARE(32, 0xff) -COMPARE(64, 0x7ff) - static inline int floatx80_compare_internal(floatx80 a, floatx80 b, int is_quiet, float_status *st= atus) { diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 35df225a55..cebe37b716 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -251,6 +251,8 @@ float16 float16_minnum(float16, float16, float_status *= status); float16 float16_maxnum(float16, float16, float_status *status); float16 float16_minnummag(float16, float16, float_status *status); float16 float16_maxnummag(float16, float16, float_status *status); +int float16_compare(float16, float16, float_status *status); +int float16_compare_quiet(float16, float16, float_status *status); =20 int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); 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Tue, 06 Feb 2018 08:48:34 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org, peter.maydell@linaro.org, laurent@vivier.eu, bharata@linux.vnet.ibm.com, andrew@andrewdutcher.com Date: Tue, 6 Feb 2018 16:48:15 +0000 Message-Id: <20180206164815.10084-23-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180206164815.10084-1-alex.bennee@linaro.org> References: <20180206164815.10084-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::230 Subject: [Qemu-devel] [PATCH v4 22/22] fpu/softfloat: re-factor sqrt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This is a little bit of a departure from softfloat's original approach as we skip the estimate step in favour of a straight iteration. Suggested-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- v3 - added to series - fixed renames of structs v4 - fix up comments - use is_nan - use return_nan instead of pick_nan(a,a) --- fpu/softfloat.c | 201 ++++++++++++++++++++++----------------------= ---- include/fpu/softfloat.h | 1 + 2 files changed, 91 insertions(+), 111 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8fc1c2a8d9..80301d8e04 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1897,6 +1897,96 @@ float64 float64_scalbn(float64 a, int n, float_statu= s *status) return float64_round_pack_canonical(pr, status); } =20 +/* + * Square Root + * + * The old softfloat code did an approximation step before zeroing in + * on the final result. However for simpleness we just compute the + * square root by iterating down from the implicit bit to enough extra + * bits to ensure we get a correctly rounded result. + */ + +static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt= *p) +{ + uint64_t a_frac, r_frac, s_frac; + int bit, last_bit; + + if (is_nan(a.cls)) { + return return_nan(a, s); + } + if (a.cls =3D=3D float_class_zero) { + return a; /* sqrt(+-0) =3D +-0 */ + } + if (a.sign) { + s->float_exception_flags |=3D float_flag_invalid; + a.cls =3D float_class_dnan; + return a; + } + if (a.cls =3D=3D float_class_inf) { + return a; /* sqrt(+inf) =3D +inf */ + } + + assert(a.cls =3D=3D float_class_normal); + + /* We need two overflow bits at the top. Adding room for that is + a right shift. If the exponent is odd, we can discard the low + bit by multiplying the fraction by 2; that's a left shift. + Combine those and we shift right if the exponent is even. */ + a_frac =3D a.frac; + if (!(a.exp & 1)) { + a_frac >>=3D 1; + } + a.exp >>=3D 1; + + /* Bit-by-bit computation of sqrt. */ + r_frac =3D 0; + s_frac =3D 0; + + /* Iterate from implicit bit down to the 3 extra bits to compute a + * properly rounded result. Remember we've inserted one more bit + * at the top, so these positions are one less. */ + bit =3D DECOMPOSED_BINARY_POINT - 1; + last_bit =3D MAX(p->frac_shift - 4, 0); + do { + uint64_t q =3D 1ULL << bit; + uint64_t t_frac =3D s_frac + q; + if (t_frac <=3D a_frac) { + s_frac =3D t_frac + q; + a_frac -=3D t_frac; + r_frac +=3D q; + } + a_frac <<=3D 1; + } while (--bit >=3D last_bit); + + /* Undo the right shift done above. If there is any remaining + fraction, the result is inexact. Set the sticky bit. */ + a.frac =3D (r_frac << 1) + (a_frac !=3D 0); + + return a; +} + +float16 float16_sqrt(float16 a, float_status *status) +{ + FloatParts pa =3D float16_unpack_canonical(a, status); + FloatParts pr =3D sqrt_float(pa, status, &float16_params); + return float16_round_pack_canonical(pr, status); +} + +float32 float32_sqrt(float32 a, float_status *status) +{ + FloatParts pa =3D float32_unpack_canonical(a, status); + FloatParts pr =3D sqrt_float(pa, status, &float32_params); + return float32_round_pack_canonical(pr, status); +} + +float64 float64_sqrt(float64 a, float_status *status) +{ + FloatParts pa =3D float64_unpack_canonical(a, status); + FloatParts pr =3D sqrt_float(pa, status, &float64_params); + return float64_round_pack_canonical(pr, status); +} + + /*------------------------------------------------------------------------= ---- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to = the @@ -3304,62 +3394,6 @@ float32 float32_rem(float32 a, float32 b, float_stat= us *status) } =20 =20 -/*------------------------------------------------------------------------= ---- -| Returns the square root of the single-precision floating-point value `a'. -| The operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_sqrt(float32 a, float_status *status) -{ - flag aSign; - int aExp, zExp; - uint32_t aSig, zSig; - uint64_t rem, term; - a =3D float32_squash_input_denormal(a, status); - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - if ( aExp =3D=3D 0xFF ) { - if (aSig) { - return propagateFloat32NaN(a, float32_zero, status); - } - if ( ! aSign ) return a; - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - if ( aSign ) { - if ( ( aExp | aSig ) =3D=3D 0 ) return a; - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return float32_zero; - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - zExp =3D ( ( aExp - 0x7F )>>1 ) + 0x7E; - aSig =3D ( aSig | 0x00800000 )<<8; - zSig =3D estimateSqrt32( aExp, aSig ) + 2; - if ( ( zSig & 0x7F ) <=3D 5 ) { - if ( zSig < 2 ) { - zSig =3D 0x7FFFFFFF; - goto roundAndPack; - } - aSig >>=3D aExp & 1; - term =3D ( (uint64_t) zSig ) * zSig; - rem =3D ( ( (uint64_t) aSig )<<32 ) - term; - while ( (int64_t) rem < 0 ) { - --zSig; - rem +=3D ( ( (uint64_t) zSig )<<1 ) | 1; - } - zSig |=3D ( rem !=3D 0 ); - } - shift32RightJamming( zSig, 1, &zSig ); - roundAndPack: - return roundAndPackFloat32(0, zExp, zSig, status); - -} =20 /*------------------------------------------------------------------------= ---- | Returns the binary exponential of the single-precision floating-point va= lue @@ -4203,61 +4237,6 @@ float64 float64_rem(float64 a, float64 b, float_stat= us *status) =20 } =20 - -/*------------------------------------------------------------------------= ---- -| Returns the square root of the double-precision floating-point value `a'. -| The operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_sqrt(float64 a, float_status *status) -{ - flag aSign; - int aExp, zExp; - uint64_t aSig, zSig, doubleZSig; - uint64_t rem0, rem1, term0, term1; - a =3D float64_squash_input_denormal(a, status); - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - if ( aExp =3D=3D 0x7FF ) { - if (aSig) { - return propagateFloat64NaN(a, a, status); - } - if ( ! aSign ) return a; - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - if ( aSign ) { - if ( ( aExp | aSig ) =3D=3D 0 ) return a; - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return float64_zero; - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - zExp =3D ( ( aExp - 0x3FF )>>1 ) + 0x3FE; - aSig |=3D LIT64( 0x0010000000000000 ); - zSig =3D estimateSqrt32( aExp, aSig>>21 ); - aSig <<=3D 9 - ( aExp & 1 ); - zSig =3D estimateDiv128To64( aSig, 0, zSig<<32 ) + ( zSig<<30 ); - if ( ( zSig & 0x1FF ) <=3D 5 ) { - doubleZSig =3D zSig<<1; - mul64To128( zSig, zSig, &term0, &term1 ); - sub128( aSig, 0, term0, term1, &rem0, &rem1 ); - while ( (int64_t) rem0 < 0 ) { - --zSig; - doubleZSig -=3D 2; - add128( rem0, rem1, zSig>>63, doubleZSig | 1, &rem0, &rem1 ); - } - zSig |=3D ( ( rem0 | rem1 ) !=3D 0 ); - } - return roundAndPackFloat64(0, zExp, zSig, status); - -} - /*------------------------------------------------------------------------= ---- | Returns the binary log of the double-precision floating-point value `a'. | The operation is performed according to the IEC/IEEE Standard for Binary diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index cebe37b716..9b7b5e34e2 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -251,6 +251,7 @@ float16 float16_minnum(float16, float16, float_status *= status); float16 float16_maxnum(float16, float16, float_status *status); float16 float16_minnummag(float16, float16, float_status *status); float16 float16_maxnummag(float16, float16, float_status *status); +float16 float16_sqrt(float16, float_status *status); int float16_compare(float16, float16, float_status *status); int float16_compare_quiet(float16, float16, float_status *status); =20 --=20 2.15.1