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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id r27sm26949344pfj.75.2018.01.28.15.16.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 28 Jan 2018 15:16:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2tOlTE3fGONKVXMFT49Q6MX6S2UmKToc68yykLOO3mU=; b=YMY6uZJhAHuDSj6oGH4O3BJDwcxVD4/ILhwPZn83QG7jyJXTC1K8Xq/pXpuKJJJCf3 ToiBHIicJp4KDO2GuBB8AgL2WofgKVRXmOMLdiNfEMngdx0VJcEOgWwcurcz5uTj03EF 7TjjwJhY4E09nQ4K1rWg7MSW+TVkAQvB8SZZk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2tOlTE3fGONKVXMFT49Q6MX6S2UmKToc68yykLOO3mU=; b=PaV6LzDPrm5sGVN8wVJ4jOikt3J74WJGqrsVLdNt3OCiPcCMcvr7OdLmmMnr29WsJA an+7nXzHk612fni3mvKofsvELPFEJAYbPqbp4LNjvQzsUobVvY456KNsjP5fPvhYSUNJ pEQfxpTUSCnr2Va8JqD1apgfeVDfXcSAI6nPvIM0hpn650o0iXnHgc419uWIuZrPrGn4 qkFe+PdB1j+yJd3+jSrxYp3tveBaBI6LahNP6LE+qNMpq/VqDWylaqO52PMmni2D/Jyr 1h5iWvdekN8N6rTmA88aUpP0MtwR26ZRiY2nM6A+tZq0NXcNa7by125eiUjtD4VMLVo6 +CsA== X-Gm-Message-State: AKwxyteUsFYlPcaLunXaZASGA2KsM9N+AOdy9rqL1zI6TIVauvBZy70w qIDp3GNwAChzvoBwEEdA0iNN8dI4R/Y= X-Google-Smtp-Source: AH8x226b/TFothGUi09FcbgASV97umwWQ0OQ/WCJVS1iQeClIr9O0MdBMjNgTdfAaXvfnuIKOPMNgA== X-Received: by 10.99.65.133 with SMTP id o127mr11021828pga.13.1517181395821; Sun, 28 Jan 2018 15:16:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 28 Jan 2018 15:15:27 -0800 Message-Id: <20180128231528.22719-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180128231528.22719-1-richard.henderson@linaro.org> References: <20180128231528.22719-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL v4 42/43] target/hppa: Fix 32-bit operand masks for 0E FCVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We masked the wrong bits, which prevented some of the 32-bit R registers. E.g. "fcnvxf,sgl,sgl fr22R,fr6R". Signed-off-by: Richard Henderson --- target/hppa/translate.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b9b097acc9..c62ee72615 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4381,34 +4381,34 @@ static const DisasInsn table_float_0e[] =3D { /* floating point class one */ /* float/float */ { 0x38000a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_d_s }, - { 0x38002200, 0xfc1fffc0, FOP_DEW =3D gen_helper_fcnv_s_d }, + { 0x38002200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_s_d }, /* int/float */ - { 0x38008200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_w_s }, + { 0x38008200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_w_s }, { 0x38008a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_dw_s }, { 0x3800a200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_w_d }, { 0x3800aa00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_dw_d }, /* float/int */ - { 0x38010200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_s_w }, + { 0x38010200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_s_w }, { 0x38010a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_d_w }, { 0x38012200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_s_dw }, { 0x38012a00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_d_dw }, /* float/int truncate */ - { 0x38018200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_t_s_w }, + { 0x38018200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_t_s_w }, { 0x38018a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_t_d_w }, { 0x3801a200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_t_s_dw }, { 0x3801aa00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_t_d_dw }, /* uint/float */ - { 0x38028200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_uw_s }, + { 0x38028200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_uw_s }, { 0x38028a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_udw_s }, { 0x3802a200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_uw_d }, { 0x3802aa00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_udw_d }, /* float/uint */ - { 0x38030200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_s_uw }, + { 0x38030200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_s_uw }, { 0x38030a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_d_uw }, { 0x38032200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_s_udw }, { 0x38032a00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_d_udw }, /* float/uint truncate */ - { 0x38038200, 0xfc1ffe60, FOP_WEW =3D gen_helper_fcnv_t_s_uw }, + { 0x38038200, 0xfc1ffe20, FOP_WEW =3D gen_helper_fcnv_t_s_uw }, { 0x38038a00, 0xfc1fffa0, FOP_WED =3D gen_helper_fcnv_t_d_uw }, { 0x3803a200, 0xfc1fff60, FOP_DEW =3D gen_helper_fcnv_t_s_udw }, { 0x3803aa00, 0xfc1fffe0, FOP_DED =3D gen_helper_fcnv_t_d_udw }, --=20 2.14.3