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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id q67sm20460313pfi.164.2018.01.25.20.58.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Jan 2018 20:58:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7zD9ZLMaBfM3L9Jb5GjWQeL+d+QUdyrmFo8RuhCOQx8=; b=fxs5r7BbunxPeOYIh3Byi+sW7152qIPt84JL85GZ74VO2Zzzed3ZlFuUgSoCP+M7Qt EXg5JtL7Ik/MKops7Ay9uWdWGm5LkLbJft6CVXiorY1+NAgz+Jzh8wO3G1gqo51rGTG6 9Qj2NvdiBL7OoCe5JcJxaWyibpAN8QkbIAIYI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7zD9ZLMaBfM3L9Jb5GjWQeL+d+QUdyrmFo8RuhCOQx8=; b=b9PHQE8tQzgQYcWeI6n1fDh1FQaqY08f8/C+Gk6ShsTXrfx5k8kn9I9GOtYHvc7AMV EtRp6Aecr5NS7YP2IoejNaORhdKNnMf2oykEjMy0L1hYSV1P0pMgVRnbLNr6M8bIS98T oKmZtpZAwaC1K2sOq9Sc63AE9kZWpKIkGIndG4nKM77RYmWOMEXINt/uN3P9/YitAkMI GqwxVt/PlZjFFMuTnn09bQVPEUAT3wgz3KeGrwK0t5M6wp0PCWEAtaYuJs8PbTXnTeyC Hu/vr+BcHLl9l4VKnxTFRskorUyB4oeMj7AobyGFzgj58bdLy2bd8x3WPTNNWbuVAJhn j05Q== X-Gm-Message-State: AKwxytd6RX1bAMVJt0SwMe2GXCZwpVRQLnbdQhL9AM5zWM+1w0vvpY96 BPuZFik6yJrhREH7lB8PhyliWNeKd8M= X-Google-Smtp-Source: AH8x226SkevEMnFYIQ0ALzWwS+QM1lGyXNB74QypdrKEDzYT0XlD0ZjBLSOPxOIZVn0ATKJDmh6tNw== X-Received: by 10.101.91.66 with SMTP id y2mr15329578pgr.11.1516942702063; Thu, 25 Jan 2018 20:58:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 20:57:39 -0800 Message-Id: <20180126045742.5487-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180126045742.5487-1-richard.henderson@linaro.org> References: <20180126045742.5487-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v11 17/20] target/arm: Use vector infrastructure for aa64 multiplies X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate-a64.c | 154 +++++++++++++++++++++++++++++++++++++----= ---- 1 file changed, 129 insertions(+), 25 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c928c4787c..64a2c2df59 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9753,6 +9753,66 @@ static void disas_simd_3same_float(DisasContext *s, = uint32_t insn) } } =20 +static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u8(a, a, b); + gen_helper_neon_add_u8(d, d, a); +} + +static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u16(a, a, b); + gen_helper_neon_add_u16(d, d, a); +} + +static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_mul_i32(a, a, b); + tcg_gen_add_i32(d, d, a); +} + +static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_mul_i64(a, a, b); + tcg_gen_add_i64(d, d, a); +} + +static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + tcg_gen_mul_vec(vece, a, a, b); + tcg_gen_add_vec(vece, d, d, a); +} + +static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u8(a, a, b); + gen_helper_neon_sub_u8(d, d, a); +} + +static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u16(a, a, b); + gen_helper_neon_sub_u16(d, d, a); +} + +static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_mul_i32(a, a, b); + tcg_gen_sub_i32(d, d, a); +} + +static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_mul_i64(a, a, b); + tcg_gen_sub_i64(d, d, a); +} + +static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + tcg_gen_mul_vec(vece, a, a, b); + tcg_gen_sub_vec(vece, d, d, a); +} + /* Integer op subgroup of C3.6.16. */ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) { @@ -9771,6 +9831,52 @@ static void disas_simd_3same_int(DisasContext *s, ui= nt32_t insn) .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; + static const GVecGen3 mla_op[4] =3D { + { .fni4 =3D gen_mla8_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_8 }, + { .fni4 =3D gen_mla16_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_16 }, + { .fni4 =3D gen_mla32_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_32 }, + { .fni8 =3D gen_mla64_i64, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .vece =3D MO_64 }, + }; + static const GVecGen3 mls_op[4] =3D { + { .fni4 =3D gen_mls8_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_8 }, + { .fni4 =3D gen_mls16_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_16 }, + { .fni4 =3D gen_mls32_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_32 }, + { .fni8 =3D gen_mls64_i64, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .vece =3D MO_64 }, + }; =20 int is_q =3D extract32(insn, 30, 1); int u =3D extract32(insn, 29, 1); @@ -9828,6 +9934,19 @@ static void disas_simd_3same_int(DisasContext *s, ui= nt32_t insn) gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size); } return; + case 0x13: /* MUL, PMUL */ + if (!u) { /* MUL */ + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size); + return; + } + break; + case 0x12: /* MLA, MLS */ + if (u) { + gen_gvec_op3(s, is_q, rd, rn, rm, &mls_op[size]); + } else { + gen_gvec_op3(s, is_q, rd, rn, rm, &mla_op[size]); + } + return; case 0x11: if (!u) { /* CMTST */ gen_gvec_op3(s, is_q, rd, rn, rm, &cmtst_op[size]); @@ -10002,23 +10121,10 @@ static void disas_simd_3same_int(DisasContext *s,= uint32_t insn) break; } case 0x13: /* MUL, PMUL */ - if (u) { - /* PMUL */ - assert(size =3D=3D 0); - genfn =3D gen_helper_neon_mul_p8; - break; - } - /* fall through : MUL */ - case 0x12: /* MLA, MLS */ - { - static NeonGenTwoOpFn * const fns[3] =3D { - gen_helper_neon_mul_u8, - gen_helper_neon_mul_u16, - tcg_gen_mul_i32, - }; - genfn =3D fns[size]; + assert(u); /* PMUL */ + assert(size =3D=3D 0); + genfn =3D gen_helper_neon_mul_p8; break; - } case 0x16: /* SQDMULH, SQRDMULH */ { static NeonGenTwoOpEnvFn * const fns[2][2] =3D { @@ -10039,18 +10145,16 @@ static void disas_simd_3same_int(DisasContext *s,= uint32_t insn) genfn(tcg_res, tcg_op1, tcg_op2); } =20 - if (opcode =3D=3D 0xf || opcode =3D=3D 0x12) { - /* SABA, UABA, MLA, MLS: accumulating ops */ - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, - { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, - { tcg_gen_add_i32, tcg_gen_sub_i32 }, + if (opcode =3D=3D 0xf) { + /* SABA, UABA: accumulating ops */ + static NeonGenTwoOpFn * const fns[3] =3D { + gen_helper_neon_add_u8, + gen_helper_neon_add_u16, + tcg_gen_add_i32, }; - bool is_sub =3D (opcode =3D=3D 0x12 && u); /* MLS */ =20 - genfn =3D fns[size][is_sub]; read_vec_element_i32(s, tcg_op1, rd, pass, MO_32); - genfn(tcg_res, tcg_op1, tcg_res); + fns[size](tcg_res, tcg_op1, tcg_res); } =20 write_vec_element_i32(s, tcg_res, rd, pass, MO_32); --=20 2.14.3