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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id q67sm20460313pfi.164.2018.01.25.20.58.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Jan 2018 20:58:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aXOW9DNrmikT+uiYNyn+PgFEkDKfF1zmv/rxbEsPO9U=; b=Ed7IgT1OloCH5OwoKm6F39tAnmWodJfANsPEQ/8D5ppl3jTzcz1gBOz2TF3r7pzcQR D9GHXIRsdLRTEWXF11UMxuGOO/ZPAFQ5AYAggl4gSK9rAKGjCYabe3xuL5BWU1seqzrr DG+SUiPlZL1/6AUxQ0AZl21SZ8e97/ZHVQdZU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aXOW9DNrmikT+uiYNyn+PgFEkDKfF1zmv/rxbEsPO9U=; b=EcRQHpbjWpxO9xKUqjMnn06Ckib3QxivVBcTy4Cyt7mkqPB0f1H75Vs0zxEliWNqw7 E1rCjvnT9JuszH/a4d+CMLcfgd3N0FxuOXBdqVCCXuASqGXkOPOq2JuggibcyBNu5GWN lAICuSR5mTYZdOwpe3PQ5fqvhAeDe326wrZbVy6w4+9Hh7UgwhR7ivRMd+UNwu7CqMQv HJ16CGJwbidIIYCXPAfK2x9TkDBx3c5VOTByWI1tH/kR68Tf6FePF/tmHzd/QFz8r8O+ Qb0jjN+mvvu3wS9NDWlfbIkVS+Y8HoxWjjNeu0BnOb3blY4Hy1sZ+7dUdvP3kY/YdAcd 40uw== X-Gm-Message-State: AKwxytclNdqKEGCQ5zA0EtFhTx4HJsEOg92wERMoc1MYj18OadhbTtok pL9uJOyY7QMvdFWKHV9giTmaFlK7OuQ= X-Google-Smtp-Source: AH8x224tnZqzEYe9u/NTqxk3rFWXsSdkRQaVouaBHxlELABav4HRDi7hVJYlOpXYX+v3GPWk3juY+A== X-Received: by 2002:a17:902:6b48:: with SMTP id g8-v6mr4267323plt.151.1516942696201; Thu, 25 Jan 2018 20:58:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 20:57:35 -0800 Message-Id: <20180126045742.5487-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180126045742.5487-1-richard.henderson@linaro.org> References: <20180126045742.5487-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v11 13/20] target/arm: Use vector infrastructure for aa64 mov/not/neg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate-a64.c | 42 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5a4e62ae0f..11310f1a7a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -86,6 +86,7 @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_= i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); =20 /* Note that the gvec expanders operate on offsets + sizes. */ +typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); =20 @@ -631,6 +632,14 @@ static TCGv_ptr get_fpstatus_ptr(void) return statusptr; } =20 +/* Expand a 2-operand AdvSIMD vector operation using an expander function.= */ +static void gen_gvec_fn2(DisasContext *s, bool is_q, int rd, int rn, + GVecGen2Fn *gvec_fn, int vece) +{ + gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), + is_q ? 16 : 8, vec_full_reg_size(s)); +} + /* Expand a 3-operand AdvSIMD vector operation using an expander function.= */ static void gen_gvec_fn3(DisasContext *s, bool is_q, int rd, int rn, int r= m, GVecGen3Fn *gvec_fn, int vece) @@ -4596,14 +4605,17 @@ static void handle_fp_1src_double(DisasContext *s, = int opcode, int rd, int rn) TCGv_i64 tcg_op; TCGv_i64 tcg_res; =20 + switch (opcode) { + case 0x0: /* FMOV */ + gen_gvec_fn2(s, false, rd, rn, tcg_gen_gvec_mov, 0); + return; + } + fpst =3D get_fpstatus_ptr(); tcg_op =3D read_fp_dreg(s, rn); tcg_res =3D tcg_temp_new_i64(); =20 switch (opcode) { - case 0x0: /* FMOV */ - tcg_gen_mov_i64(tcg_res, tcg_op); - break; case 0x1: /* FABS */ gen_helper_vfp_absd(tcg_res, tcg_op); break; @@ -9185,7 +9197,11 @@ static void disas_simd_3same_logic(DisasContext *s, = uint32_t insn) gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0); return; case 2: /* ORR */ - gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); + if (rn =3D=3D rm) { /* MOV */ + gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0); + } else { + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); + } return; case 3: /* ORN */ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0); @@ -10059,8 +10075,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) return; case 0x5: /* CNT, NOT, RBIT */ if (u && size =3D=3D 0) { - /* NOT: adjust size so we can use the 64-bits-at-a-time loop. = */ - size =3D 3; + /* NOT */ break; } else if (u && size =3D=3D 1) { /* RBIT */ @@ -10312,6 +10327,21 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) tcg_rmode =3D NULL; } =20 + switch (opcode) { + case 0x5: + if (u && size =3D=3D 0) { /* NOT */ + gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0); + return; + } + break; + case 0xb: + if (u) { /* NEG */ + gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); + return; + } + break; + } + if (size =3D=3D 3) { /* All 64-bit element operations can be shared with scalar 2misc */ int pass; --=20 2.14.3