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Thu, 25 Jan 2018 10:15:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eejFf-0000lD-KP for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:46 -0500 Received: from mout.kundenserver.de ([212.227.126.134]:62674) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eejFf-0000kI-An for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:43 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue004 [212.227.15.167]) with ESMTPSA (Nemesis) id 0LgtFa-1fAz8d2eTW-00oBbP; Thu, 25 Jan 2018 16:15:41 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 16:15:34 +0100 Message-Id: <20180125151535.25256-8-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180125151535.25256-1-laurent@vivier.eu> References: <20180125151535.25256-1-laurent@vivier.eu> X-Provags-ID: V03:K0:gBa5kLY2bx+pRPpNmc2vvWJ/eOzUa6y9vzDsyG1NGRm/ompn5qf k8X/c75BkK8CA0McVe6LjyV4mQhDzQJCEPPFOOrVJHm5OK7RKtuDZexPhXj+KCuNai0OEFY qdJobFFWjyQNg7EwHaWDLYw7pSsmJ4zAoTLDKMa1lk2sG3LXHZ1FCP72u883W+uCmgLuJkA o4L2lYZPjNJQ/NZwlNq/A== X-UI-Out-Filterresults: notjunk:1;V01:K0:4WrAijYb4hg=:H9PpuPZyP5syhgwQjfkk88 e9C5Vx+q2yYDdbCmQiEz5Pm98OiIuGkjkHmBOSeArdFNTg2K0DUbVyD6fDfAx2sJuOm7LU+xL hUFaNr8XKUx7XNzWnjKWafLoAVEfFD1VG25ag0iILMN/7iCUHIr+Kze9RNwzfzaaPfgi4aSdw ouFI+qEjngzoi72xpQM5GdrGR8qCK9p6zzBlne/cnd23BoBz/altWMT5r7Ec8DOr7CxXiPLL2 mkdYAYkFpe4WAN/qkY/xVQLvEbwPRECQA67uqJVQwP/6TVvL7l8RPycBtHs4sRhAioPWauQIx oGAsycgUNLPiQ9n+Txb1SHIJUtM5BPqehyEuBGqKlZzcGxZWwfTg8iOXHfUs4Z+9PR91P3Sd9 BEcokGJRJO9hlylEFDWlOmnrVE1PgZ5rBPSMHQuTt/pxZpAUuiFKR9OK9xdHmz+FxivbrTAZD KJLqpE4ab6yqepL0uC8h+lgn2XRadEcMSUJ8KyKCOSl6DKMjzoerYrSPoSepPQre5JWXCA2cW 6r5zcmKGdZccr7vQRWrS4R2qN8RAnj1UQpFA2a0GsiYFtT0jnsIlpevAL5gTGl0HF7l86gohq aihdcr+nZ+p2CsBbI2sOaN1w/rZaFoiX3kMhRnYtRKWMg0wkPxUUZ4kw/sfJhVCnBcDYMx9Vv oiE+taDVhwCAIiKm0/RpS65a7S8g0XybOFEU9aTpS1Ph8Bdf3XwWgmh5vcOJgXWziJk0H1hSs 7VnLjNeuuyV7cJcTE+QWcz7tgwlTcApjk1kK5A== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.134 Subject: [Qemu-devel] [PULL 7/8] target/m68k: add pflush/ptest X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20180118193846.24953-7-laurent@vivier.eu> --- target/m68k/cpu.h | 3 ++ target/m68k/helper.c | 73 +++++++++++++++++++++++++++++++++++++++++++++= ++++ target/m68k/helper.h | 2 ++ target/m68k/monitor.c | 1 + target/m68k/op_helper.c | 1 + target/m68k/translate.c | 33 ++++++++++++++++++++++ 6 files changed, 113 insertions(+) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index cc1759bb5d..0739c3f5c8 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -131,6 +131,7 @@ typedef struct CPUM68KState { uint32_t srp; bool fault; uint32_t ttr[4]; + uint32_t mmusr; } mmu; =20 /* Control registers. */ @@ -512,6 +513,8 @@ enum { ACCESS_STORE =3D 0x02, /* 1 bit to indicate debug access */ ACCESS_DEBUG =3D 0x04, + /* PTEST instruction */ + ACCESS_PTEST =3D 0x08, /* Type of instruction that generated the access */ ACCESS_CODE =3D 0x10, /* Code fetch access */ ACCESS_DATA =3D 0x20, /* Data load/store access */ diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 80db0b75b0..9fd9d3f1ff 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -221,6 +221,9 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t = reg, uint32_t val) case M68K_CR_TC: env->mmu.tcr =3D val; return; + case M68K_CR_MMUSR: + env->mmu.mmusr =3D val; + return; case M68K_CR_SRP: env->mmu.srp =3D val; return; @@ -272,6 +275,8 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uin= t32_t reg) /* MC680[34]0 */ case M68K_CR_TC: return env->mmu.tcr; + case M68K_CR_MMUSR: + return env->mmu.mmusr; case M68K_CR_SRP: return env->mmu.srp; case M68K_CR_USP: @@ -433,6 +438,10 @@ static int get_physical_address(CPUM68KState *env, hwa= ddr *physical, for (i =3D 0; i < M68K_MAX_TTR; i++) { if (check_TTR(env->mmu.TTR(access_type, i), prot, address, access_type)) { + if (access_type & ACCESS_PTEST) { + /* Transparent Translation Register bit */ + env->mmu.mmusr =3D M68K_MMU_T_040 | M68K_MMU_R_040; + } *physical =3D address & TARGET_PAGE_MASK; *page_size =3D TARGET_PAGE_SIZE; return 0; @@ -461,6 +470,9 @@ static int get_physical_address(CPUM68KState *env, hwad= dr *physical, stl_phys(cs->as, entry, next | M68K_DESC_USED); } if (next & M68K_DESC_WRITEPROT) { + if (access_type & ACCESS_PTEST) { + env->mmu.mmusr |=3D M68K_MMU_WP_040; + } *prot &=3D ~PAGE_WRITE; if (access_type & ACCESS_STORE) { return -1; @@ -478,6 +490,9 @@ static int get_physical_address(CPUM68KState *env, hwad= dr *physical, stl_phys(cs->as, entry, next | M68K_DESC_USED); } if (next & M68K_DESC_WRITEPROT) { + if (access_type & ACCESS_PTEST) { + env->mmu.mmusr |=3D M68K_MMU_WP_040; + } *prot &=3D ~PAGE_WRITE; if (access_type & ACCESS_STORE) { return -1; @@ -524,6 +539,12 @@ static int get_physical_address(CPUM68KState *env, hwa= ddr *physical, page_mask =3D ~(*page_size - 1); *physical =3D next & page_mask; =20 + if (access_type & ACCESS_PTEST) { + env->mmu.mmusr |=3D next & M68K_MMU_SR_MASK_040; + env->mmu.mmusr |=3D *physical & 0xfffff000; + env->mmu.mmusr |=3D M68K_MMU_R_040; + } + if (next & M68K_DESC_WRITEPROT) { *prot &=3D ~PAGE_WRITE; if (access_type & ACCESS_STORE) { @@ -1078,6 +1099,58 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_= t val, uint32_t acc) } =20 #if defined(CONFIG_SOFTMMU) +void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read) +{ + M68kCPU *cpu =3D m68k_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + hwaddr physical; + int access_type; + int prot; + int ret; + target_ulong page_size; + + access_type =3D ACCESS_PTEST; + if (env->dfc & 4) { + access_type |=3D ACCESS_SUPER; + } + if ((env->dfc & 3) =3D=3D 2) { + access_type |=3D ACCESS_CODE; + } + if (!is_read) { + access_type |=3D ACCESS_STORE; + } + + env->mmu.mmusr =3D 0; + env->mmu.ssw =3D 0; + ret =3D get_physical_address(env, &physical, &prot, addr, + access_type, &page_size); + if (ret =3D=3D 0) { + addr &=3D TARGET_PAGE_MASK; + physical +=3D addr & (page_size - 1); + tlb_set_page(cs, addr, physical, + prot, access_type & ACCESS_SUPER ? + MMU_KERNEL_IDX : MMU_USER_IDX, page_size); + } +} + +void HELPER(pflush)(CPUM68KState *env, uint32_t addr, uint32_t opmode) +{ + M68kCPU *cpu =3D m68k_env_get_cpu(env); + + switch (opmode) { + case 0: /* Flush page entry if not global */ + case 1: /* Flush page entry */ + tlb_flush_page(CPU(cpu), addr); + break; + case 2: /* Flush all except global entries */ + tlb_flush(CPU(cpu)); + break; + case 3: /* Flush all entries */ + tlb_flush(CPU(cpu)); + break; + } +} + void HELPER(reset)(CPUM68KState *env) { /* FIXME: reset all except CPU */ diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 57f210aa14..7f400f0def 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -101,5 +101,7 @@ DEF_HELPER_3(chk, void, env, s32, s32) DEF_HELPER_4(chk2, void, env, s32, s32, s32) =20 #if defined(CONFIG_SOFTMMU) +DEF_HELPER_3(ptest, void, env, i32, i32) +DEF_HELPER_3(pflush, void, env, i32, i32) DEF_HELPER_FLAGS_1(reset, TCG_CALL_NO_RWG, void, env) #endif diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c index c31feb4b02..486213cd8b 100644 --- a/target/m68k/monitor.c +++ b/target/m68k/monitor.c @@ -39,6 +39,7 @@ static const MonitorDef monitor_defs[] =3D { { "dttr1", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR1]) }, { "ittr0", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR0]) }, { "ittr1", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR1]) }, + { "mmusr", offsetof(CPUM68KState, mmu.mmusr) }, { NULL }, }; =20 diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 4609caa546..ffea9693fc 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -466,6 +466,7 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr ad= dr, bool is_write, } =20 if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.mmusr =3D 0; env->mmu.ssw |=3D M68K_ATC_040; /* FIXME: manage MMU table access error */ env->mmu.ssw &=3D ~M68K_TM_040; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index c0edaa533c..34db97b8a0 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4661,6 +4661,35 @@ DISAS_INSN(cinv) /* Invalidate cache line. Implement as no-op. */ } =20 +#if defined(CONFIG_SOFTMMU) +DISAS_INSN(pflush) +{ + TCGv opmode; + + if (IS_USER(s)) { + gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); + return; + } + + opmode =3D tcg_const_i32((insn >> 3) & 3); + gen_helper_pflush(cpu_env, AREG(insn, 0), opmode); + tcg_temp_free(opmode); +} + +DISAS_INSN(ptest) +{ + TCGv is_read; + + if (IS_USER(s)) { + gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); + return; + } + is_read =3D tcg_const_i32((insn >> 5) & 1); + gen_helper_ptest(cpu_env, AREG(insn, 0), is_read); + tcg_temp_free(is_read); +} +#endif + DISAS_INSN(wddata) { gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); @@ -5854,6 +5883,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(cpushl, f428, ff38, CF_ISA_A); INSN(cpush, f420, ff20, M68040); INSN(cinv, f400, ff20, M68040); + INSN(pflush, f500, ffe0, M68040); + INSN(ptest, f548, ffd8, M68040); INSN(wddata, fb00, ff00, CF_ISA_A); INSN(wdebug, fbc0, ffc0, CF_ISA_A); #endif @@ -6056,6 +6087,8 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprin= tf_function cpu_fprintf, cpu_fprintf(f, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n", env->mmu.ttr[M68K_DTTR0], env->mmu.ttr[M68K_DTTR1], env->mmu.ttr[M68K_ITTR0], env->mmu.ttr[M68K_ITTR1]); + cpu_fprintf(f, "MMUSR %08x, fault at %08x\n", + env->mmu.mmusr, env->mmu.ar); #endif } =20 --=20 2.14.3