From nobody Wed Feb 11 02:10:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516893488532768.4745549444445; Thu, 25 Jan 2018 07:18:08 -0800 (PST) Received: from localhost ([::1]:46103 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejHz-0007ax-N3 for importer@patchew.org; Thu, 25 Jan 2018 10:18:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eejFg-0006EK-OR for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eejFe-0000kO-Lg for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:44 -0500 Received: from mout.kundenserver.de ([212.227.126.187]:53786) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eejFe-0000je-8T for qemu-devel@nongnu.org; Thu, 25 Jan 2018 10:15:42 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue004 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MHKOl-1eaYWd2J87-00E1yI; Thu, 25 Jan 2018 16:15:41 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 25 Jan 2018 16:15:32 +0100 Message-Id: <20180125151535.25256-6-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180125151535.25256-1-laurent@vivier.eu> References: <20180125151535.25256-1-laurent@vivier.eu> X-Provags-ID: V03:K0:4hTDSXMpXQ4DL4/WJ91Zf3DIO93HiiTv/wWRibI9L4LD1mYWtKN P6OCNCJJQYBZmMD5m+C29cYlly3jnktOix/I5PcxJhPy1LMYtcEZcKzlqDehLWa446GMTjB NM94B2A4+MwD9vTNmOQaafWvptYJyFmFHQjo0zRosPJMJnkKb7zJOHlr2kNiBWHDMsy2tui ekZD12XXPmK0ygikNL5kQ== X-UI-Out-Filterresults: notjunk:1;V01:K0:2grLtj2dQK8=:eMjkcIdJ9HtsiKQ81wcVGv Hgo4b3vTQggoWxgqn2YxeT3TRKtrk2D+DL0Tdcb78xSNwXYcxfHkA9JxlVTD86z78iTtfm1jS 7PI/s7lo9rnVWH+/RQ8KRVkYF7iYU89DCZoZphx6jjXb+x6EkjzR4Y4KGM9vI8EsJuokWA+gA pxH615eGDMyAbjBT9c5qWgRq3VObifi/rkAWQtzGMG3M4lBKMc6486TkAKj3DixpYmd+piGVb qd7P98G9zOVLBYgNaxZbG3hgadG/qPj2OMYHY7FU1ogtnidFbZme7p5lqtM0sSWdlYBW691zc /EfsfweEOnaSmTrme87Ju56Ey175j68P75AFXc1y+tAciU1bELxe9vK+Ps8doox3OrVPQlX5V 7rtGPaWTFwCpWnbfXmmg45rCf+5eSgQbBVVF8vrEac8ZfTDvgt5YNIbT+U32pz/0kPA47NmF9 4OPCpEFDGy3tUBMJ0nrvCHhAStO1c5KNjjUG3U4q+jDsV4lrJrjpha3ALmS2bcbtjhJqMz2ka PVGfeoVjmYOienO0cjCvOPaI+kZNGNxFnUMVytf0gUBvsDZ9MDp/cVx1Qhu4iovCiDE9m0JGF mmTa/v35cMCWP55bi6mA0xw1KUsHHUuYFN0EyAkUKjqlhpOQaqQK0NEQ7Dsjr4x3hmh3uZY2G TzFf0wXHoAALk1/5cQy+8yL9t9ngxjGKF2TuZh8dn6rPcI61WyygOMNjoy4uyXAGJoUNr2NkG 90B1/NfxVObf1rK8AWenW4j+TrLjRHyRghJiKg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PULL 5/8] target/m68k: add index parameter to gen_load()/gen_store() and Co. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The instruction "moves" can select source and destination address space (user or kernel). This patch modifies all the load/store functions to be able to provide the address space the caller wants to use instead of using the current one. All the callers are modified to provide the default address space to these functions. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20180118193846.24953-5-laurent@vivier.eu> --- target/m68k/translate.c | 125 +++++++++++++++++++++++++-------------------= ---- 1 file changed, 66 insertions(+), 59 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index b33b3c6828..ecb89e4239 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -281,10 +281,10 @@ static inline void gen_addr_fault(DisasContext *s) =20 /* Generate a load from the specified address. Narrow values are sign extended to full register width. */ -static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int s= ign) +static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr, + int sign, int index) { TCGv tmp; - int index =3D IS_USER(s); tmp =3D tcg_temp_new_i32(); switch(opsize) { case OS_BYTE: @@ -309,9 +309,9 @@ static inline TCGv gen_load(DisasContext * s, int opsiz= e, TCGv addr, int sign) } =20 /* Generate a store. */ -static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv = val) +static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv = val, + int index) { - int index =3D IS_USER(s); switch(opsize) { case OS_BYTE: tcg_gen_qemu_st8(val, addr, index); @@ -336,13 +336,13 @@ typedef enum { /* Generate an unsigned load if VAL is 0 a signed load if val is -1, otherwise generate a store. */ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, - ea_what what) + ea_what what, int index) { if (what =3D=3D EA_STORE) { - gen_store(s, opsize, addr, val); + gen_store(s, opsize, addr, val, index); return store_dummy; } else { - return gen_load(s, opsize, addr, what =3D=3D EA_LOADS); + return gen_load(s, opsize, addr, what =3D=3D EA_LOADS, index); } } =20 @@ -464,7 +464,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasCon= text *s, TCGv base) } if ((ext & 3) !=3D 0) { /* memory indirect */ - base =3D gen_load(s, OS_LONG, add, 0); + base =3D gen_load(s, OS_LONG, add, 0, IS_USER(s)); if ((ext & 0x44) =3D=3D 4) { add =3D gen_addr_index(s, ext, tmp); tcg_gen_add_i32(tmp, add, base); @@ -793,7 +793,8 @@ static TCGv gen_lea(CPUM68KState *env, DisasContext *s,= uint16_t insn, a write otherwise it is a read (0 =3D=3D sign extend, -1 =3D=3D zero ex= tend). ADDRP is non-null for readwrite operands. */ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int = reg0, - int opsize, TCGv val, TCGv *addrp, ea_what what) + int opsize, TCGv val, TCGv *addrp, ea_what what, + int index) { TCGv reg, tmp, result; int32_t offset; @@ -817,10 +818,10 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasConte= xt *s, int mode, int reg0, } case 2: /* Indirect register */ reg =3D get_areg(s, reg0); - return gen_ldst(s, opsize, reg, val, what); + return gen_ldst(s, opsize, reg, val, what, index); case 3: /* Indirect postincrement. */ reg =3D get_areg(s, reg0); - result =3D gen_ldst(s, opsize, reg, val, what); + result =3D gen_ldst(s, opsize, reg, val, what, index); if (what =3D=3D EA_STORE || !addrp) { TCGv tmp =3D tcg_temp_new(); if (reg0 =3D=3D 7 && opsize =3D=3D OS_BYTE && @@ -844,7 +845,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext= *s, int mode, int reg0, *addrp =3D tmp; } } - result =3D gen_ldst(s, opsize, tmp, val, what); + result =3D gen_ldst(s, opsize, tmp, val, what, index); if (what =3D=3D EA_STORE || !addrp) { delay_set_areg(s, reg0, tmp, false); } @@ -863,7 +864,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext= *s, int mode, int reg0, *addrp =3D tmp; } } - return gen_ldst(s, opsize, tmp, val, what); + return gen_ldst(s, opsize, tmp, val, what, index); case 7: /* Other */ switch (reg0) { case 0: /* Absolute short. */ @@ -904,11 +905,11 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasConte= xt *s, int mode, int reg0, } =20 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, - int opsize, TCGv val, TCGv *addrp, ea_what what) + int opsize, TCGv val, TCGv *addrp, ea_what what, int in= dex) { int mode =3D extract32(insn, 3, 3); int reg0 =3D REG(insn, 0); - return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what); + return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what, index= ); } =20 static TCGv_ptr gen_fp_ptr(int freg) @@ -941,11 +942,11 @@ static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src) tcg_temp_free_i64(t64); } =20 -static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr f= p) +static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr f= p, + int index) { TCGv tmp; TCGv_i64 t64; - int index =3D IS_USER(s); =20 t64 =3D tcg_temp_new_i64(); tmp =3D tcg_temp_new(); @@ -995,11 +996,11 @@ static void gen_load_fp(DisasContext *s, int opsize, = TCGv addr, TCGv_ptr fp) tcg_temp_free_i64(t64); } =20 -static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr = fp) +static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr = fp, + int index) { TCGv tmp; TCGv_i64 t64; - int index =3D IS_USER(s); =20 t64 =3D tcg_temp_new_i64(); tmp =3D tcg_temp_new(); @@ -1050,17 +1051,18 @@ static void gen_store_fp(DisasContext *s, int opsiz= e, TCGv addr, TCGv_ptr fp) } =20 static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr, - TCGv_ptr fp, ea_what what) + TCGv_ptr fp, ea_what what, int index) { if (what =3D=3D EA_STORE) { - gen_store_fp(s, opsize, addr, fp); + gen_store_fp(s, opsize, addr, fp, index); } else { - gen_load_fp(s, opsize, addr, fp); + gen_load_fp(s, opsize, addr, fp, index); } } =20 static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode, - int reg0, int opsize, TCGv_ptr fp, ea_what what) + int reg0, int opsize, TCGv_ptr fp, ea_what what, + int index) { TCGv reg, addr, tmp; TCGv_i64 t64; @@ -1108,11 +1110,11 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasC= ontext *s, int mode, return -1; case 2: /* Indirect register */ addr =3D get_areg(s, reg0); - gen_ldst_fp(s, opsize, addr, fp, what); + gen_ldst_fp(s, opsize, addr, fp, what, index); return 0; case 3: /* Indirect postincrement. */ addr =3D cpu_aregs[reg0]; - gen_ldst_fp(s, opsize, addr, fp, what); + gen_ldst_fp(s, opsize, addr, fp, what, index); tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize)); return 0; case 4: /* Indirect predecrememnt. */ @@ -1120,7 +1122,7 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasCon= text *s, int mode, if (IS_NULL_QREG(addr)) { return -1; } - gen_ldst_fp(s, opsize, addr, fp, what); + gen_ldst_fp(s, opsize, addr, fp, what, index); tcg_gen_mov_i32(cpu_aregs[reg0], addr); return 0; case 5: /* Indirect displacement. */ @@ -1130,7 +1132,7 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasCon= text *s, int mode, if (IS_NULL_QREG(addr)) { return -1; } - gen_ldst_fp(s, opsize, addr, fp, what); + gen_ldst_fp(s, opsize, addr, fp, what, index); return 0; case 7: /* Other */ switch (reg0) { @@ -1199,11 +1201,11 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasC= ontext *s, int mode, } =20 static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn, - int opsize, TCGv_ptr fp, ea_what what) + int opsize, TCGv_ptr fp, ea_what what, int index) { int mode =3D extract32(insn, 3, 3); int reg0 =3D REG(insn, 0); - return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what); + return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what, index); } =20 typedef struct { @@ -1423,7 +1425,7 @@ static void gen_lookup_tb(DisasContext *s) =20 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ result =3D gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ - op_sign ? EA_LOADS : EA_LOADU); \ + op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \ if (IS_NULL_QREG(result)) { \ gen_addr_fault(s); \ return; \ @@ -1431,7 +1433,8 @@ static void gen_lookup_tb(DisasContext *s) } while (0) =20 #define DEST_EA(env, insn, opsize, val, addrp) do { \ - TCGv ea_result =3D gen_ea(env, s, insn, opsize, val, addrp, EA_STO= RE); \ + TCGv ea_result =3D gen_ea(env, s, insn, opsize, val, addrp, \ + EA_STORE, IS_USER(s)); \ if (IS_NULL_QREG(ea_result)) { \ gen_addr_fault(s); \ return; \ @@ -1768,13 +1771,14 @@ DISAS_INSN(abcd_mem) /* Indirect pre-decrement load (mode 4) */ =20 src =3D gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, - NULL_QREG, NULL, EA_LOADU); + NULL_QREG, NULL, EA_LOADU, IS_USER(s)); dest =3D gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, - NULL_QREG, &addr, EA_LOADU); + NULL_QREG, &addr, EA_LOADU, IS_USER(s)); =20 bcd_add(dest, src); =20 - gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); + gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, + EA_STORE, IS_USER(s)); =20 bcd_flags(dest); } @@ -1804,13 +1808,14 @@ DISAS_INSN(sbcd_mem) /* Indirect pre-decrement load (mode 4) */ =20 src =3D gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, - NULL_QREG, NULL, EA_LOADU); + NULL_QREG, NULL, EA_LOADU, IS_USER(s)); dest =3D gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, - NULL_QREG, &addr, EA_LOADU); + NULL_QREG, &addr, EA_LOADU, IS_USER(s)); =20 bcd_sub(dest, src); =20 - gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); + gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, + EA_STORE, IS_USER(s)); =20 bcd_flags(dest); } @@ -1947,7 +1952,7 @@ static void gen_push(DisasContext *s, TCGv val) =20 tmp =3D tcg_temp_new(); tcg_gen_subi_i32(tmp, QREG_SP, 4); - gen_store(s, OS_LONG, tmp, val); + gen_store(s, OS_LONG, tmp, val, IS_USER(s)); tcg_gen_mov_i32(QREG_SP, tmp); tcg_temp_free(tmp); } @@ -2016,7 +2021,7 @@ DISAS_INSN(movem) /* memory to register */ for (i =3D 0; i < 16; i++) { if (mask & (1 << i)) { - r[i] =3D gen_load(s, opsize, addr, 1); + r[i] =3D gen_load(s, opsize, addr, 1, IS_USER(s)); tcg_gen_add_i32(addr, addr, incr); } } @@ -2048,10 +2053,10 @@ DISAS_INSN(movem) */ tmp =3D tcg_temp_new(); tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr); - gen_store(s, opsize, addr, tmp); + gen_store(s, opsize, addr, tmp, IS_USER(s)); tcg_temp_free(tmp); } else { - gen_store(s, opsize, addr, mreg(i)); + gen_store(s, opsize, addr, mreg(i), IS_USER(s)); } } } @@ -2059,7 +2064,7 @@ DISAS_INSN(movem) } else { for (i =3D 0; i < 16; i++) { if (mask & (1 << i)) { - gen_store(s, opsize, addr, mreg(i)); + gen_store(s, opsize, addr, mreg(i), IS_USER(s)); tcg_gen_add_i32(addr, addr, incr); } } @@ -2779,7 +2784,7 @@ static void gen_link(DisasContext *s, uint16_t insn, = int32_t offset) reg =3D AREG(insn, 0); tmp =3D tcg_temp_new(); tcg_gen_subi_i32(tmp, QREG_SP, 4); - gen_store(s, OS_LONG, tmp, reg); + gen_store(s, OS_LONG, tmp, reg, IS_USER(s)); if ((insn & 7) !=3D 7) { tcg_gen_mov_i32(reg, tmp); } @@ -2812,7 +2817,7 @@ DISAS_INSN(unlk) src =3D tcg_temp_new(); reg =3D AREG(insn, 0); tcg_gen_mov_i32(src, reg); - tmp =3D gen_load(s, OS_LONG, src, 0); + tmp =3D gen_load(s, OS_LONG, src, 0, IS_USER(s)); tcg_gen_mov_i32(reg, tmp); tcg_gen_addi_i32(QREG_SP, src, 4); tcg_temp_free(src); @@ -2839,7 +2844,7 @@ DISAS_INSN(rtd) TCGv tmp; int16_t offset =3D read_im16(env, s); =20 - tmp =3D gen_load(s, OS_LONG, QREG_SP, 0); + tmp =3D gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s)); tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4); gen_jmp(s, tmp); } @@ -2848,7 +2853,7 @@ DISAS_INSN(rts) { TCGv tmp; =20 - tmp =3D gen_load(s, OS_LONG, QREG_SP, 0); + tmp =3D gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s)); tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); gen_jmp(s, tmp); } @@ -3084,15 +3089,15 @@ DISAS_INSN(subx_mem) =20 addr_src =3D AREG(insn, 0); tcg_gen_subi_i32(addr_src, addr_src, opsize); - src =3D gen_load(s, opsize, addr_src, 1); + src =3D gen_load(s, opsize, addr_src, 1, IS_USER(s)); =20 addr_dest =3D AREG(insn, 9); tcg_gen_subi_i32(addr_dest, addr_dest, opsize); - dest =3D gen_load(s, opsize, addr_dest, 1); + dest =3D gen_load(s, opsize, addr_dest, 1, IS_USER(s)); =20 gen_subx(s, src, dest, opsize); =20 - gen_store(s, opsize, addr_dest, QREG_CC_N); + gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s)); } =20 DISAS_INSN(mov3q) @@ -3144,10 +3149,10 @@ DISAS_INSN(cmpm) =20 /* Post-increment load (mode 3) from Ay. */ src =3D gen_ea_mode(env, s, 3, REG(insn, 0), opsize, - NULL_QREG, NULL, EA_LOADS); + NULL_QREG, NULL, EA_LOADS, IS_USER(s)); /* Post-increment load (mode 3) from Ax. */ dst =3D gen_ea_mode(env, s, 3, REG(insn, 9), opsize, - NULL_QREG, NULL, EA_LOADS); + NULL_QREG, NULL, EA_LOADS, IS_USER(s)); =20 gen_update_cc_cmp(s, dst, src, opsize); } @@ -3290,15 +3295,15 @@ DISAS_INSN(addx_mem) =20 addr_src =3D AREG(insn, 0); tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize)); - src =3D gen_load(s, opsize, addr_src, 1); + src =3D gen_load(s, opsize, addr_src, 1, IS_USER(s)); =20 addr_dest =3D AREG(insn, 9); tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize)); - dest =3D gen_load(s, opsize, addr_dest, 1); + dest =3D gen_load(s, opsize, addr_dest, 1, IS_USER(s)); =20 gen_addx(s, src, dest, opsize); =20 - gen_store(s, opsize, addr_dest, QREG_CC_N); + gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s)); } =20 static inline void shift_im(DisasContext *s, uint16_t insn, int opsize) @@ -4328,9 +4333,9 @@ DISAS_INSN(chk2) addr2 =3D tcg_temp_new(); tcg_gen_addi_i32(addr2, addr1, opsize_bytes(opsize)); =20 - bound1 =3D gen_load(s, opsize, addr1, 1); + bound1 =3D gen_load(s, opsize, addr1, 1, IS_USER(s)); tcg_temp_free(addr1); - bound2 =3D gen_load(s, opsize, addr2, 1); + bound2 =3D gen_load(s, opsize, addr2, 1, IS_USER(s)); tcg_temp_free(addr2); =20 reg =3D tcg_temp_new(); @@ -4843,7 +4848,8 @@ DISAS_INSN(fpu) case 3: /* fmove out */ cpu_src =3D gen_fp_ptr(REG(ext, 7)); opsize =3D ext_opsize(ext, 10); - if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_STORE) =3D=3D -1) { + if (gen_ea_fp(env, s, insn, opsize, cpu_src, + EA_STORE, IS_USER(s)) =3D=3D -1) { gen_addr_fault(s); } gen_helper_ftst(cpu_env, cpu_src); @@ -4865,7 +4871,8 @@ DISAS_INSN(fpu) /* Source effective address. */ opsize =3D ext_opsize(ext, 10); cpu_src =3D gen_fp_result_ptr(); - if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_LOADS) =3D=3D -1) { + if (gen_ea_fp(env, s, insn, opsize, cpu_src, + EA_LOADS, IS_USER(s)) =3D=3D -1) { gen_addr_fault(s); return; } @@ -5264,7 +5271,7 @@ DISAS_INSN(mac) tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); /* Load the value now to ensure correct exception behavior. Perform writeback after reading the MAC inputs. */ - loadval =3D gen_load(s, OS_LONG, addr, 0); + loadval =3D gen_load(s, OS_LONG, addr, 0, IS_USER(s)); =20 acc ^=3D 1; rx =3D (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); --=20 2.14.3