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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.09 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=W1Ymh+4pKR0f40mVJ3TI2zd9pktGvqRjYsVLc8R5trk=; b=bFA0dOtjhb217eGh4AH7QdNUrfsXH8AUOkOjKhGdYbJdL/RgT7cGFdGWqyebEw6KTd ydTK100C0zn3P9qbumI84XYC9dCTVtZOyoTcYoLY2NzhsqY5ZFDlir4hjzoE5cdIpLEJ Y8Bx0Mi+fYUf+vUYGlCi+l77SWrIQBCsNN9uw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=W1Ymh+4pKR0f40mVJ3TI2zd9pktGvqRjYsVLc8R5trk=; b=mpU4sl0d9Mh48fw8yHd7ItXlt+4CXGUcTyacEUGga/XLRTnMT+WxwjZ9Nerd7ky5BT w6uLMTjZQK8oPHEdwUIr3JQRrKddy4ipNl9PGmGU2BMpz88V9eZOQIHaC4S76/i1tpa4 B0w+a/8AbNJyi3v+W3M70+SgksFVeDAmYgcBdyKK6vddPUf2YM/8jQiy9/fupCI0OxQl tn3TMOxVqyojtuBkgTKPoQzksOiXKi5tINraCMdsiel45+GkdfRMSeTbOAhbafvDX6TQ vJRrRK5vuUIsuK9sEtl78I6SxtWDJX5bfEjPGm0TOaZtssLoMBbdXTipWnLXojeKHAEu w2KA== X-Gm-Message-State: AKwxytdFlLqUXEX+3HmRv/Gz0+MRu+eHUGZas6b93R4GctYtKssAtF8j hAKOJ0I6BbGo+jLnwTwYJ+H69DOBGlg= X-Google-Smtp-Source: AH8x227WiUTDTWAFV7H50jI4hKQnGOxcKcaoElhNiutNfxPUCz6LJeD9bTjK8G6BWdZeax3OXyO99g== X-Received: by 10.98.205.72 with SMTP id o69mr11930138pfg.104.1516836430830; Wed, 24 Jan 2018 15:27:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:08 -0800 Message-Id: <20180124232625.30105-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 28/45] target/hppa: Optimize for flat addressing space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Linux sets sr4-sr7 all to the same value, which means that we need not do any runtime computation to find out what space to use in forming the GVA. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 11 ++++++++++- target/hppa/translate.c | 29 ++++++++++++++++++++--------- 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index a6e4091b6a..57e0bd6f0e 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -282,7 +282,11 @@ static inline target_ulong hppa_form_gva(CPUHPPAState = *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } =20 -/* Since PSW_CB will never need to be in tb->flags, reuse them. */ +/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. + * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the + * same value. + */ +#define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 =20 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *p= c, @@ -318,6 +322,11 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *= env, target_ulong *pc, *cs_base |=3D (uint32_t)diff; } } + if ((env->sr[4] =3D=3D env->sr[5]) + & (env->sr[4] =3D=3D env->sr[6]) + & (env->sr[4] =3D=3D env->sr[7])) { + flags |=3D TB_FLAG_SR_SAME; + } #endif =20 *pflags =3D flags; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8c1ae4db78..24d357889e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -284,6 +284,7 @@ typedef struct DisasContext { TCGLabel *null_lab; =20 uint32_t insn; + uint32_t tb_flags; int mmu_idx; int privilege; bool psw_n_nonzero; @@ -323,6 +324,7 @@ typedef struct DisasInsn { /* global register indexes */ static TCGv_reg cpu_gr[32]; static TCGv_i64 cpu_sr[4]; +static TCGv_i64 cpu_srH; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; static TCGv_i64 cpu_iasq_f; @@ -360,8 +362,8 @@ void hppa_translate_init(void) "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; /* SR[4-7] are not global registers so that we can index them. */ - static const char sr_names[4][4] =3D { - "sr0", "sr1", "sr2", "sr3" + static const char sr_names[5][4] =3D { + "sr0", "sr1", "sr2", "sr3", "srH" }; =20 int i; @@ -377,6 +379,9 @@ void hppa_translate_init(void) offsetof(CPUHPPAState, sr[i]), sr_names[i]); } + cpu_srH =3D tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, sr[4]), + sr_names[4]); =20 for (i =3D 0; i < ARRAY_SIZE(vars); ++i) { const GlobalVar *v =3D &vars[i]; @@ -604,6 +609,8 @@ static void load_spr(DisasContext *ctx, TCGv_i64 dest, = unsigned reg) #else if (reg < 4) { tcg_gen_mov_i64(dest, cpu_sr[reg]); + } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { + tcg_gen_mov_i64(dest, cpu_srH); } else { tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); } @@ -1362,6 +1369,9 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) load_spr(ctx, spc, sp); return spc; } + if (ctx->tb_flags & TB_FLAG_SR_SAME) { + return cpu_srH; + } =20 ptr =3D tcg_temp_new_ptr(); tmp =3D tcg_temp_new(); @@ -1405,7 +1415,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva= , TCGv_reg *pofs, #else TCGv_tl addr =3D get_temp_tl(ctx); tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); - if (ctx->base.tb->flags & PSW_W) { + if (ctx->tb_flags & PSW_W) { tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); } if (!is_phys) { @@ -2112,6 +2122,7 @@ static DisasJumpType trans_mtsp(DisasContext *ctx, ui= nt32_t insn, =20 if (rs >=3D 4) { tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); + ctx->tb_flags &=3D ~TB_FLAG_SR_SAME; } else { tcg_gen_mov_i64(cpu_sr[rs], t64); } @@ -2407,7 +2418,7 @@ static DisasJumpType trans_ixtlbx(DisasContext *ctx, = uint32_t insn, =20 /* Exit TB for ITLB change if mmu is enabled. This *should* not be the case, since the OS TLB fill handler runs with mmu disabled. */ - return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + return nullify_end(ctx, !is_data && (ctx->tb_flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } =20 @@ -2443,7 +2454,7 @@ static DisasJumpType trans_pxtlbx(DisasContext *ctx, = uint32_t insn, } =20 /* Exit TB for TLB change if mmu is enabled. */ - return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + return nullify_end(ctx, !is_data && (ctx->tb_flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } =20 @@ -4556,6 +4567,7 @@ static int hppa_tr_init_disas_context(DisasContextBas= e *dcbase, int bound; =20 ctx->cs =3D cs; + ctx->tb_flags =3D ctx->base.tb->flags; =20 #ifdef CONFIG_USER_ONLY ctx->privilege =3D MMU_USER_IDX; @@ -4563,9 +4575,8 @@ static int hppa_tr_init_disas_context(DisasContextBas= e *dcbase, ctx->iaoq_f =3D ctx->base.pc_first; ctx->iaoq_b =3D ctx->base.tb->cs_base; #else - ctx->privilege =3D (ctx->base.tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; - ctx->mmu_idx =3D (ctx->base.tb->flags & PSW_D - ? ctx->privilege : MMU_PHYS_IDX); + ctx->privilege =3D (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; + ctx->mmu_idx =3D (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_ID= X); =20 /* Recover the IAOQ values from the GVA + PRIV. */ uint64_t cs_base =3D ctx->base.tb->cs_base; @@ -4597,7 +4608,7 @@ static void hppa_tr_tb_start(DisasContextBase *dcbase= , CPUState *cs) /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. = */ ctx->null_cond =3D cond_make_f(); ctx->psw_n_nonzero =3D false; - if (ctx->base.tb->flags & PSW_N) { + if (ctx->tb_flags & PSW_N) { ctx->null_cond.c =3D TCG_COND_ALWAYS; ctx->psw_n_nonzero =3D true; } --=20 2.14.3