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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.59 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=syJ0GoJ+f8WMWrwcEiicvHb0HU1xqjyXCwDF8fegEPk=; b=RRSdKFHJ3KtTcB402j5FKgTcsTRSOxWgw6OnEq59VvujFKsp9wggmSMRf8wgFqiXtJ b3JoYb4NmTDiei0OPxEA5O14jdQrnzRtxks5Bb6oxb77Froz5D0WyaEwL8re+beuccrR MCfjzhBcdoNFpLzqKmhVI6iKR4h60wprXK4Jo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=syJ0GoJ+f8WMWrwcEiicvHb0HU1xqjyXCwDF8fegEPk=; b=iOeJed81MS6m0GHBe5Yl9Q45GSHN9XZ4LTBbF8fAsdNVK3Yddkj+F6dokStctbqotI igqbJsd6ni8frCrx8duIUv44xlYojYygyuK/ttHX3Y2nkcoleJIYZMbsoqA3tDOSBu16 Tu7uLXWe090zsRjBwWHeecZC5qA4Mzlnkyi45ZfBgxpUD+SZj36RbopeflOXLWjVjwab ARe7VxMhw1exsuhNAMgcju+YmWjzy7RaFWDfhTjIjZ8eDRPHxsfb6BAEGU8b25QsqRmz Og3YRs/q0SrkmsPjYSqIoKJLkapCK7jwzsxXYvhzufcoRPbym4XoqVIvBqK9aQUIK6+C xJcQ== X-Gm-Message-State: AKwxytfJBdBM+GIqm76+iWXz0OuVRNZ3dFn8C80YqNlU8Drc8zx13OzF s8chIBaXxqzzLzz/xYW3uIxS1oaZKZc= X-Google-Smtp-Source: AH8x2248ynwvyjPJ5LOfQsamug66/31mxnX0+xMqz+7BbqnJEQn3RsMXOryDEz6J426hO0cAA/qljg== X-Received: by 10.99.127.24 with SMTP id a24mr11758319pgd.225.1516836420673; Wed, 24 Jan 2018 15:27:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:26:02 -0800 Message-Id: <20180124232625.30105-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 22/45] target/hppa: Implement P*TLB and P*TLBE insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We now have all of the TLB manipulation instructions. Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/mem_helper.c | 37 +++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index d412093914..f059ddf3b9 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -88,4 +88,6 @@ DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env= , tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr) DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 7c3c7d1415..2835d890f2 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -270,4 +270,41 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong add= r, target_ureg reg) ent->t =3D extract32(reg, 29, 1); ent->entry_valid =3D 1; } + +/* Purge (Insn/Data) TLB. This is explicitly page-based, and is + synchronous across all processors. */ +static void ptlb_work(CPUState *cpu, run_on_cpu_data data) +{ + CPUHPPAState *env =3D cpu->env_ptr; + target_ulong addr =3D (target_ulong) data.target_ptr; + hppa_tlb_entry *ent =3D hppa_find_tlb(env, addr); + + if (ent && ent->entry_valid) { + hppa_flush_tlb_ent(env, ent); + } +} + +void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) +{ + CPUState *src =3D CPU(hppa_env_get_cpu(env)); + CPUState *cpu; + run_on_cpu_data data =3D RUN_ON_CPU_TARGET_PTR(addr); + + CPU_FOREACH(cpu) { + if (cpu !=3D src) { + async_run_on_cpu(cpu, ptlb_work, data); + } + } + async_safe_run_on_cpu(src, ptlb_work, data); +} + +/* Purge (Insn/Data) TLB entry. This affects an implementation-defined + number of pages/entries (we choose all), and is local to the cpu. */ +void HELPER(ptlbe)(CPUHPPAState *env) +{ + CPUState *src =3D CPU(hppa_env_get_cpu(env)); + + memset(env->tlb, 0, sizeof(env->tlb)); + tlb_flush_by_mmuidx(src, 0xf); +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c02d107041..5b77688fc0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2397,6 +2397,42 @@ static DisasJumpType trans_ixtlbx(DisasContext *ctx,= uint32_t insn, return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } + +static DisasJumpType trans_pxtlbx(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned m =3D extract32(insn, 5, 1); + unsigned sp; + unsigned rx =3D extract32(insn, 16, 5); + unsigned rb =3D extract32(insn, 21, 5); + unsigned is_data =3D insn & 0x1000; + unsigned is_local =3D insn & 0x40; + TCGv_tl addr; + TCGv_reg ofs; + + if (is_data) { + sp =3D extract32(insn, 14, 2); + } else { + sp =3D ~assemble_sr3(insn); + } + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + form_gva(ctx, &addr, &ofs, rb, rx, 0, 0, sp, m, false); + if (m) { + save_gpr(ctx, rb, ofs); + } + if (is_local) { + gen_helper_ptlbe(cpu_env); + } else { + gen_helper_ptlb(cpu_env, addr); + } + + /* Exit TB for TLB change if mmu is enabled. */ + return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + ? DISAS_IAQ_N_STALE : DISAS_NEXT); +} #endif /* !CONFIG_USER_ONLY */ =20 static const DisasInsn table_mem_mgmt[] =3D { @@ -2420,6 +2456,10 @@ static const DisasInsn table_mem_mgmt[] =3D { { 0x04000040u, 0xfc001fffu, trans_ixtlbx }, /* iitlba */ { 0x04001000u, 0xfc001fffu, trans_ixtlbx }, /* idtlbp */ { 0x04001040u, 0xfc001fffu, trans_ixtlbx }, /* idtlba */ + { 0x04000200u, 0xfc001fdfu, trans_pxtlbx }, /* pitlb */ + { 0x04000240u, 0xfc001fdfu, trans_pxtlbx }, /* pitlbe */ + { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ + { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ #endif }; =20 --=20 2.14.3