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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.26.55 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:26:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=3QgQ3aTosAcrqniuf2FzQ9ncn1tfTZjIHIuTzT3AMPw=; b=B3Ud02GCV3RJw4F8OdHaNjP5U6ibt3T1t2Yh7dlPcbRJkKo2d+PjlGEfTm3p0Uz4nC seUOa1Mt4uaEVqaY3aTa2Xobv5hHkROKyeOcf6zYfRfEikXT9gOK6i0OsgCrgPhdA5LI bdQQbOBuXf0p2UzAiNmO0ejsxa1dFCbW+j2uM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=3QgQ3aTosAcrqniuf2FzQ9ncn1tfTZjIHIuTzT3AMPw=; b=c/cAbhB3tBPRa5eeKiEnz6QUKNIg2BEZI3Z1yitM3bS+Z14DYjcp76IXbIX+5GjjP0 mKhrEvRfPtBRXU8Vl0JT3AShKPysQl/F15X/DkDaTlT4Cghqr1SsS4QvpCtf08UxiPgg auTvgQXiEx3xxU2f93teg/GIhqpWwYktGZ8n4z1cw0MVH2gocoaPqJEpKA5kOFto4PQe xxck8RRN6ADDqESZ6IzjjpzIQCaacciQCDpDOwkFVSn8mcmnbmPQVMe7yiEDNLrIUaHm wIog5XvR0u4mShVTfH7GFUD11tl3FngJiVR3bec3rEn+cMT18Jl6ZSrwbKrqrQH6Got9 5vhQ== X-Gm-Message-State: AKwxytfA6smPp6Zd6/VzwJk7nccJewek0i4Q6GrOHKhZK08pc1CpFVvF WaQ7b1sP0dtSw78Hj6S/MXQnzB+JZqY= X-Google-Smtp-Source: AH8x2266wD8vt0g0lXv44EvSFy/4J+uhT8sErktVcQMwa1/azL2rslNllPuVg7NcZEhkaLEU2hJV4w== X-Received: by 2002:a17:902:7244:: with SMTP id c4-v6mr9965185pll.414.1516836416308; Wed, 24 Jan 2018 15:26:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Jan 2018 15:25:59 -0800 Message-Id: <20180124232625.30105-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 19/45] target/hppa: Implement the interval timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 ++ target/hppa/helper.h | 3 +++ target/hppa/cpu.c | 8 ++++++++ target/hppa/int_helper.c | 6 ++++++ target/hppa/op_helper.c | 36 ++++++++++++++++++++++++++++++++++++ target/hppa/translate.c | 16 ++++++++++++---- 6 files changed, 67 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fc3e62c0af..31a3702684 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -234,6 +234,7 @@ struct HPPACPU { /*< public >*/ =20 CPUHPPAState env; + QEMUTimer *alarm_timer; }; =20 static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) @@ -341,6 +342,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int rw, int midx); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *ppro= t); extern const MemoryRegionOps hppa_io_eir_ops; +void hppa_cpu_alarm_timer(void *); #endif =20 #endif /* HPPA_CPU_H */ diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 535f086ab4..744b11cb66 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -77,9 +77,12 @@ DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, en= v, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) =20 +DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr) + #ifndef CONFIG_USER_ONLY DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) +DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 888a48f16d..6be6eb0a7b 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -99,6 +99,14 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error *= *errp) =20 qemu_init_vcpu(cs); acc->parent_realize(dev, errp); + +#ifndef CONFIG_USER_ONLY + { + HPPACPU *cpu =3D HPPA_CPU(cs); + cpu->alarm_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + hppa_cpu_alarm_timer, cpu); + } +#endif } =20 /* Sort hppabetically by type name. */ diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 249e14a2a1..d54d830196 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -67,6 +67,12 @@ const MemoryRegionOps hppa_io_eir_ops =3D { .impl.max_access_size =3D 4, }; =20 +void hppa_cpu_alarm_timer(void *opaque) +{ + /* Raise interrupt 0. */ + io_eir_write(opaque, 0, 0, 4); +} + void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) { env->cr[CR_EIRR] &=3D ~val; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 1963b2439b..6d19cab6c9 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -22,6 +22,8 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" +#include "qemu/timer.h" + =20 void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) { @@ -602,7 +604,41 @@ float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64= a, float64 b, float64 c) return ret; } =20 +target_ureg HELPER(read_interval_timer)(void) +{ +#ifdef CONFIG_USER_ONLY + /* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist. + Just pass through the host cpu clock ticks. */ + return cpu_get_host_ticks(); +#else + /* In system mode we have access to a decent high-resolution clock. + In order to make OS-level time accounting work with the cr16, + present it with a well-timed clock fixed at 250MHz. */ + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2; +#endif +} + #ifndef CONFIG_USER_ONLY +void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val) +{ + HPPACPU *cpu =3D hppa_env_get_cpu(env); + uint64_t current =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t timeout; + + /* Even in 64-bit mode, the comparator is always 32-bit. But the + value we expose to the guest is 1/4 of the speed of the clock, + so moosh in 34 bits. */ + timeout =3D deposit64(current, 0, 34, (uint64_t)val << 2); + + /* If the mooshing puts the clock in the past, advance to next round. = */ + if (timeout < current + 1000) { + timeout +=3D 1ULL << 34; + } + + cpu->env.cr[CR_IT] =3D timeout; + timer_mod(cpu->alarm_timer, timeout); +} + target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) { target_ulong psw =3D env->psw; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d6c65f314b..1cd57f5a90 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2038,6 +2038,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, u= int32_t insn, unsigned rt =3D extract32(insn, 0, 5); unsigned ctl =3D extract32(insn, 21, 5); TCGv_reg tmp; + DisasJumpType ret; =20 switch (ctl) { case CR_SAR: @@ -2056,9 +2057,17 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, = uint32_t insn, /* FIXME: Respect PSW_S bit. */ nullify_over(ctx); tmp =3D dest_gpr(ctx, rt); - tcg_gen_movi_reg(tmp, 0); /* FIXME */ + if (ctx->base.tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + gen_helper_read_interval_timer(tmp); + gen_io_end(); + ret =3D DISAS_IAQ_N_STALE; + } else { + gen_helper_read_interval_timer(tmp); + ret =3D DISAS_NEXT; + } save_gpr(ctx, rt, tmp); - break; + return nullify_end(ctx, ret); case 26: case 27: break; @@ -2132,9 +2141,8 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, u= int32_t insn, nullify_over(ctx); switch (ctl) { case CR_IT: - /* ??? modify interval timer offset */ + gen_helper_write_interval_timer(cpu_env, reg); break; - case CR_EIRR: gen_helper_write_eirr(cpu_env, reg); break; --=20 2.14.3