From nobody Wed Apr 16 12:17:15 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516716466219204.02141688871598; Tue, 23 Jan 2018 06:07:46 -0800 (PST) Received: from localhost ([::1]:59739 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edzEn-0007Id-Cr for importer@patchew.org; Tue, 23 Jan 2018 09:07:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57594) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edz9e-0003NQ-MF for qemu-devel@nongnu.org; Tue, 23 Jan 2018 09:02:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edz9Y-0005k6-Jb for qemu-devel@nongnu.org; Tue, 23 Jan 2018 09:02:26 -0500 Received: from mx1.redhat.com ([209.132.183.28]:41232) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1edz9O-0005cC-T6; Tue, 23 Jan 2018 09:02:11 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EF82C99DA1; Tue, 23 Jan 2018 14:02:09 +0000 (UTC) Received: from localhost.localdomain.com (ovpn-117-26.ams2.redhat.com [10.36.117.26]) by smtp.corp.redhat.com (Postfix) with ESMTP id C44768517; Tue, 23 Jan 2018 14:02:08 +0000 (UTC) From: Kevin Wolf To: qemu-block@nongnu.org Date: Tue, 23 Jan 2018 15:01:34 +0100 Message-Id: <20180123140201.31163-3-kwolf@redhat.com> In-Reply-To: <20180123140201.31163-1-kwolf@redhat.com> References: <20180123140201.31163-1-kwolf@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 23 Jan 2018 14:02:10 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 02/29] hw/block: Fix pin-based interrupt behaviour of NVMe X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kwolf@redhat.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Hikaru Nishida Pin-based interrupt of NVMe controller did not work properly because using an obsolated function pci_irq_pulse(). To fix this, change to use pci_irq_assert() / pci_irq_deassert() instead of pci_irq_pulse(). Signed-off-by: Hikaru Nishida Reviewed-by: Keith Busch Signed-off-by: Kevin Wolf --- hw/block/nvme.h | 1 + hw/block/nvme.c | 39 ++++++++++++++++++++++++++++++++++----- 2 files changed, 35 insertions(+), 5 deletions(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 6aab338ff5..7b62dad072 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -775,6 +775,7 @@ typedef struct NvmeCtrl { uint32_t cmbsz; uint32_t cmbloc; uint8_t *cmbuf; + uint64_t irq_status; =20 char *serial; NvmeNamespace *namespaces; diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 1ac356d3a5..51a58fefba 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -91,7 +91,19 @@ static uint8_t nvme_sq_empty(NvmeSQueue *sq) return sq->head =3D=3D sq->tail; } =20 -static void nvme_isr_notify(NvmeCtrl *n, NvmeCQueue *cq) +static void nvme_irq_check(NvmeCtrl *n) +{ + if (msix_enabled(&(n->parent_obj))) { + return; + } + if (~n->bar.intms & n->irq_status) { + pci_irq_assert(&n->parent_obj); + } else { + pci_irq_deassert(&n->parent_obj); + } +} + +static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq) { if (cq->irq_enabled) { if (msix_enabled(&(n->parent_obj))) { @@ -99,13 +111,28 @@ static void nvme_isr_notify(NvmeCtrl *n, NvmeCQueue *c= q) msix_notify(&(n->parent_obj), cq->vector); } else { trace_nvme_irq_pin(); - pci_irq_pulse(&n->parent_obj); + assert(cq->cqid < 64); + n->irq_status |=3D 1 << cq->cqid; + nvme_irq_check(n); } } else { trace_nvme_irq_masked(); } } =20 +static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq) +{ + if (cq->irq_enabled) { + if (msix_enabled(&(n->parent_obj))) { + return; + } else { + assert(cq->cqid < 64); + n->irq_status &=3D ~(1 << cq->cqid); + nvme_irq_check(n); + } + } +} + static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVector *iov, uint64_t = prp1, uint64_t prp2, uint32_t len, NvmeCtrl *n) { @@ -242,7 +269,7 @@ static void nvme_post_cqes(void *opaque) sizeof(req->cqe)); QTAILQ_INSERT_TAIL(&sq->req_list, req, entry); } - nvme_isr_notify(n, cq); + nvme_irq_assert(n, cq); } =20 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req) @@ -905,6 +932,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, = uint64_t data, n->bar.intmc =3D n->bar.intms; trace_nvme_mmio_intm_set(data & 0xffffffff, n->bar.intmc); + nvme_irq_check(n); break; case 0x10: /* INTMC */ if (unlikely(msix_enabled(&(n->parent_obj)))) { @@ -917,6 +945,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, = uint64_t data, n->bar.intmc =3D n->bar.intms; trace_nvme_mmio_intm_clr(data & 0xffffffff, n->bar.intmc); + nvme_irq_check(n); break; case 0x14: /* CC */ trace_nvme_mmio_cfg(data & 0xffffffff); @@ -1085,8 +1114,8 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 5= 00); } =20 - if (cq->tail !=3D cq->head) { - nvme_isr_notify(n, cq); + if (cq->tail =3D=3D cq->head) { + nvme_irq_deassert(n, cq); } } else { /* Submission queue doorbell write */ --=20 2.13.6