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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id t1sm3444680pfj.21.2018.01.22.19.53.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jan 2018 19:53:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aOP5CpWP51onl5Hzyvxgad3yYqWLQMfjilJrKFLiPkU=; b=BdqCt9NhofwJ7TCkTSw1tax0ch18dFc6/if3K4t5ZAi70jElowF5AIb/NllHvBN1TN cOcQwggf2/xGq2j/v9QmX6pF6uVLNjGM19ArKX+FAQJ4HwMywmeURvyc5ArSCcj7v0IX hm7McGVKK6dFmI1tf3zVf02gIJV0kZjo7Z1tk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aOP5CpWP51onl5Hzyvxgad3yYqWLQMfjilJrKFLiPkU=; b=PLLKQhYy9Kkx2CN3/cpg560yCaMdG+Y+7ehVXt2rKFmp3XyDrr8OrAndDhMOoVr6Z6 VD4D41t7DHzf6e5f0yLON0LnHZBQ6M6p0GAlUUX7Pv1ckFDVF0drcIQGm8Dvix9Ul2qG h/4plYRzwC+3lvC17OvTRf83yPj9/fN0vy4JRg1qzz3Q4wfXTLMnNDd+HWjKI6tfhq2r 1H09ov0mwlqmm/JJ/BJ/BnpcyGFgWqX222NFMuPRz9TEOG63W2DfTiwwFHAWcZXBhOB+ Oxp1xpdu/eHkfLCTtCySA3DY0IS4OgfU2L1epGqKmKonKaKWO0QxH68SHAmU9kLhLkPI rC/w== X-Gm-Message-State: AKwxytf3Xf30ilMS7a2ejVjwK4tGPqbpuZMaCr62biAzrQmAVOh8zm3R 9ZzUeVrvW2pM4GjjZfUpHu0HA/KxtHk= X-Google-Smtp-Source: AH8x224W4n+RUMJxZ0QiR7TwG9lffccJR/18TZs1RP0rfh5sA2d7++2+/tiLDUCliNqAkcvcl+p90Q== X-Received: by 10.99.151.2 with SMTP id n2mr5791489pge.87.1516679639854; Mon, 22 Jan 2018 19:53:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 22 Jan 2018 19:53:49 -0800 Message-Id: <20180123035349.24538-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180123035349.24538-1-richard.henderson@linaro.org> References: <20180123035349.24538-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 5/5] target/arm: Add SVE state to TB->FLAGS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add both SVE exception state and vector length. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 8 ++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 25 ++++++++++++++++++++++++- target/arm/translate-a64.c | 2 ++ 4 files changed, 36 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 17955ad3ef..a311d4e327 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2648,6 +2648,10 @@ static inline bool arm_cpu_data_is_big_endian(CPUARM= State *env) #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) +#define ARM_TBFLAG_SVEEXC_EL_SHIFT 2 +#define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) +#define ARM_TBFLAG_ZCR_LEN_SHIFT 4 +#define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) =20 /* some convenience accessor macros */ #define ARM_TBFLAG_AARCH64_STATE(F) \ @@ -2684,6 +2688,10 @@ static inline bool arm_cpu_data_is_big_endian(CPUARM= State *env) (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) #define ARM_TBFLAG_TBI1(F) \ (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) +#define ARM_TBFLAG_SVEEXC_EL(F) \ + (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) +#define ARM_TBFLAG_ZCR_LEN(F) \ + (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index 3f4df91e5e..c47febf99d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -29,6 +29,8 @@ typedef struct DisasContext { bool tbi1; /* TBI1 for EL0/1, not used for EL2/3 */ bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ + int sve_excp_el; /* SVE exception EL or 0 if enabled */ + int sve_len; /* SVE vector length in bytes */ /* Flag indicating that exceptions from secure mode are routed to EL3.= */ bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ diff --git a/target/arm/helper.c b/target/arm/helper.c index db67e8ac72..d46d3622fc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11823,14 +11823,37 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + int fp_el =3D fp_exception_el(env); uint32_t flags; =20 if (is_a64(env)) { + int sve_el =3D sve_exception_el(env); + uint32_t zcr_len; + *pc =3D env->pc; flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; /* Get control bits for tagged addresses */ flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT= ); flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT= ); + flags |=3D sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT; + + /* If SVE is disabled, but FP is enabled, + then the effective len is 0. */ + if (sve_el !=3D 0 && fp_el =3D=3D 0) { + zcr_len =3D 0; + } else { + int current_el =3D arm_current_el(env); + + zcr_len =3D env->vfp.zcr_el[current_el <=3D 1 ? 1 : current_el= ]; + zcr_len &=3D 0xf; + if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2= ]); + } + if (current_el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3= ]); + } + } + flags |=3D zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT; } else { *pc =3D env->regs[15]; flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) @@ -11873,7 +11896,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (arm_cpu_data_is_big_endian(env)) { flags |=3D ARM_TBFLAG_BE_DATA_MASK; } - flags |=3D fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; + flags |=3D fp_el << ARM_TBFLAG_FPEXC_EL_SHIFT; =20 if (arm_v7m_is_handler_mode(env)) { flags |=3D ARM_TBFLAG_HANDLER_MASK; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 10eef870fe..4c1eca7062 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11263,6 +11263,8 @@ static int aarch64_tr_init_disas_context(DisasConte= xtBase *dcbase, dc->user =3D (dc->current_el =3D=3D 0); #endif dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); + dc->sve_excp_el =3D ARM_TBFLAG_SVEEXC_EL(dc->base.tb->flags); + dc->sve_len =3D (ARM_TBFLAG_ZCR_LEN(dc->base.tb->flags) + 1) * 16; dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.14.3