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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id t1sm3444680pfj.21.2018.01.22.19.53.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jan 2018 19:53:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rtUJek3aPDGG5LW/JtqEYY8tEezLcf4E59P/pioBFKI=; b=PKa2a16/TMZ8XwergD5sZp/vzIA7Cjb4+OArfZMAjiVPkX2RW6mS0+Onie2u3XK2YB RBQ5yzKrMxLWZbFndOS/9X2F+nmDrqQRyLxrXKuLfvT1KMDDWcMAdJR3r97vpy66UAHO DAMsVEx04lO1WmRFPZGnKPROiq122dDchZaW4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rtUJek3aPDGG5LW/JtqEYY8tEezLcf4E59P/pioBFKI=; b=hctbg4tehkLSlPHAIfbJcjfb5KyvEkhQgfZ7IbjR2LbawWG3fB319hBQgt85D843iV 6zW0n1NBmYzXMFzxBGBql3bC+pLYgtHuaQQq/avWZl1VwC4tLJLUDQAW3ZR9/G+Z52YA y4H6J+yXL9TIIyetWEQ8LKXgdOfMbHR/eqSRAGY/EwGkNWLEqI1mZzaAHO9du4zhYHoi QXLvamYeZ2w8PLnMLSMDqSDiqn0wYX0cCAszuSxuxA+eHpjOSUiEnCyBD+Xv2MW1x7aT yUwMGgDVGSYd3ftQ+gVDaT+lPXzOLYO2V0pNKsrbqrJhSbLK7/IHLGX6AhUG9/qeJ4E/ qeAQ== X-Gm-Message-State: AKwxyteW6dJ/MpoZra0FEp/KTdSMnLf5zLUQ04jDBBI2BbWzv6Cnsfoy /wadHjBxEdca/GxEarSMmKYjd8t5FBc= X-Google-Smtp-Source: AH8x226t27zZA7SHbv+NC322xOxuTBnwWobJLJnTnbWPYkUb6IMNgrypYkzAiVx8gxvacegixnOFkw== X-Received: by 10.99.112.81 with SMTP id a17mr8201317pgn.293.1516679636953; Mon, 22 Jan 2018 19:53:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 22 Jan 2018 19:53:47 -0800 Message-Id: <20180123035349.24538-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180123035349.24538-1-richard.henderson@linaro.org> References: <20180123035349.24538-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 3/5] target/arm: Add SVE to migration state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Save the high parts of the Zregs and all of the Pregs. The ZCR_ELx registers are migrated via the CP mechanism. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- target/arm/machine.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 53 insertions(+) diff --git a/target/arm/machine.c b/target/arm/machine.c index cb0e1c92bb..2c8b43062f 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -122,6 +122,56 @@ static const VMStateDescription vmstate_iwmmxt =3D { } }; =20 +#ifdef TARGET_AARCH64 +/* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, + * and ARMPredicateReg is actively empty. This triggers errors + * in the expansion of the VMSTATE macros. + */ + +static bool sve_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_SVE); +} + +/* The first two words of each Zreg is stored in VFP state. */ +static const VMStateDescription vmstate_zreg_hi_reg =3D { + .name =3D "cpu/sve/zreg_hi", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_preg_reg =3D { + .name =3D "cpu/sve/preg", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_sve =3D { + .name =3D "cpu/sve", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D sve_needed, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, + vmstate_zreg_hi_reg, ARMVectorReg), + VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, + vmstate_preg_reg, ARMPredicateReg), + VMSTATE_END_OF_LIST() + } +}; +#endif /* AARCH64 */ + static bool m_needed(void *opaque) { ARMCPU *cpu =3D opaque; @@ -586,6 +636,9 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_pmsav7, &vmstate_pmsav8, &vmstate_m_security, +#ifdef TARGET_AARCH64 + &vmstate_sve, +#endif NULL } }; --=20 2.14.3