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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id t1sm3444680pfj.21.2018.01.22.19.53.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jan 2018 19:53:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j5ZzFe9v1seJM10ejjq7LnkqZkzsXk5giC+K0+xGnVc=; b=Ed8LJlk6PR/1hL3FhoAdyYapJn0blJ8/Mj8TPSnIgrDwvJPkF1Dt8oYicvaOHD8lJb iLt2nUHUQix4IJqCt1AjvU4Kj332USpPxVWnskNtkSM2tDbvUM8X05uQuTBwyolAk+No Nr7nHCMrNCV+/hmDmDgYnJN+tpHMsSKPlM+p4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j5ZzFe9v1seJM10ejjq7LnkqZkzsXk5giC+K0+xGnVc=; b=uMFwoR/VyRT6NL0Caqg/WvLFecmsm1O0iMVs0I5P1EF8Pn+/LifmOR6DgtkkTZ/Jsq 9osxSbddsftB1awiawV85BXycpb4oWOSgAQ4tF+dQpcxyPLgdyQR/EMv3Cs5x1TjxLvN c/e2ZdgTi9MQFbCTEg5YvMRObx1DAVXu+RjQxEBYFHnIYxgo9VctnkrTCJ4LXZc8w5D8 8cmyjK7qi5FQq+Xw0iezIkHVJXg7Wjcwsy1QUWQnmLjJtLtMGi+OLrWyov7sqzzyc8HG 8QBNKJABXht2YmiTUVImhivn2PlQvLNzvPzjzZtOo3bV0JN6nBumUc/VBxhh+G+xPg8F a0hg== X-Gm-Message-State: AKwxytcq5sqcIekyuB2MYnmUFtgbVzNpNPEq1/3qEZ+PKkXd2Pm8DWkF upO3hDRm94bea7oZYSQYJpuIY3ZHwVk= X-Google-Smtp-Source: AH8x224Ba0yqrIYGFp+jJYSajPHNTPFPMSod+CSTUm1LUcXi9IASQXX24P2r4eSqZUGHgZVl5jF64Q== X-Received: by 2002:a17:902:f:: with SMTP id 15-v6mr4474291pla.419.1516679635543; Mon, 22 Jan 2018 19:53:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 22 Jan 2018 19:53:46 -0800 Message-Id: <20180123035349.24538-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180123035349.24538-1-richard.henderson@linaro.org> References: <20180123035349.24538-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3 2/5] target/arm: Add predicate registers for SVE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1854fe51a8..3f4f6b6144 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -188,6 +188,13 @@ typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; =20 +/* In AArch32 mode, predicate registers do not exist at all. */ +#ifdef TARGET_AARCH64 +typedef struct ARMPredicateReg { + uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); +} ARMPredicateReg; +#endif + =20 typedef struct CPUARMState { /* Regs for current mode. */ @@ -515,6 +522,11 @@ typedef struct CPUARMState { struct { ARMVectorReg zregs[32]; =20 +#ifdef TARGET_AARCH64 + /* Store FFR as pregs[16] to make it easier to treat as any other.= */ + ARMPredicateReg pregs[17]; +#endif + uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ int vec_len; --=20 2.14.3