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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Wc/CoNMqsyKqJodnheiaplEPKVpkUJ1XJf9Pg7DmoME=; b=byZZq1GB6e/PSPntxyAd9F1SLcfutK8dnlsb4Conzw6Wnu5E9EFAJbpv3HZWdILmd4 JGfLTO/6GtWi7gmRxicnVQGfiFempXrXa6iVtfWY8jGaCL9gAZ9MjonogCqx0uvvdU9c 0EvY7IVgX+SvGXVPuVJfMRKA+1b8EgK20s3Sc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Wc/CoNMqsyKqJodnheiaplEPKVpkUJ1XJf9Pg7DmoME=; b=EDJkub56cMfQ/c7GrZEAg8pbzvecN1iOLSPz3P7TLA+ak++zan6flhLfmDx5vcQcsR pYSpfcfUfs8NUhavu6o9cmPyb2nFXhUIt8vWhVxSOA4GTenD1Ubvg705hmlEwV/PPnuo XZS3uK9yXTvs7bOZlaJ9tc6/gYD1lypvjxa4I82wJ6jRb56vAioSxNMd32GaKejqnuNV iYLf2mQqHMb/9QE+74OzuYICUVKfdz+PuYqlENCjBmUHkpLBSn7CwEVPakogzf0ntSrP MRUvWnoa/LGVWmOZyaTsQUDHfBzrhhMAdxlxSdl09Gq7FhH/LrDLrHbHzOYnXASH1vh8 Mp+w== X-Gm-Message-State: AKwxytccAF9jHmJEIPIhHjErR+PFbWPxbFQNiEnuuWGRUZbYhCI9mrhW RDldhWof+HwRypot5ilNLCakf+e37Eo= X-Google-Smtp-Source: AH8x2246adoWrUpgLQvfVJRKV0Kli82XhiP5B38qUvF0JdPBWe+74nuFeyo/rFGcGf0fl/5xW4skdg== X-Received: by 10.101.66.193 with SMTP id l1mr6017912pgp.17.1516592566388; Sun, 21 Jan 2018 19:42:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:52 -0800 Message-Id: <20180122034217.19593-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 18/43] target/hppa: Implement external interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.h | 2 ++ target/hppa/cpu.c | 6 +++++ target/hppa/int_helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++++= ++++ target/hppa/translate.c | 16 ++++++++++++- 5 files changed, 83 insertions(+), 1 deletion(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c7a2fb5b20..fc3e62c0af 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -340,6 +340,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int rw, int midx); #else int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, MMUAccessType type, hwaddr *pphys, int *ppro= t); +extern const MemoryRegionOps hppa_io_eir_ops; #endif =20 #endif /* HPPA_CPU_H */ diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 79d22ae486..535f086ab4 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -80,5 +80,7 @@ DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env= , i64, i64, i64) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) +DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) +DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 237d2b8ab5..7837d10381 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -57,6 +57,11 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, T= ranslationBlock *tb) cpu->env.psw_n =3D (tb->flags & PSW_N) !=3D 0; } =20 +static bool hppa_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) { info->mach =3D bfd_mach_hppa20; @@ -157,6 +162,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) dc->realize =3D hppa_cpu_realizefn; =20 cc->class_by_name =3D hppa_cpu_class_by_name; + cc->has_work =3D hppa_cpu_has_work; cc->do_interrupt =3D hppa_cpu_do_interrupt; cc->cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index e66ca26941..74ab34f306 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -24,6 +24,65 @@ #include "exec/helper-proto.h" #include "qom/cpu.h" =20 +#ifndef CONFIG_USER_ONLY +static void eval_interrupt(HPPACPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + if (cpu->env.cr[CR_EIRR] & cpu->env.cr[CR_EIEM]) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +/* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus + * can write to this word to raise an external interrupt on the target CPU. + * This includes the system controler (DINO) for regular devices, or + * another CPU for SMP interprocessor interrupts. + */ +static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size) +{ + HPPACPU *cpu =3D opaque; + + /* ??? What does a read of this register over the GSC bus do? */ + return cpu->env.cr[CR_EIRR]; +} + +static void io_eir_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + HPPACPU *cpu =3D opaque; + int le_bit =3D ~data & (TARGET_REGISTER_BITS - 1); + + cpu->env.cr[CR_EIRR] |=3D (target_ureg)1 << le_bit; + eval_interrupt(cpu); +} + +const MemoryRegionOps hppa_io_eir_ops =3D { + .read =3D io_eir_read, + .write =3D io_eir_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, +}; + +void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) +{ + env->cr[CR_EIRR] &=3D ~val; + qemu_mutex_lock_iothread(); + eval_interrupt(hppa_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); +} + +void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val) +{ + env->cr[CR_EIEM] =3D val; + qemu_mutex_lock_iothread(); + eval_interrupt(hppa_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); +} +#endif /* !CONFIG_USER_ONLY */ =20 void hppa_cpu_do_interrupt(CPUState *cs) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f0ee6be052..cac21dbe2f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2113,12 +2113,25 @@ static DisasJumpType trans_mtctl(DisasContext *ctx,= uint32_t insn, /* All other control registers are privileged or read-only. */ CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); =20 +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + DisasJumpType ret =3D DISAS_NEXT; + nullify_over(ctx); switch (ctl) { case CR_IT: /* ??? modify interval timer offset */ break; =20 + case CR_EIRR: + gen_helper_write_eirr(cpu_env, reg); + break; + case CR_EIEM: + gen_helper_write_eiem(cpu_env, reg); + ret =3D DISAS_IAQ_N_STALE_EXIT; + break; + case CR_IIASQ: case CR_IIAOQ: /* FIXME: Respect PSW_Q bit */ @@ -2135,7 +2148,8 @@ static DisasJumpType trans_mtctl(DisasContext *ctx, u= int32_t insn, tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); break; } - return nullify_end(ctx, DISAS_NEXT); + return nullify_end(ctx, ret); +#endif } =20 static DisasJumpType trans_mtsarcm(DisasContext *ctx, uint32_t insn, --=20 2.14.3