From nobody Tue Feb 10 19:49:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526307367663.0225070661677; Sun, 21 Jan 2018 01:18:27 -0800 (PST) Received: from localhost ([::1]:45023 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBli-0001ny-Hy for importer@patchew.org; Sun, 21 Jan 2018 04:18:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34775) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBft-0006Ge-6k for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edBfr-0003DB-MI for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:25 -0500 Received: from chuckie.co.uk ([82.165.15.123]:47998 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1edBfr-0003C0-Cz for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:23 -0500 Received: from host86-133-194-144.range86-133.btcentralplus.com ([86.133.194.144] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1edBg0-0005SV-KH; Sun, 21 Jan 2018 09:12:34 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:52 +0000 Message-Id: <20180121091154.17426-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 08/10] apb: rename apb.c to sabre.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This is the final stage in correcting the naming convention with respect to sabre, APB and PBM. It is effectively a file rename from apb.c to sabre.c along with touching up a few constants to remove the remaining references to APB. Note that as part of the rename process the configuration variable CONFIG_PCI_APB is changed to CONFIG_PCI_SABRE. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko --- default-configs/sparc64-softmmu.mak | 2 +- hw/pci-host/Makefile.objs | 2 +- hw/pci-host/{apb.c =3D> sabre.c} | 57 +++++++++++++++++-----------= ------ hw/sparc64/sun4u.c | 2 +- include/hw/pci-host/{apb.h =3D> sabre.h} | 2 +- 5 files changed, 33 insertions(+), 32 deletions(-) rename hw/pci-host/{apb.c =3D> sabre.c} (91%) rename include/hw/pci-host/{apb.h =3D> sabre.h} (97%) diff --git a/default-configs/sparc64-softmmu.mak b/default-configs/sparc64-= softmmu.mak index 9b742a7b41..52edafe547 100644 --- a/default-configs/sparc64-softmmu.mak +++ b/default-configs/sparc64-softmmu.mak @@ -11,7 +11,7 @@ CONFIG_PCKBD=3Dy CONFIG_FDC=3Dy CONFIG_IDE_ISA=3Dy CONFIG_IDE_CMD646=3Dy -CONFIG_PCI_APB=3Dy +CONFIG_PCI_SABRE=3Dy CONFIG_SIMBA=3Dy CONFIG_SUNHME=3Dy CONFIG_MC146818RTC=3Dy diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs index 9c7909cf44..4b69f737b5 100644 --- a/hw/pci-host/Makefile.objs +++ b/hw/pci-host/Makefile.objs @@ -11,7 +11,7 @@ common-obj-$(CONFIG_PPCE500_PCI) +=3D ppce500.o # ARM devices common-obj-$(CONFIG_VERSATILE_PCI) +=3D versatile.o =20 -common-obj-$(CONFIG_PCI_APB) +=3D apb.o +common-obj-$(CONFIG_PCI_SABRE) +=3D sabre.o common-obj-$(CONFIG_FULONG) +=3D bonito.o common-obj-$(CONFIG_PCI_PIIX) +=3D piix.o common-obj-$(CONFIG_PCI_Q35) +=3D q35.o diff --git a/hw/pci-host/apb.c b/hw/pci-host/sabre.c similarity index 91% rename from hw/pci-host/apb.c rename to hw/pci-host/sabre.c index f6c5dbd469..4054c17598 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/sabre.c @@ -1,8 +1,9 @@ /* - * QEMU Ultrasparc APB PCI host + * QEMU Ultrasparc Sabre PCI host (PBM) * * Copyright (c) 2006 Fabrice Bellard * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2018 Mark Cave-Ayland * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -23,10 +24,6 @@ * THE SOFTWARE. */ =20 -/* XXX This file and most of its contents are somewhat misnamed. The - Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is - the secondary PCI bridge. */ - #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/pci/pci.h" @@ -34,20 +31,20 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "hw/pci-bridge/simba.h" -#include "hw/pci-host/apb.h" +#include "hw/pci-host/sabre.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/log.h" =20 -/* debug APB */ -//#define DEBUG_APB +/* debug sabre */ +//#define DEBUG_SABRE =20 -#ifdef DEBUG_APB -#define APB_DPRINTF(fmt, ...) \ -do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) +#ifdef DEBUG_SABRE +#define SABRE_DPRINTF(fmt, ...) \ +do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0) #else -#define APB_DPRINTF(fmt, ...) +#define SABRE_DPRINTF(fmt, ...) #endif =20 /* @@ -72,7 +69,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) =20 static inline void sabre_set_request(SabreState *s, unsigned int irq_num) { - APB_DPRINTF("%s: request irq %d\n", __func__, irq_num); + SABRE_DPRINTF("%s: request irq %d\n", __func__, irq_num); =20 s->irq_request =3D irq_num; qemu_set_irq(s->ivec_irqs[irq_num], 1); @@ -111,7 +108,7 @@ static inline void sabre_check_irqs(SabreState *s) =20 static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) { - APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); + SABRE_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); qemu_set_irq(s->ivec_irqs[irq_num], 0); s->irq_request =3D NO_IRQ_REQUEST; } @@ -128,7 +125,8 @@ static void sabre_config_write(void *opaque, hwaddr add= r, { SabreState *s =3D opaque; =20 - APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,= addr, val); + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func_= _, + addr, val); =20 switch (addr & 0xffff) { case 0x30 ... 0x4f: /* DMA error registers */ @@ -252,7 +250,7 @@ static uint64_t sabre_config_read(void *opaque, val =3D 0; break; } - APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val= ); + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, v= al); =20 return val; } @@ -269,7 +267,8 @@ static void sabre_pci_config_write(void *opaque, hwaddr= addr, SabreState *s =3D opaque; PCIHostState *phb =3D PCI_HOST_BRIDGE(s); =20 - APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,= addr, val); + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func_= _, + addr, val); pci_data_write(phb->bus, addr, val, size); } =20 @@ -281,7 +280,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwa= ddr addr, PCIHostState *phb =3D PCI_HOST_BRIDGE(s); =20 ret =3D pci_data_read(phb->bus, addr, size); - APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret= ); + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, r= et); return ret; } =20 @@ -319,7 +318,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num= , int level) { SabreState *s =3D opaque; =20 - APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level); + SABRE_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level= ); /* PCI IRQ map onto the first 32 INO. */ if (irq_num < 32) { if (level) { @@ -333,7 +332,8 @@ static void pci_sabre_set_irq(void *opaque, int irq_num= , int level) } else { /* OBIO IRQ map onto the next 32 INO. */ if (level) { - APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, le= vel); + SABRE_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, + level); s->pci_irq_in |=3D 1ULL << irq_num; if ((s->irq_request =3D=3D NO_IRQ_REQUEST) && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { @@ -390,7 +390,7 @@ static void sabre_realize(DeviceState *dev, Error **err= p) SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); PCIDevice *pci_dev; =20 - /* apb_config */ + /* sabre_config */ sysbus_mmio_map(sbd, 0, s->special_base); /* PCI configuration space */ sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); @@ -410,7 +410,7 @@ static void sabre_realize(DeviceState *dev, Error **err= p) pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); =20 /* IOMMU */ - memory_region_add_subregion_overlap(&s->apb_config, 0x200, + memory_region_add_subregion_overlap(&s->sabre_config, 0x200, sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1= ); pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); =20 @@ -454,19 +454,20 @@ static void sabre_init(Object *obj) qdev_prop_allow_set_link_before_realize, 0, NULL); =20 - /* apb_config */ - memory_region_init_io(&s->apb_config, OBJECT(s), &sabre_config_ops, s, - "apb-config", 0x10000); + /* sabre_config */ + memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, = s, + "sabre-config", 0x10000); /* at region 0 */ - sysbus_init_mmio(sbd, &s->apb_config); + sysbus_init_mmio(sbd, &s->sabre_config); =20 memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, - "apb-pci-config", 0x1000000); + "sabre-pci-config", 0x1000000); /* at region 1 */ sysbus_init_mmio(sbd, &s->pci_config); =20 /* pci_ioport */ - memory_region_init(&s->pci_ioport, OBJECT(s), "apb-pci-ioport", 0x1000= 000); + memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport", + 0x1000000); =20 /* at region 2 */ sysbus_init_mmio(sbd, &s->pci_ioport); diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index fb18afaaa6..c4eff6bea2 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -30,7 +30,7 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" -#include "hw/pci-host/apb.h" +#include "hw/pci-host/sabre.h" #include "hw/i386/pc.h" #include "hw/char/serial.h" #include "hw/timer/m48t59.h" diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/sabre.h similarity index 97% rename from include/hw/pci-host/apb.h rename to include/hw/pci-host/sabre.h index 2552f3c984..0f2ccc01c6 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/sabre.h @@ -27,7 +27,7 @@ typedef struct SabreState { =20 hwaddr special_base; hwaddr mem_base; - MemoryRegion apb_config; + MemoryRegion sabre_config; MemoryRegion pci_config; MemoryRegion pci_mmio; MemoryRegion pci_ioport; --=20 2.11.0