From nobody Tue Feb 10 21:59:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516526600277794.7773987765897; Sun, 21 Jan 2018 01:23:20 -0800 (PST) Received: from localhost ([::1]:45286 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBqR-0005Rh-IS for importer@patchew.org; Sun, 21 Jan 2018 04:23:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34783) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edBfw-0006HP-8X for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edBft-0003Dw-CW for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:26 -0500 Received: from chuckie.co.uk ([82.165.15.123]:48000 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1edBft-0003De-5V for qemu-devel@nongnu.org; Sun, 21 Jan 2018 04:12:25 -0500 Received: from host86-133-194-144.range86-133.btcentralplus.com ([86.133.194.144] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1edBg2-0005SV-Ue; Sun, 21 Jan 2018 09:12:36 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 21 Jan 2018 09:11:53 +0000 Message-Id: <20180121091154.17426-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> References: <20180121091154.17426-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.194.144 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 09/10] sabre: convert from SABRE_DPRINTF macro to trace-events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcel Apfelbaum , Mark Cave-Ayland , "Michael S . Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Signed-off-by: Mark Cave-Ayland CC: Michael S. Tsirkin CC: Marcel Apfelbaum Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Artyom Tarasenko [for addition of trace-events to hw/pci-host] Acked-by: Michael S. Tsirkin --- Makefile.objs | 1 + hw/pci-host/sabre.c | 32 ++++++++++---------------------- hw/pci-host/trace-events | 11 +++++++++++ 3 files changed, 22 insertions(+), 22 deletions(-) create mode 100644 hw/pci-host/trace-events diff --git a/Makefile.objs b/Makefile.objs index 669d8d684d..323ef12384 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -150,6 +150,7 @@ trace-events-subdirs +=3D hw/i386/xen trace-events-subdirs +=3D hw/9pfs trace-events-subdirs +=3D hw/ppc trace-events-subdirs +=3D hw/pci +trace-events-subdirs +=3D hw/pci-host trace-events-subdirs +=3D hw/s390x trace-events-subdirs +=3D hw/vfio trace-events-subdirs +=3D hw/acpi diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index 4054c17598..2268a41dd9 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -36,16 +36,7 @@ #include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/log.h" - -/* debug sabre */ -//#define DEBUG_SABRE - -#ifdef DEBUG_SABRE -#define SABRE_DPRINTF(fmt, ...) \ -do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0) -#else -#define SABRE_DPRINTF(fmt, ...) -#endif +#include "trace.h" =20 /* * Chipset docs: @@ -69,8 +60,7 @@ do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0) =20 static inline void sabre_set_request(SabreState *s, unsigned int irq_num) { - SABRE_DPRINTF("%s: request irq %d\n", __func__, irq_num); - + trace_sabre_set_request(irq_num); s->irq_request =3D irq_num; qemu_set_irq(s->ivec_irqs[irq_num], 1); } @@ -108,7 +98,7 @@ static inline void sabre_check_irqs(SabreState *s) =20 static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) { - SABRE_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); + trace_sabre_clear_request(irq_num); qemu_set_irq(s->ivec_irqs[irq_num], 0); s->irq_request =3D NO_IRQ_REQUEST; } @@ -125,8 +115,7 @@ static void sabre_config_write(void *opaque, hwaddr add= r, { SabreState *s =3D opaque; =20 - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func_= _, - addr, val); + trace_sabre_config_write(addr, val); =20 switch (addr & 0xffff) { case 0x30 ... 0x4f: /* DMA error registers */ @@ -250,7 +239,7 @@ static uint64_t sabre_config_read(void *opaque, val =3D 0; break; } - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, v= al); + trace_sabre_config_read(addr, val); =20 return val; } @@ -267,8 +256,7 @@ static void sabre_pci_config_write(void *opaque, hwaddr= addr, SabreState *s =3D opaque; PCIHostState *phb =3D PCI_HOST_BRIDGE(s); =20 - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func_= _, - addr, val); + trace_sabre_pci_config_write(addr, val); pci_data_write(phb->bus, addr, val, size); } =20 @@ -280,7 +268,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwa= ddr addr, PCIHostState *phb =3D PCI_HOST_BRIDGE(s); =20 ret =3D pci_data_read(phb->bus, addr, size); - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, r= et); + trace_sabre_pci_config_read(addr, ret); return ret; } =20 @@ -318,7 +306,8 @@ static void pci_sabre_set_irq(void *opaque, int irq_num= , int level) { SabreState *s =3D opaque; =20 - SABRE_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level= ); + trace_sabre_pci_set_irq(irq_num, level); + /* PCI IRQ map onto the first 32 INO. */ if (irq_num < 32) { if (level) { @@ -332,8 +321,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num= , int level) } else { /* OBIO IRQ map onto the next 32 INO. */ if (level) { - SABRE_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, - level); + trace_sabre_pci_set_obio_irq(irq_num, level); s->pci_irq_in |=3D 1ULL << irq_num; if ((s->irq_request =3D=3D NO_IRQ_REQUEST) && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events new file mode 100644 index 0000000000..32dfc84692 --- /dev/null +++ b/hw/pci-host/trace-events @@ -0,0 +1,11 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/pci-host/sabre.c +sabre_set_request(int irq_num) "request irq %d" +sabre_clear_request(int irq_num) "clear request irq %d" +sabre_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"= PRIx64 +sabre_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"P= RIx64 +sabre_pci_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val = 0x%"PRIx64 +sabre_pci_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0= x%"PRIx64 +sabre_pci_set_irq(int irq_num, int level) "set irq_in %d level %d" +sabre_pci_set_obio_irq(int irq_num, int level) "set irq %d level %d" --=20 2.11.0