From nobody Sun Apr 28 17:28:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516386335485761.6250800532796; Fri, 19 Jan 2018 10:25:35 -0800 (PST) Received: from localhost ([::1]:36502 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecbM3-0000xH-8a for importer@patchew.org; Fri, 19 Jan 2018 13:25:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35404) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecbJj-0007bh-2C for qemu-devel@nongnu.org; Fri, 19 Jan 2018 13:23:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecbJh-0008EB-0M for qemu-devel@nongnu.org; Fri, 19 Jan 2018 13:23:07 -0500 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:44847) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecbJg-0008Ds-Nv for qemu-devel@nongnu.org; Fri, 19 Jan 2018 13:23:04 -0500 Received: by mail-wm0-x244.google.com with SMTP id t74so5159170wme.3 for ; Fri, 19 Jan 2018 10:23:04 -0800 (PST) Received: from localhost.localdomain ([160.170.62.40]) by smtp.gmail.com with ESMTPSA id f48sm6263629wra.72.2018.01.19.10.23.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 10:23:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gnEjMy7hxIp5V2FTQJWtq2MOvx9sVxQfdppBY0G5cdU=; b=jdCGyY6wkhyA4dO8j4tbnPfSAZDC/hAasXptMbfX7oOlRHGfa14Cmi9yzFjdxE1smy FLXi+d28uYoDNoDuxZgbIcZGiynWWIsO9dg7t4JTrnZUk8zDHDeKH34s2mckEGAh+xCF 2ZLTkbqss83RYnzbhb15/tfkB9XOqu0ShtMJE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gnEjMy7hxIp5V2FTQJWtq2MOvx9sVxQfdppBY0G5cdU=; b=IYAFojhUGb0/BGP2Fft66bNQ/Z7Qt2zT/orgUlLqdRjkCQTir5OuUxknbGOcnp+W8k AKNgh5LSYjs69/8lWwnm4HacosntCbN0lsCoD+TSZcVWDPy+b90rS8JoQ46CWb6UG3xf itELBS+N+olOBtY31BT07eAndFTMC6ULcj0IACKaK1mC/VIA94t3/3/jDOV2CcaWS2qt naywD451xg9klfF5uLus8nBDWKff1cQ9R1W+pUU9hWKNbXEw78Hk72/DI2yGM6Lck+j5 cCdm3yu6tu5Ar+T3x+lTHgU7UdqlYQVCFk4NBxJ/xe5tKxZYRA025B2DZ+Y7wyDSWqqj LAaQ== X-Gm-Message-State: AKwxytcTkTnVHkEvktTeNigMMiD8yOeKAzMp32uJgjDi62GoIi/EFOWi KilJ3njNRUIK9cMZq++6qcF8c9StphA= X-Google-Smtp-Source: ACJfBosv2lTYNJIyvxoTBrt6LhzbyEc7/fNNCkDTB1orRuldtfSor5b+jmFFRWK0HOUqEQh5YGphCg== X-Received: by 10.28.40.195 with SMTP id o186mr9818957wmo.136.1516386183374; Fri, 19 Jan 2018 10:23:03 -0800 (PST) From: Ard Biesheuvel To: qemu-devel@nongnu.org Date: Fri, 19 Jan 2018 18:22:45 +0000 Message-Id: <20180119182248.10821-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119182248.10821-1-ard.biesheuvel@linaro.org> References: <20180119182248.10821-1-ard.biesheuvel@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v4 1/4] target/arm: implement SHA-512 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel , rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This implements emulation of the new SHA-512 instructions that have been added as an optional extension to the ARMv8 Crypto Extensions in ARM v8.2. Signed-off-by: Ard Biesheuvel --- target/arm/cpu.h | 1 + target/arm/crypto_helper.c | 75 ++++++++++++++- target/arm/helper.h | 5 + target/arm/translate-a64.c | 99 ++++++++++++++++++++ 4 files changed, 179 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0a923e42d8bf..32a18510e70b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1372,6 +1372,7 @@ enum arm_features { ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_SVE, /* has Scalable Vector Extension */ + ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensio= ns */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index 9ca0bdead7bb..fb45948e9f13 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -1,7 +1,7 @@ /* * crypto_helper.c - emulate v8 Crypto Extensions instructions * - * Copyright (C) 2013 - 2014 Linaro Ltd + * Copyright (C) 2013 - 2018 Linaro Ltd * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -419,3 +419,76 @@ void HELPER(crypto_sha256su1)(void *vd, void *vn, void= *vm) rd[0] =3D d.l[0]; rd[1] =3D d.l[1]; } + +/* + * The SHA-512 logical functions (same as above but using 64-bit operands) + */ + +static uint64_t cho512(uint64_t x, uint64_t y, uint64_t z) +{ + return (x & (y ^ z)) ^ z; +} + +static uint64_t maj512(uint64_t x, uint64_t y, uint64_t z) +{ + return (x & y) | ((x | y) & z); +} + +static uint64_t S0_512(uint64_t x) +{ + return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39); +} + +static uint64_t S1_512(uint64_t x) +{ + return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41); +} + +static uint64_t s0_512(uint64_t x) +{ + return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7); +} + +static uint64_t s1_512(uint64_t x) +{ + return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6); +} + +void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + + rd[1] +=3D S1_512(rm[1]) + cho512(rm[1], rn[0], rn[1]); + rd[0] +=3D S1_512(rd[1] + rm[0]) + cho512(rd[1] + rm[0], rm[1], rn[0]); +} + +void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + + rd[1] +=3D S0_512(rm[0]) + maj512(rn[0], rm[1], rm[0]); + rd[0] +=3D S0_512(rd[1]) + maj512(rd[1], rm[0], rm[1]); +} + +void HELPER(crypto_sha512su0)(void *vd, void *vn) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + + rd[0] +=3D s0_512(rd[1]); + rd[1] +=3D s0_512(rn[0]); +} + +void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + + rd[0] +=3D s1_512(rn[0]) + rm[0]; + rd[1] +=3D s1_512(rn[1]) + rm[1]; +} diff --git a/target/arm/helper.h b/target/arm/helper.h index 5dec2e62626b..81d460702867 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -534,6 +534,11 @@ DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, v= oid, ptr, ptr, ptr) DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr) DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_3(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) +DEF_HELPER_FLAGS_2(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sha512su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) + DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(dc_zva, void, env, i64) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 10eef870fee2..fe08f3198dac 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11132,6 +11132,103 @@ static void disas_crypto_two_reg_sha(DisasContext= *s, uint32_t insn) tcg_temp_free_ptr(tcg_rn_ptr); } =20 +/* Crypto three-reg SHA512 + * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 + * +-----------------------+------+---+---+-----+--------+------+------+ + * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd | + * +-----------------------+------+---+---+-----+--------+------+------+ + */ +static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) +{ + int opcode =3D extract32(insn, 10, 2); + int o =3D extract32(insn, 14, 1); + int rm =3D extract32(insn, 16, 5); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; + CryptoThreeOpFn *genfn; + + if (o !=3D 0) { + unallocated_encoding(s); + return; + } + + switch (opcode) { + case 0: /* SHA512H */ + genfn =3D gen_helper_crypto_sha512h; + break; + case 1: /* SHA512H2 */ + genfn =3D gen_helper_crypto_sha512h2; + break; + case 2: /* SHA512SU1 */ + genfn =3D gen_helper_crypto_sha512su1; + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA512)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); + tcg_rm_ptr =3D vec_full_reg_ptr(s, rm); + + genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr); + + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); + tcg_temp_free_ptr(tcg_rm_ptr); +} + +/* Crypto two-reg SHA512 + * 31 12 11 10 9 5 4 0 + * +-----------------------------------------+--------+------+------+ + * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd | + * +-----------------------------------------+--------+------+------+ + */ +static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) +{ + int opcode =3D extract32(insn, 10, 2); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; + CryptoTwoOpFn *genfn; + + switch (opcode) { + case 0: /* SHA512SU0 */ + genfn =3D gen_helper_crypto_sha512su0; + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA512)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); + + genfn(tcg_rd_ptr, tcg_rn_ptr); + + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); +} + /* C3.6 Data processing - SIMD, inc Crypto * * As the decode gets a little complex we are using a table based @@ -11161,6 +11258,8 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, + { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 }, + { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.11.0 From nobody Sun Apr 28 17:28:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 19 Jan 2018 10:23:05 -0800 (PST) From: Ard Biesheuvel To: qemu-devel@nongnu.org Date: Fri, 19 Jan 2018 18:22:46 +0000 Message-Id: <20180119182248.10821-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119182248.10821-1-ard.biesheuvel@linaro.org> References: <20180119182248.10821-1-ard.biesheuvel@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v4 2/4] target/arm: implement SHA-3 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel , rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This implements emulation of the new SHA-3 instructions that have been added as an optional extensions to the ARMv8 Crypto Extensions in ARM v8.2. Signed-off-by: Ard Biesheuvel --- target/arm/cpu.h | 1 + target/arm/translate-a64.c | 157 ++++++++++++++++++-- 2 files changed, 146 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 32a18510e70b..d0b19e0cbc88 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1373,6 +1373,7 @@ enum arm_features { ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensio= ns */ + ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fe08f3198dac..787b94047286 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11145,8 +11145,8 @@ static void disas_crypto_three_reg_sha512(DisasCont= ext *s, uint32_t insn) int rm =3D extract32(insn, 16, 5); int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); - TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; CryptoThreeOpFn *genfn; + int feature; =20 if (o !=3D 0) { unallocated_encoding(s); @@ -11155,20 +11155,24 @@ static void disas_crypto_three_reg_sha512(DisasCo= ntext *s, uint32_t insn) =20 switch (opcode) { case 0: /* SHA512H */ + feature =3D ARM_FEATURE_V8_SHA512; genfn =3D gen_helper_crypto_sha512h; break; case 1: /* SHA512H2 */ + feature =3D ARM_FEATURE_V8_SHA512; genfn =3D gen_helper_crypto_sha512h2; break; case 2: /* SHA512SU1 */ + feature =3D ARM_FEATURE_V8_SHA512; genfn =3D gen_helper_crypto_sha512su1; break; - default: - unallocated_encoding(s); - return; + case 3: /* RAX1 */ + feature =3D ARM_FEATURE_V8_SHA3; + genfn =3D NULL; + break; } =20 - if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA512)) { + if (!arm_dc_feature(s, feature)) { unallocated_encoding(s); return; } @@ -11177,15 +11181,42 @@ static void disas_crypto_three_reg_sha512(DisasCo= ntext *s, uint32_t insn) return; } =20 - tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); - tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); - tcg_rm_ptr =3D vec_full_reg_ptr(s, rm); + if (genfn) { + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; =20 - genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr); + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); + tcg_rm_ptr =3D vec_full_reg_ptr(s, rm); =20 - tcg_temp_free_ptr(tcg_rd_ptr); - tcg_temp_free_ptr(tcg_rn_ptr); - tcg_temp_free_ptr(tcg_rm_ptr); + genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr); + + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); + tcg_temp_free_ptr(tcg_rm_ptr); + } else { + TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; + int pass; + + tcg_op1 =3D tcg_temp_new_i64(); + tcg_op2 =3D tcg_temp_new_i64(); + tcg_res[0] =3D tcg_temp_new_i64(); + tcg_res[1] =3D tcg_temp_new_i64(); + + for (pass =3D 0; pass < 2; pass++) { + read_vec_element(s, tcg_op1, rn, pass, MO_64); + read_vec_element(s, tcg_op2, rm, pass, MO_64); + + tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1); + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); + } + write_vec_element(s, tcg_res[0], rd, 0, MO_64); + write_vec_element(s, tcg_res[1], rd, 1, MO_64); + + tcg_temp_free(tcg_op1); + tcg_temp_free(tcg_op2); + tcg_temp_free(tcg_res[0]); + tcg_temp_free(tcg_res[1]); + } } =20 /* Crypto two-reg SHA512 @@ -11229,6 +11260,106 @@ static void disas_crypto_two_reg_sha512(DisasCont= ext *s, uint32_t insn) tcg_temp_free_ptr(tcg_rn_ptr); } =20 +/* Crypto four-register + * 31 23 22 21 20 16 15 14 10 9 5 4 0 + * +-------------------+-----+------+---+------+------+------+ + * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd | + * +-------------------+-----+------+---+------+------+------+ + */ +static void disas_crypto_four_reg(DisasContext *s, uint32_t insn) +{ + int op0 =3D extract32(insn, 21, 2); + int rm =3D extract32(insn, 16, 5); + int ra =3D extract32(insn, 10, 5); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2]; + int pass; + + if (op0 > 1 || !arm_dc_feature(s, ARM_FEATURE_V8_SHA3)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + tcg_op1 =3D tcg_temp_new_i64(); + tcg_op2 =3D tcg_temp_new_i64(); + tcg_op3 =3D tcg_temp_new_i64(); + tcg_res[0] =3D tcg_temp_new_i64(); + tcg_res[1] =3D tcg_temp_new_i64(); + + for (pass =3D 0; pass < 2; pass++) { + read_vec_element(s, tcg_op1, rn, pass, MO_64); + read_vec_element(s, tcg_op2, rm, pass, MO_64); + read_vec_element(s, tcg_op3, ra, pass, MO_64); + + if (op0 =3D=3D 0) { + /* EOR3 */ + tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op3); + } else { + /* BCAX */ + tcg_gen_andc_i64(tcg_res[pass], tcg_op2, tcg_op3); + } + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); + } + write_vec_element(s, tcg_res[0], rd, 0, MO_64); + write_vec_element(s, tcg_res[1], rd, 1, MO_64); + + tcg_temp_free(tcg_op1); + tcg_temp_free(tcg_op2); + tcg_temp_free(tcg_op3); + tcg_temp_free(tcg_res[0]); + tcg_temp_free(tcg_res[1]); +} + +/* Crypto XAR + * 31 21 20 16 15 10 9 5 4 0 + * +-----------------------+------+--------+------+------+ + * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd | + * +-----------------------+------+--------+------+------+ + */ +static void disas_crypto_xar(DisasContext *s, uint32_t insn) +{ + int rm =3D extract32(insn, 16, 5); + int imm6 =3D extract32(insn, 10, 6); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA3)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + tcg_op1 =3D tcg_temp_new_i64(); + tcg_op2 =3D tcg_temp_new_i64(); + tcg_res[0] =3D tcg_temp_new_i64(); + tcg_res[1] =3D tcg_temp_new_i64(); + + for (pass =3D 0; pass < 2; pass++) { + read_vec_element(s, tcg_op1, rn, pass, MO_64); + read_vec_element(s, tcg_op2, rm, pass, MO_64); + + tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); + tcg_gen_rotri_i64(tcg_res[pass], tcg_res[pass], imm6); + } + write_vec_element(s, tcg_res[0], rd, 0, MO_64); + write_vec_element(s, tcg_res[1], rd, 1, MO_64); + + tcg_temp_free(tcg_op1); + tcg_temp_free(tcg_op2); + tcg_temp_free(tcg_res[0]); + tcg_temp_free(tcg_res[1]); +} + /* C3.6 Data processing - SIMD, inc Crypto * * As the decode gets a little complex we are using a table based @@ -11260,6 +11391,8 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 }, { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, + { 0xce000000, 0xff808000, disas_crypto_four_reg }, + { 0xce800000, 0xffe00000, disas_crypto_xar }, { 0x00000000, 0x00000000, NULL } }; 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v4 3/4] target/arm: implement SM3 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel , rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This implements emulation of the new SM3 instructions that have been added as an optional extension to the ARMv8 Crypto Extensions in ARM v8.2. Signed-off-by: Ard Biesheuvel --- target/arm/cpu.h | 1 + target/arm/crypto_helper.c | 117 +++++++++++++ target/arm/helper.h | 5 + target/arm/translate-a64.c | 183 ++++++++++++++------ 4 files changed, 257 insertions(+), 49 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d0b19e0cbc88..18383666e02d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1374,6 +1374,7 @@ enum arm_features { ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensio= ns */ ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ + ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index fb45948e9f13..c1d9f765cd40 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -492,3 +492,120 @@ void HELPER(crypto_sha512su1)(void *vd, void *vn, voi= d *vm) rd[0] +=3D s1_512(rn[0]) + rm[0]; rd[1] +=3D s1_512(rn[1]) + rm[1]; } + +void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; + uint32_t t; + + t =3D CR_ST_WORD(d, 0) ^ CR_ST_WORD(n, 0) ^ ror32(CR_ST_WORD(m, 1), 17= ); + CR_ST_WORD(d, 0) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + t =3D CR_ST_WORD(d, 1) ^ CR_ST_WORD(n, 1) ^ ror32(CR_ST_WORD(m, 2), 17= ); + CR_ST_WORD(d, 1) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + t =3D CR_ST_WORD(d, 2) ^ CR_ST_WORD(n, 2) ^ ror32(CR_ST_WORD(m, 3), 17= ); + CR_ST_WORD(d, 2) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + t =3D CR_ST_WORD(d, 3) ^ CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(d, 0), 17= ); + CR_ST_WORD(d, 3) =3D t ^ ror32(t, 17) ^ ror32(t, 9); + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} + +void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; + uint32_t t =3D CR_ST_WORD(n, 0) ^ ror32(CR_ST_WORD(m, 0), 25); + + CR_ST_WORD(d, 0) ^=3D t; + CR_ST_WORD(d, 1) ^=3D CR_ST_WORD(n, 1) ^ ror32(CR_ST_WORD(m, 1), 25); + CR_ST_WORD(d, 2) ^=3D CR_ST_WORD(n, 2) ^ ror32(CR_ST_WORD(m, 2), 25); + CR_ST_WORD(d, 3) ^=3D CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(m, 3), 25) ^ + ror32(t, 17) ^ ror32(t, 2) ^ ror32(t, 26); + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} + +void HELPER(crypto_sm3ss1)(void *vd, void *vn, void *va, void *vm) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *ra =3D va; + uint64_t *rm =3D vm; + union CRYPTO_STATE d; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE a =3D { .l =3D { ra[0], ra[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; + + CR_ST_WORD(d, 0) =3D 0; + CR_ST_WORD(d, 1) =3D 0; + CR_ST_WORD(d, 2) =3D 0; + CR_ST_WORD(d, 3) =3D ror32(ror32(CR_ST_WORD(n, 3), 20) + CR_ST_WORD(m,= 3) + + CR_ST_WORD(a, 3), 25); + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} + +void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2, + uint32_t opcode) +{ + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; + uint32_t t; + + assert(imm2 < 4); + + if (opcode =3D=3D 0 || opcode =3D=3D 2) { + /* SM3TT1A, SM3TT2A */ + t =3D par(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1)); + } else if (opcode =3D=3D 1) { + /* SM3TT1B */ + t =3D maj(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1)); + } else if (opcode =3D=3D 3) { + /* SM3TT2B */ + t =3D cho(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1)); + } else { + g_assert_not_reached(); + } + + t +=3D CR_ST_WORD(d, 0) + CR_ST_WORD(m, imm2); + + CR_ST_WORD(d, 0) =3D CR_ST_WORD(d, 1); + + if (opcode < 2) { + /* SM3TT1A, SM3TT1B */ + t +=3D CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(d, 3), 20); + + CR_ST_WORD(d, 1) =3D ror32(CR_ST_WORD(d, 2), 23); + } else { + /* SM3TT2A, SM3TT2B */ + t +=3D CR_ST_WORD(n, 3); + t ^=3D rol32(t, 9) ^ rol32(t, 17); + + CR_ST_WORD(d, 1) =3D ror32(CR_ST_WORD(d, 2), 13); + } + + CR_ST_WORD(d, 2) =3D CR_ST_WORD(d, 3); + CR_ST_WORD(d, 3) =3D t; + + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; +} diff --git a/target/arm/helper.h b/target/arm/helper.h index 81d460702867..2d0bba10c006 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -539,6 +539,11 @@ DEF_HELPER_FLAGS_3(crypto_sha512h2, TCG_CALL_NO_RWG, v= oid, ptr, ptr, ptr) DEF_HELPER_FLAGS_2(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr) DEF_HELPER_FLAGS_3(crypto_sha512su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(crypto_sm3ss1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32= , i32) +DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) + DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(dc_zva, void, env, i64) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 787b94047286..1e3ff9a6152f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11148,28 +11148,39 @@ static void disas_crypto_three_reg_sha512(DisasCo= ntext *s, uint32_t insn) CryptoThreeOpFn *genfn; int feature; =20 - if (o !=3D 0) { - unallocated_encoding(s); - return; - } - - switch (opcode) { - case 0: /* SHA512H */ - feature =3D ARM_FEATURE_V8_SHA512; - genfn =3D gen_helper_crypto_sha512h; - break; - case 1: /* SHA512H2 */ - feature =3D ARM_FEATURE_V8_SHA512; - genfn =3D gen_helper_crypto_sha512h2; - break; - case 2: /* SHA512SU1 */ - feature =3D ARM_FEATURE_V8_SHA512; - genfn =3D gen_helper_crypto_sha512su1; - break; - case 3: /* RAX1 */ - feature =3D ARM_FEATURE_V8_SHA3; - genfn =3D NULL; - break; + if (o =3D=3D 0) { + switch (opcode) { + case 0: /* SHA512H */ + feature =3D ARM_FEATURE_V8_SHA512; + genfn =3D gen_helper_crypto_sha512h; + break; + case 1: /* SHA512H2 */ + feature =3D ARM_FEATURE_V8_SHA512; + genfn =3D gen_helper_crypto_sha512h2; + break; + case 2: /* SHA512SU1 */ + feature =3D ARM_FEATURE_V8_SHA512; + genfn =3D gen_helper_crypto_sha512su1; + break; + case 3: /* RAX1 */ + feature =3D ARM_FEATURE_V8_SHA3; + genfn =3D NULL; + break; + } + } else { + switch (opcode) { + case 0: /* SM3PARTW1 */ + feature =3D ARM_FEATURE_V8_SM3; + genfn =3D gen_helper_crypto_sm3partw1; + break; + case 1: /* SM3PARTW2 */ + feature =3D ARM_FEATURE_V8_SM3; + genfn =3D gen_helper_crypto_sm3partw2; + break; + default: + unallocated_encoding(s); + return; + } } =20 if (!arm_dc_feature(s, feature)) { @@ -11273,10 +11284,22 @@ static void disas_crypto_four_reg(DisasContext *s= , uint32_t insn) int ra =3D extract32(insn, 10, 5); int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); - TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2]; - int pass; + int feature; =20 - if (op0 > 1 || !arm_dc_feature(s, ARM_FEATURE_V8_SHA3)) { + switch (op0) { + case 0: /* EOR3 */ + case 1: /* BCAX */ + feature =3D ARM_FEATURE_V8_SHA3; + break; + case 2: /* SM3SS1 */ + feature =3D ARM_FEATURE_V8_SM3; + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, feature)) { unallocated_encoding(s); return; } @@ -11285,34 +11308,54 @@ static void disas_crypto_four_reg(DisasContext *s= , uint32_t insn) return; } =20 - tcg_op1 =3D tcg_temp_new_i64(); - tcg_op2 =3D tcg_temp_new_i64(); - tcg_op3 =3D tcg_temp_new_i64(); - tcg_res[0] =3D tcg_temp_new_i64(); - tcg_res[1] =3D tcg_temp_new_i64(); + if (op0 =3D=3D 2) { + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_ra_ptr, tcg_rm_ptr; =20 - for (pass =3D 0; pass < 2; pass++) { - read_vec_element(s, tcg_op1, rn, pass, MO_64); - read_vec_element(s, tcg_op2, rm, pass, MO_64); - read_vec_element(s, tcg_op3, ra, pass, MO_64); + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); + tcg_ra_ptr =3D vec_full_reg_ptr(s, ra); + tcg_rm_ptr =3D vec_full_reg_ptr(s, rm); =20 - if (op0 =3D=3D 0) { - /* EOR3 */ - tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op3); - } else { - /* BCAX */ - tcg_gen_andc_i64(tcg_res[pass], tcg_op2, tcg_op3); + gen_helper_crypto_sm3ss1(tcg_rd_ptr, tcg_rn_ptr, tcg_ra_ptr, + tcg_rm_ptr); + + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); + tcg_temp_free_ptr(tcg_ra_ptr); + tcg_temp_free_ptr(tcg_rm_ptr); + } else { + TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2]; + int pass; + + tcg_op1 =3D tcg_temp_new_i64(); + tcg_op2 =3D tcg_temp_new_i64(); + tcg_op3 =3D tcg_temp_new_i64(); + tcg_res[0] =3D tcg_temp_new_i64(); + tcg_res[1] =3D tcg_temp_new_i64(); + + for (pass =3D 0; pass < 2; pass++) { + read_vec_element(s, tcg_op1, rn, pass, MO_64); + read_vec_element(s, tcg_op2, rm, pass, MO_64); + read_vec_element(s, tcg_op3, ra, pass, MO_64); + + if (op0 =3D=3D 0) { + /* EOR3 */ + tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op3); + } else { + /* BCAX */ + tcg_gen_andc_i64(tcg_res[pass], tcg_op2, tcg_op3); + } + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); } - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); - } - write_vec_element(s, tcg_res[0], rd, 0, MO_64); - write_vec_element(s, tcg_res[1], rd, 1, MO_64); + write_vec_element(s, tcg_res[0], rd, 0, MO_64); + write_vec_element(s, tcg_res[1], rd, 1, MO_64); =20 - tcg_temp_free(tcg_op1); - tcg_temp_free(tcg_op2); - tcg_temp_free(tcg_op3); - tcg_temp_free(tcg_res[0]); - tcg_temp_free(tcg_res[1]); + tcg_temp_free(tcg_op1); + tcg_temp_free(tcg_op2); + tcg_temp_free(tcg_op3); + tcg_temp_free(tcg_res[0]); + tcg_temp_free(tcg_res[1]); + } } =20 /* Crypto XAR @@ -11360,6 +11403,47 @@ static void disas_crypto_xar(DisasContext *s, uint= 32_t insn) tcg_temp_free(tcg_res[1]); } =20 +/* Crypto three-reg imm2 + * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 + * +-----------------------+------+-----+------+--------+------+------+ + * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd | + * +-----------------------+------+-----+------+--------+------+------+ + */ +static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) +{ + int opcode =3D extract32(insn, 10, 2); + int imm2 =3D extract32(insn, 12, 2); + int rm =3D extract32(insn, 16, 5); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; + TCGv_i32 tcg_imm2, tcg_opcode; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_SM3)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); + tcg_rm_ptr =3D vec_full_reg_ptr(s, rm); + tcg_imm2 =3D tcg_const_i32(imm2); + tcg_opcode =3D tcg_const_i32(opcode); + + gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2, + tcg_opcode); + + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); + tcg_temp_free_ptr(tcg_rm_ptr); + tcg_temp_free_i32(tcg_imm2); + tcg_temp_free_i32(tcg_opcode); +} + /* C3.6 Data processing - SIMD, inc Crypto * * As the decode gets a little complex we are using a table based @@ -11393,6 +11477,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, { 0xce000000, 0xff808000, disas_crypto_four_reg }, { 0xce800000, 0xffe00000, disas_crypto_xar }, + { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.11.0 From nobody Sun Apr 28 17:28:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Fri, 19 Jan 2018 10:23:10 -0800 (PST) From: Ard Biesheuvel To: qemu-devel@nongnu.org Date: Fri, 19 Jan 2018 18:22:48 +0000 Message-Id: <20180119182248.10821-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119182248.10821-1-ard.biesheuvel@linaro.org> References: <20180119182248.10821-1-ard.biesheuvel@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v4 4/4] target/arm: enable user-mode SHA-3, SM3 and SHA-512 instruction support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel , rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the new ARMv8.2 SHA-3, SM3 and SHA-512 instructions to AArch64 user mode emulation. Signed-off-by: Ard Biesheuvel Reviewed-by: Peter Maydell --- linux-user/elfload.c | 18 ++++++++++++++++++ target/arm/cpu64.c | 3 +++ 2 files changed, 21 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 20f3d8c2c373..5d5aa26d2710 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -512,6 +512,21 @@ enum { ARM_HWCAP_A64_SHA1 =3D 1 << 5, ARM_HWCAP_A64_SHA2 =3D 1 << 6, ARM_HWCAP_A64_CRC32 =3D 1 << 7, + ARM_HWCAP_A64_ATOMICS =3D 1 << 8, + ARM_HWCAP_A64_FPHP =3D 1 << 9, + ARM_HWCAP_A64_ASIMDHP =3D 1 << 10, + ARM_HWCAP_A64_CPUID =3D 1 << 11, + ARM_HWCAP_A64_ASIMDRDM =3D 1 << 12, + ARM_HWCAP_A64_JSCVT =3D 1 << 13, + ARM_HWCAP_A64_FCMA =3D 1 << 14, + ARM_HWCAP_A64_LRCPC =3D 1 << 15, + ARM_HWCAP_A64_DCPOP =3D 1 << 16, + ARM_HWCAP_A64_SHA3 =3D 1 << 17, + ARM_HWCAP_A64_SM3 =3D 1 << 18, + ARM_HWCAP_A64_SM4 =3D 1 << 19, + ARM_HWCAP_A64_ASIMDDP =3D 1 << 20, + ARM_HWCAP_A64_SHA512 =3D 1 << 21, + ARM_HWCAP_A64_SVE =3D 1 << 22, }; =20 #define ELF_HWCAP get_elf_hwcap() @@ -532,6 +547,9 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); + GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3); + GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); + GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); #undef GET_FEATURE =20 return hwcaps; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6ed4..56d50ba57194 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -224,6 +224,9 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_AES); set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ --=20 2.11.0