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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.54.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:54:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5WNzWOnHIPiHy0Szq3f4k4lBfnWBOrorMzjkzO2oPgc=; b=iNYCzjSgBnHehBFmyEw16BjWWjHVkp/ph+wiPXGSLKIpnTG07uh9tArpMPVuzV2mQc a8Qnf8EQWS8DmmIsbuEV8AqCCsChx5sxQW49dgna0r5zv4EPauudIkG+1+69/ENBgJoI Zyp2GX8V7lqvS/be3aVBTpA1MiAw9QUWMY2WQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5WNzWOnHIPiHy0Szq3f4k4lBfnWBOrorMzjkzO2oPgc=; b=NrJ/e1bu64++5AgkAcNJQIv/rZu7GyQEQoUv5BxSdazMY7/x06ErNk7cbeAL+2nePR IAhNO5K34ZlvEFz1gCpxonN0+JZiWpIw8F2MNwxHlLf2ECKyyslEawq0TzV5jrL9NpKS UO6aWxQmMpp4OQ4cRwbCHz3YltMLav3sA1Iga0AgmQrwija5tp/osxiyUUQOdIqqpHkX cKsK0pO34l8oQZa1bMINWfZK+skPgkOUGT22enFtm3DVh113H84qmEOfMDy0b1xORvRT yH4LKY2IfeUbNTxMgk6b9DfLzGttfrtzIwdozIjB5LKbkoLKbUOWhvNeGE2hNwsyb0g2 wV0A== X-Gm-Message-State: AKwxytfGzEfAk9aLvM7mR8ZM6cy//TGxwZoWC0bWEiN7TE+k/fcCsule SCxgZ5TgSxkkdXhn2WyMnXyd4CITOtY= X-Google-Smtp-Source: ACJfBouqL6pIXqMSxCCxks99lmcWLnZC5Ww9iwm2EzXuMTITz/7nFNSrhtGfA33i5aDOmHfAxRrI+A== X-Received: by 2002:a17:902:658f:: with SMTP id c15-v6mr946368plk.412.1516337682375; Thu, 18 Jan 2018 20:54:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:23 -0800 Message-Id: <20180119045438.28582-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v2 01/16] target/arm: Mark disas_set_insn_syndrome inline X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 If it isn't used when translate.h is included, we'll get a compiler Werror. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index cd7313ace7..3f4df91e5e 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -108,7 +108,7 @@ static inline int default_exception_el(DisasContext *s) ? 3 : MAX(1, s->current_el); } =20 -static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) +static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) { /* We don't need to save all of the syndrome so we mask and shift * out unneeded bits to help the sleb128 encoder do a better job. --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516338115277850.040269884181; Thu, 18 Jan 2018 21:01:55 -0800 (PST) Received: from localhost ([::1]:52371 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOoM-00086V-B2 for importer@patchew.org; Fri, 19 Jan 2018 00:01:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58602) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOhX-00027D-L7 for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:54:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecOhU-0008T5-Sz for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:54:51 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:34382) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecOhU-0008ST-KM for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:54:48 -0500 Received: by mail-pg0-x241.google.com with SMTP id r19so561719pgn.1 for ; Thu, 18 Jan 2018 20:54:48 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.54.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:54:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cJ/sG2+QHUNjdmxtOhiJiYCY3BWFF+bfGGP6NiPjTYc=; b=FSaUilJ+9o8d7yw0PxI6gHwVAyZsfeHclfeQdX7KVy5bzmHwfiG8a8/i2OMRvnHf+6 myLPP3uEqOggUkVaDfXcQ4k+3SKtUVY4zEm1ykdMw046+Aofb8A9T227eaqz868zgQw1 7LYy1BLhZv62DyLgA/85ccjrMWuWr7f+7w+4Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cJ/sG2+QHUNjdmxtOhiJiYCY3BWFF+bfGGP6NiPjTYc=; b=HtWejaPfwsbf+RIj0nHf12q/tFSQgePYXu8N6/DEj+ytJTIcv2MZd+OKl24vegMEc4 MdXHaIwKA0pPj9wsVgLffgvVj3glDAQObtkbYLw0g7B+Sq7+ueAmvC1ggRE1G9OpcNx1 ourjMbrE+01i2JacKcJgPgigGQKYSBCXcLaCMzmrDpngETx8hdh7YFRKMGzOmRISmyHO IqKR4aOx/UDaGMSuIYuD8c/3QY2KKHRTrrdij35NkcbRrsxVdIyhTLeNY6W+s4+rwKT1 pF92NmnmPo1uW9HL0SAK7KRpzRm8n8+2Gqwpcll0QINwBIXattWUDO5oqyeyoGBag6Yr l9eg== X-Gm-Message-State: AKwxytd/752YGE6vXuTBdVhPYPs87XQ5fgI3TwzwlEmjhrZsErTtcXvb gIK9747Uzv+gJzEN6CUXAKLmbKWe41Y= X-Google-Smtp-Source: ACJfBouU7LzLBKnGG/jVMFQhpQbdaUXifIZ+R8ARLGUkM2sPVTWCGEeFutgZjwTM/+uAWWxOAfbLug== X-Received: by 10.99.168.5 with SMTP id o5mr8849171pgf.27.1516337686872; Thu, 18 Jan 2018 20:54:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:24 -0800 Message-Id: <20180119045438.28582-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v2 02/16] target/arm: Use pointers in crypto helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than passing regnos to the helpers, pass pointers to the vector registers directly. This eliminates the need to pass in the environment pointer and reduces the number of places that directly access env->vfp.regs[]. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.h | 18 ++--- target/arm/crypto_helper.c | 184 +++++++++++++++++------------------------= ---- target/arm/translate-a64.c | 75 ++++++++++-------- target/arm/translate.c | 68 +++++++++-------- 4 files changed, 161 insertions(+), 184 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 066729e8ad..688380af6b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -522,17 +522,17 @@ DEF_HELPER_3(neon_qzip8, void, env, i32, i32) DEF_HELPER_3(neon_qzip16, void, env, i32, i32) DEF_HELPER_3(neon_qzip32, void, env, i32, i32) =20 -DEF_HELPER_4(crypto_aese, void, env, i32, i32, i32) -DEF_HELPER_4(crypto_aesmc, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_3(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 -DEF_HELPER_5(crypto_sha1_3reg, void, env, i32, i32, i32, i32) -DEF_HELPER_3(crypto_sha1h, void, env, i32, i32) -DEF_HELPER_3(crypto_sha1su1, void, env, i32, i32) +DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_2(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr) =20 -DEF_HELPER_4(crypto_sha256h, void, env, i32, i32, i32) -DEF_HELPER_4(crypto_sha256h2, void, env, i32, i32, i32) -DEF_HELPER_3(crypto_sha256su0, void, env, i32, i32) -DEF_HELPER_4(crypto_sha256su1, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_3(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) +DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) =20 DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index 3b6df3f41a..9ca0bdead7 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -30,20 +30,14 @@ union CRYPTO_STATE { #define CR_ST_WORD(state, i) (state.words[i]) #endif =20 -void HELPER(crypto_aese)(CPUARMState *env, uint32_t rd, uint32_t rm, - uint32_t decrypt) +void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt) { static uint8_t const * const sbox[2] =3D { AES_sbox, AES_isbox }; static uint8_t const * const shift[2] =3D { AES_shifts, AES_ishifts }; - - union CRYPTO_STATE rk =3D { .l =3D { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; - union CRYPTO_STATE st =3D { .l =3D { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; + uint64_t *rd =3D vd; + uint64_t *rm =3D vm; + union CRYPTO_STATE rk =3D { .l =3D { rm[0], rm[1] } }; + union CRYPTO_STATE st =3D { .l =3D { rd[0], rd[1] } }; int i; =20 assert(decrypt < 2); @@ -57,12 +51,11 @@ void HELPER(crypto_aese)(CPUARMState *env, uint32_t rd,= uint32_t rm, CR_ST_BYTE(st, i) =3D sbox[decrypt][CR_ST_BYTE(rk, shift[decrypt][= i])]; } =20 - env->vfp.regs[rd] =3D make_float64(st.l[0]); - env->vfp.regs[rd + 1] =3D make_float64(st.l[1]); + rd[0] =3D st.l[0]; + rd[1] =3D st.l[1]; } =20 -void HELPER(crypto_aesmc)(CPUARMState *env, uint32_t rd, uint32_t rm, - uint32_t decrypt) +void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt) { static uint32_t const mc[][256] =3D { { /* MixColumns lookup table */ @@ -197,10 +190,10 @@ void HELPER(crypto_aesmc)(CPUARMState *env, uint32_t = rd, uint32_t rm, 0x92b479a7, 0x99b970a9, 0x84ae6bbb, 0x8fa362b5, 0xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d, } }; - union CRYPTO_STATE st =3D { .l =3D { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + + uint64_t *rd =3D vd; + uint64_t *rm =3D vm; + union CRYPTO_STATE st =3D { .l =3D { rm[0], rm[1] } }; int i; =20 assert(decrypt < 2); @@ -213,8 +206,8 @@ void HELPER(crypto_aesmc)(CPUARMState *env, uint32_t rd= , uint32_t rm, rol32(mc[decrypt][CR_ST_BYTE(st, i + 3)], 24); } =20 - env->vfp.regs[rd] =3D make_float64(st.l[0]); - env->vfp.regs[rd + 1] =3D make_float64(st.l[1]); + rd[0] =3D st.l[0]; + rd[1] =3D st.l[1]; } =20 /* @@ -236,21 +229,14 @@ static uint32_t maj(uint32_t x, uint32_t y, uint32_t = z) return (x & y) | ((x | y) & z); } =20 -void HELPER(crypto_sha1_3reg)(CPUARMState *env, uint32_t rd, uint32_t rn, - uint32_t rm, uint32_t op) +void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op) { - union CRYPTO_STATE d =3D { .l =3D { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE n =3D { .l =3D { - float64_val(env->vfp.regs[rn]), - float64_val(env->vfp.regs[rn + 1]) - } }; - union CRYPTO_STATE m =3D { .l =3D { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; =20 if (op =3D=3D 3) { /* sha1su0 */ d.l[0] ^=3D d.l[1] ^ m.l[0]; @@ -284,42 +270,37 @@ void HELPER(crypto_sha1_3reg)(CPUARMState *env, uint3= 2_t rd, uint32_t rn, CR_ST_WORD(d, 0) =3D t; } } - env->vfp.regs[rd] =3D make_float64(d.l[0]); - env->vfp.regs[rd + 1] =3D make_float64(d.l[1]); + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; } =20 -void HELPER(crypto_sha1h)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(crypto_sha1h)(void *vd, void *vm) { - union CRYPTO_STATE m =3D { .l =3D { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd =3D vd; + uint64_t *rm =3D vm; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; =20 CR_ST_WORD(m, 0) =3D ror32(CR_ST_WORD(m, 0), 2); CR_ST_WORD(m, 1) =3D CR_ST_WORD(m, 2) =3D CR_ST_WORD(m, 3) =3D 0; =20 - env->vfp.regs[rd] =3D make_float64(m.l[0]); - env->vfp.regs[rd + 1] =3D make_float64(m.l[1]); + rd[0] =3D m.l[0]; + rd[1] =3D m.l[1]; } =20 -void HELPER(crypto_sha1su1)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(crypto_sha1su1)(void *vd, void *vm) { - union CRYPTO_STATE d =3D { .l =3D { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE m =3D { .l =3D { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd =3D vd; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; =20 CR_ST_WORD(d, 0) =3D rol32(CR_ST_WORD(d, 0) ^ CR_ST_WORD(m, 1), 1); CR_ST_WORD(d, 1) =3D rol32(CR_ST_WORD(d, 1) ^ CR_ST_WORD(m, 2), 1); CR_ST_WORD(d, 2) =3D rol32(CR_ST_WORD(d, 2) ^ CR_ST_WORD(m, 3), 1); CR_ST_WORD(d, 3) =3D rol32(CR_ST_WORD(d, 3) ^ CR_ST_WORD(d, 0), 1); =20 - env->vfp.regs[rd] =3D make_float64(d.l[0]); - env->vfp.regs[rd + 1] =3D make_float64(d.l[1]); + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; } =20 /* @@ -347,21 +328,14 @@ static uint32_t s1(uint32_t x) return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10); } =20 -void HELPER(crypto_sha256h)(CPUARMState *env, uint32_t rd, uint32_t rn, - uint32_t rm) +void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm) { - union CRYPTO_STATE d =3D { .l =3D { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE n =3D { .l =3D { - float64_val(env->vfp.regs[rn]), - float64_val(env->vfp.regs[rn + 1]) - } }; - union CRYPTO_STATE m =3D { .l =3D { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; int i; =20 for (i =3D 0; i < 4; i++) { @@ -383,25 +357,18 @@ void HELPER(crypto_sha256h)(CPUARMState *env, uint32_= t rd, uint32_t rn, CR_ST_WORD(d, 0) =3D t; } =20 - env->vfp.regs[rd] =3D make_float64(d.l[0]); - env->vfp.regs[rd + 1] =3D make_float64(d.l[1]); + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; } =20 -void HELPER(crypto_sha256h2)(CPUARMState *env, uint32_t rd, uint32_t rn, - uint32_t rm) +void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm) { - union CRYPTO_STATE d =3D { .l =3D { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE n =3D { .l =3D { - float64_val(env->vfp.regs[rn]), - float64_val(env->vfp.regs[rn + 1]) - } }; - union CRYPTO_STATE m =3D { .l =3D { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; int i; =20 for (i =3D 0; i < 4; i++) { @@ -415,51 +382,40 @@ void HELPER(crypto_sha256h2)(CPUARMState *env, uint32= _t rd, uint32_t rn, CR_ST_WORD(d, 0) =3D CR_ST_WORD(n, 3 - i) + t; } =20 - env->vfp.regs[rd] =3D make_float64(d.l[0]); - env->vfp.regs[rd + 1] =3D make_float64(d.l[1]); + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; } =20 -void HELPER(crypto_sha256su0)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(crypto_sha256su0)(void *vd, void *vm) { - union CRYPTO_STATE d =3D { .l =3D { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE m =3D { .l =3D { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd =3D vd; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; =20 CR_ST_WORD(d, 0) +=3D s0(CR_ST_WORD(d, 1)); CR_ST_WORD(d, 1) +=3D s0(CR_ST_WORD(d, 2)); CR_ST_WORD(d, 2) +=3D s0(CR_ST_WORD(d, 3)); CR_ST_WORD(d, 3) +=3D s0(CR_ST_WORD(m, 0)); =20 - env->vfp.regs[rd] =3D make_float64(d.l[0]); - env->vfp.regs[rd + 1] =3D make_float64(d.l[1]); + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; } =20 -void HELPER(crypto_sha256su1)(CPUARMState *env, uint32_t rd, uint32_t rn, - uint32_t rm) +void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm) { - union CRYPTO_STATE d =3D { .l =3D { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE n =3D { .l =3D { - float64_val(env->vfp.regs[rn]), - float64_val(env->vfp.regs[rn + 1]) - } }; - union CRYPTO_STATE m =3D { .l =3D { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd =3D vd; + uint64_t *rn =3D vn; + uint64_t *rm =3D vm; + union CRYPTO_STATE d =3D { .l =3D { rd[0], rd[1] } }; + union CRYPTO_STATE n =3D { .l =3D { rn[0], rn[1] } }; + union CRYPTO_STATE m =3D { .l =3D { rm[0], rm[1] } }; =20 CR_ST_WORD(d, 0) +=3D s1(CR_ST_WORD(m, 2)) + CR_ST_WORD(n, 1); CR_ST_WORD(d, 1) +=3D s1(CR_ST_WORD(m, 3)) + CR_ST_WORD(n, 2); CR_ST_WORD(d, 2) +=3D s1(CR_ST_WORD(d, 0)) + CR_ST_WORD(n, 3); CR_ST_WORD(d, 3) +=3D s1(CR_ST_WORD(d, 1)) + CR_ST_WORD(m, 0); =20 - env->vfp.regs[rd] =3D make_float64(d.l[0]); - env->vfp.regs[rd + 1] =3D make_float64(d.l[1]); + rd[0] =3D d.l[0]; + rd[1] =3D d.l[1]; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 70c1e08a36..6d9b3af64c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -80,8 +80,9 @@ typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); -typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32); -typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); +typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); +typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); +typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); =20 /* initialize TCG globals. */ void a64_translate_init(void) @@ -535,6 +536,21 @@ static inline int vec_reg_offset(DisasContext *s, int = regno, return offs; } =20 +/* Return the offset info CPUARMState of the "whole" vector register Qn. = */ +static inline int vec_full_reg_offset(DisasContext *s, int regno) +{ + assert_fp_access_checked(s); + return offsetof(CPUARMState, vfp.regs[regno * 2]); +} + +/* Return a newly allocated pointer to the vector register. */ +static TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno) +{ + TCGv_ptr ret =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno)); + return ret; +} + /* Return the offset into CPUARMState of a slice (from * the least significant end) of FP register Qn (ie * Dn, Sn, Hn or Bn). @@ -10949,8 +10965,9 @@ static void disas_crypto_aes(DisasContext *s, uint3= 2_t insn) int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); int decrypt; - TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_decrypt; - CryptoThreeOpEnvFn *genfn; + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; + TCGv_i32 tcg_decrypt; + CryptoThreeOpIntFn *genfn; =20 if (!arm_dc_feature(s, ARM_FEATURE_V8_AES) || size !=3D 0) { @@ -10984,18 +11001,14 @@ static void disas_crypto_aes(DisasContext *s, uin= t32_t insn) return; } =20 - /* Note that we convert the Vx register indexes into the - * index within the vfp.regs[] array, so we can share the - * helper with the AArch32 instructions. - */ - tcg_rd_regno =3D tcg_const_i32(rd << 1); - tcg_rn_regno =3D tcg_const_i32(rn << 1); + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); tcg_decrypt =3D tcg_const_i32(decrypt); =20 - genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_decrypt); + genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt); =20 - tcg_temp_free_i32(tcg_rd_regno); - tcg_temp_free_i32(tcg_rn_regno); + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); tcg_temp_free_i32(tcg_decrypt); } =20 @@ -11012,8 +11025,8 @@ static void disas_crypto_three_reg_sha(DisasContext= *s, uint32_t insn) int rm =3D extract32(insn, 16, 5); int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); - CryptoThreeOpEnvFn *genfn; - TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_rm_regno; + CryptoThreeOpFn *genfn; + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; int feature =3D ARM_FEATURE_V8_SHA256; =20 if (size !=3D 0) { @@ -11052,23 +11065,23 @@ static void disas_crypto_three_reg_sha(DisasConte= xt *s, uint32_t insn) return; } =20 - tcg_rd_regno =3D tcg_const_i32(rd << 1); - tcg_rn_regno =3D tcg_const_i32(rn << 1); - tcg_rm_regno =3D tcg_const_i32(rm << 1); + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); + tcg_rm_ptr =3D vec_full_reg_ptr(s, rm); =20 if (genfn) { - genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_rm_regno); + genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr); } else { TCGv_i32 tcg_opcode =3D tcg_const_i32(opcode); =20 - gen_helper_crypto_sha1_3reg(cpu_env, tcg_rd_regno, - tcg_rn_regno, tcg_rm_regno, tcg_opcode= ); + gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr, + tcg_rm_ptr, tcg_opcode); tcg_temp_free_i32(tcg_opcode); } =20 - tcg_temp_free_i32(tcg_rd_regno); - tcg_temp_free_i32(tcg_rn_regno); - tcg_temp_free_i32(tcg_rm_regno); + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); + tcg_temp_free_ptr(tcg_rm_ptr); } =20 /* Crypto two-reg SHA @@ -11083,9 +11096,9 @@ static void disas_crypto_two_reg_sha(DisasContext *= s, uint32_t insn) int opcode =3D extract32(insn, 12, 5); int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); - CryptoTwoOpEnvFn *genfn; + CryptoTwoOpFn *genfn; int feature; - TCGv_i32 tcg_rd_regno, tcg_rn_regno; + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; =20 if (size !=3D 0) { unallocated_encoding(s); @@ -11119,13 +11132,13 @@ static void disas_crypto_two_reg_sha(DisasContext= *s, uint32_t insn) return; } =20 - tcg_rd_regno =3D tcg_const_i32(rd << 1); - tcg_rn_regno =3D tcg_const_i32(rn << 1); + tcg_rd_ptr =3D vec_full_reg_ptr(s, rd); + tcg_rn_ptr =3D vec_full_reg_ptr(s, rn); =20 - genfn(cpu_env, tcg_rd_regno, tcg_rn_regno); + genfn(tcg_rd_ptr, tcg_rn_ptr); =20 - tcg_temp_free_i32(tcg_rd_regno); - tcg_temp_free_i32(tcg_rn_regno); + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); } =20 /* C3.6 Data processing - SIMD, inc Crypto diff --git a/target/arm/translate.c b/target/arm/translate.c index 781be1e219..7b5db15861 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1559,6 +1559,13 @@ static inline void neon_store_reg64(TCGv_i64 var, in= t reg) tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); } =20 +static TCGv_ptr vfp_reg_ptr(bool dp, int reg) +{ + TCGv_ptr ret =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); + return ret; +} + #define tcg_gen_ld_f32 tcg_gen_ld_i32 #define tcg_gen_ld_f64 tcg_gen_ld_i64 #define tcg_gen_st_f32 tcg_gen_st_i32 @@ -5597,6 +5604,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) int u; uint32_t imm, mask; TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5; + TCGv_ptr ptr1, ptr2, ptr3; TCGv_i64 tmp64; =20 /* FIXME: this access check should not take precedence over UNDEF @@ -5643,34 +5651,34 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) { return 1; } - tmp =3D tcg_const_i32(rd); - tmp2 =3D tcg_const_i32(rn); - tmp3 =3D tcg_const_i32(rm); + ptr1 =3D vfp_reg_ptr(true, rd); + ptr2 =3D vfp_reg_ptr(true, rn); + ptr3 =3D vfp_reg_ptr(true, rm); tmp4 =3D tcg_const_i32(size); - gen_helper_crypto_sha1_3reg(cpu_env, tmp, tmp2, tmp3, tmp4= ); + gen_helper_crypto_sha1_3reg(ptr1, ptr2, ptr3, tmp4); tcg_temp_free_i32(tmp4); } else { /* SHA-256 */ if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA256) || size =3D= =3D 3) { return 1; } - tmp =3D tcg_const_i32(rd); - tmp2 =3D tcg_const_i32(rn); - tmp3 =3D tcg_const_i32(rm); + ptr1 =3D vfp_reg_ptr(true, rd); + ptr2 =3D vfp_reg_ptr(true, rn); + ptr3 =3D vfp_reg_ptr(true, rm); switch (size) { case 0: - gen_helper_crypto_sha256h(cpu_env, tmp, tmp2, tmp3); + gen_helper_crypto_sha256h(ptr1, ptr2, ptr3); break; case 1: - gen_helper_crypto_sha256h2(cpu_env, tmp, tmp2, tmp3); + gen_helper_crypto_sha256h2(ptr1, ptr2, ptr3); break; case 2: - gen_helper_crypto_sha256su1(cpu_env, tmp, tmp2, tmp3); + gen_helper_crypto_sha256su1(ptr1, ptr2, ptr3); break; } } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); + tcg_temp_free_ptr(ptr3); return 0; } if (size =3D=3D 3 && op !=3D NEON_3R_LOGIC) { @@ -7159,8 +7167,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) || ((rm | rd) & 1)) { return 1; } - tmp =3D tcg_const_i32(rd); - tmp2 =3D tcg_const_i32(rm); + ptr1 =3D vfp_reg_ptr(true, rd); + ptr2 =3D vfp_reg_ptr(true, rm); =20 /* Bit 6 is the lowest opcode bit; it distinguishes b= etween * encryption (AESE/AESMC) and decryption (AESD/AESIM= C) @@ -7168,12 +7176,12 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) tmp3 =3D tcg_const_i32(extract32(insn, 6, 1)); =20 if (op =3D=3D NEON_2RM_AESE) { - gen_helper_crypto_aese(cpu_env, tmp, tmp2, tmp3); + gen_helper_crypto_aese(ptr1, ptr2, tmp3); } else { - gen_helper_crypto_aesmc(cpu_env, tmp, tmp2, tmp3); + gen_helper_crypto_aesmc(ptr1, ptr2, tmp3); } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); tcg_temp_free_i32(tmp3); break; case NEON_2RM_SHA1H: @@ -7181,13 +7189,13 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) || ((rm | rd) & 1)) { return 1; } - tmp =3D tcg_const_i32(rd); - tmp2 =3D tcg_const_i32(rm); + ptr1 =3D vfp_reg_ptr(true, rd); + ptr2 =3D vfp_reg_ptr(true, rm); =20 - gen_helper_crypto_sha1h(cpu_env, tmp, tmp2); + gen_helper_crypto_sha1h(ptr1, ptr2); =20 - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); break; case NEON_2RM_SHA1SU1: if ((rm | rd) & 1) { @@ -7201,15 +7209,15 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) } else if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) { return 1; } - tmp =3D tcg_const_i32(rd); - tmp2 =3D tcg_const_i32(rm); + ptr1 =3D vfp_reg_ptr(true, rd); + ptr2 =3D vfp_reg_ptr(true, rm); if (q) { - gen_helper_crypto_sha256su0(cpu_env, tmp, tmp2); + gen_helper_crypto_sha256su0(ptr1, ptr2); } else { - gen_helper_crypto_sha1su1(cpu_env, tmp, tmp2); + gen_helper_crypto_sha1su1(ptr1, ptr2); } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); break; default: elementwise: --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516337960795471.74472332219045; Thu, 18 Jan 2018 20:59:20 -0800 (PST) Received: from localhost ([::1]:52336 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOlj-0005mM-L6 for importer@patchew.org; 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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.54.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:54:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cqrA8CU4eKHFUueqSZ+9jYOSEtrX5Z7lO22SsZclNa8=; b=hKZcTZtipnou93Si/P8M65jD2QZkAz+Gzk3k/kXmIAIJwNaLbrpgv8/y16ZE6AhPFf iKRr+gr2MzKcFrMW5jAE2TubvN4bOdet3OdxEgRMNzNYOx6h6mPF2pTEMtiqm/OF6QrW BrCCpjbcWcywqG9gEpd2wwMhFAhRlIUIoZCxI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cqrA8CU4eKHFUueqSZ+9jYOSEtrX5Z7lO22SsZclNa8=; b=SQW9tCpm4WQey4UyF0YZmMIFp+k7qtJViiXGUZfQplqZKSBHXPUwrx1q1cumbG/cYf suT2+rYMo46KFeo0rrONCD9FTX37JCx0nOYlohKFitScFXtuqG3Zbuj/IqxRTQ2KhM7z TDEHAa7iOLbPM/RnH/pIOr1yZNh4vzemrbFV+5Gwbf3z0O7CtYcgwHrq/kHm+jSvXXG0 oGo6gaYoGa0Z4gDyh5ZNJmgh+wkwvBZlQ+WNrVFrV1ymDKRBe7F9wPg4iGUVuQ61hsFb jwSyW06gN5IbacorKDYpvxeHQzM9GYwRerYhRtJeG++BfAdI4A9puuXTxyEe7LVAOyc/ icqA== X-Gm-Message-State: AKGB3mKjoqN95I3Y4m7Sli1FB9Qp3sMr2hABtKCbK0M6OoPYgA5RoJZe lqZ6mzSWVF76z/xQ3XNlmiiFEa/l4sQ= X-Google-Smtp-Source: ACJfBovM5goBKRdSGdtU6WztfnQ+ppkWxU9UPIgPTgf0d/H4B/fogVQPRy6OOqkzmOLgpl4rn/hqIQ== X-Received: by 10.99.175.66 with SMTP id s2mr39379313pgo.168.1516337688489; Thu, 18 Jan 2018 20:54:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:25 -0800 Message-Id: <20180119045438.28582-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 03/16] target/arm: Use pointers in neon zip/uzp helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than passing regnos to the helpers, pass pointers to the vector registers directly. This eliminates the need to pass in the environment pointer and reduces the number of places that directly access env->vfp.regs[]. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.h | 20 +++--- target/arm/neon_helper.c | 162 +++++++++++++++++++++++++------------------= ---- target/arm/translate.c | 42 ++++++------ 3 files changed, 120 insertions(+), 104 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 688380af6b..dbdc38fcb7 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -511,16 +511,16 @@ DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) =20 -DEF_HELPER_3(neon_unzip8, void, env, i32, i32) -DEF_HELPER_3(neon_unzip16, void, env, i32, i32) -DEF_HELPER_3(neon_qunzip8, void, env, i32, i32) -DEF_HELPER_3(neon_qunzip16, void, env, i32, i32) -DEF_HELPER_3(neon_qunzip32, void, env, i32, i32) -DEF_HELPER_3(neon_zip8, void, env, i32, i32) -DEF_HELPER_3(neon_zip16, void, env, i32, i32) -DEF_HELPER_3(neon_qzip8, void, env, i32, i32) -DEF_HELPER_3(neon_qzip16, void, env, i32, i32) -DEF_HELPER_3(neon_qzip32, void, env, i32, i32) +DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip32, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) =20 DEF_HELPER_FLAGS_3(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index ebdf7c9b10..689491cad3 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -2027,12 +2027,12 @@ uint64_t HELPER(neon_acgt_f64)(uint64_t a, uint64_t= b, void *fpstp) =20 #define ELEM(V, N, SIZE) (((V) >> ((N) * (SIZE))) & ((1ull << (SIZE)) - 1)) =20 -void HELPER(neon_qunzip8)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qunzip8)(void *vd, void *vm) { - uint64_t zm0 =3D float64_val(env->vfp.regs[rm]); - uint64_t zm1 =3D float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 =3D float64_val(env->vfp.regs[rd]); - uint64_t zd1 =3D float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd =3D vd, *rm =3D vm; + uint64_t zd0 =3D rd[0], zd1 =3D rd[1]; + uint64_t zm0 =3D rm[0], zm1 =3D rm[1]; + uint64_t d0 =3D ELEM(zd0, 0, 8) | (ELEM(zd0, 2, 8) << 8) | (ELEM(zd0, 4, 8) << 16) | (ELEM(zd0, 6, 8) << 24) | (ELEM(zd1, 0, 8) << 32) | (ELEM(zd1, 2, 8) << 40) @@ -2049,18 +2049,19 @@ void HELPER(neon_qunzip8)(CPUARMState *env, uint32_= t rd, uint32_t rm) | (ELEM(zm0, 5, 8) << 16) | (ELEM(zm0, 7, 8) << 24) | (ELEM(zm1, 1, 8) << 32) | (ELEM(zm1, 3, 8) << 40) | (ELEM(zm1, 5, 8) << 48) | (ELEM(zm1, 7, 8) << 56); - env->vfp.regs[rm] =3D make_float64(m0); - env->vfp.regs[rm + 1] =3D make_float64(m1); - env->vfp.regs[rd] =3D make_float64(d0); - env->vfp.regs[rd + 1] =3D make_float64(d1); + + rm[0] =3D m0; + rm[1] =3D m1; + rd[0] =3D d0; + rd[1] =3D d1; } =20 -void HELPER(neon_qunzip16)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qunzip16)(void *vd, void *vm) { - uint64_t zm0 =3D float64_val(env->vfp.regs[rm]); - uint64_t zm1 =3D float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 =3D float64_val(env->vfp.regs[rd]); - uint64_t zd1 =3D float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd =3D vd, *rm =3D vm; + uint64_t zd0 =3D rd[0], zd1 =3D rd[1]; + uint64_t zm0 =3D rm[0], zm1 =3D rm[1]; + uint64_t d0 =3D ELEM(zd0, 0, 16) | (ELEM(zd0, 2, 16) << 16) | (ELEM(zd1, 0, 16) << 32) | (ELEM(zd1, 2, 16) << 48); uint64_t d1 =3D ELEM(zm0, 0, 16) | (ELEM(zm0, 2, 16) << 16) @@ -2069,32 +2070,35 @@ void HELPER(neon_qunzip16)(CPUARMState *env, uint32= _t rd, uint32_t rm) | (ELEM(zd1, 1, 16) << 32) | (ELEM(zd1, 3, 16) << 48); uint64_t m1 =3D ELEM(zm0, 1, 16) | (ELEM(zm0, 3, 16) << 16) | (ELEM(zm1, 1, 16) << 32) | (ELEM(zm1, 3, 16) << 48); - env->vfp.regs[rm] =3D make_float64(m0); - env->vfp.regs[rm + 1] =3D make_float64(m1); - env->vfp.regs[rd] =3D make_float64(d0); - env->vfp.regs[rd + 1] =3D make_float64(d1); + + rm[0] =3D m0; + rm[1] =3D m1; + rd[0] =3D d0; + rd[1] =3D d1; } =20 -void HELPER(neon_qunzip32)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qunzip32)(void *vd, void *vm) { - uint64_t zm0 =3D float64_val(env->vfp.regs[rm]); - uint64_t zm1 =3D float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 =3D float64_val(env->vfp.regs[rd]); - uint64_t zd1 =3D float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd =3D vd, *rm =3D vm; + uint64_t zd0 =3D rd[0], zd1 =3D rd[1]; + uint64_t zm0 =3D rm[0], zm1 =3D rm[1]; + uint64_t d0 =3D ELEM(zd0, 0, 32) | (ELEM(zd1, 0, 32) << 32); uint64_t d1 =3D ELEM(zm0, 0, 32) | (ELEM(zm1, 0, 32) << 32); uint64_t m0 =3D ELEM(zd0, 1, 32) | (ELEM(zd1, 1, 32) << 32); uint64_t m1 =3D ELEM(zm0, 1, 32) | (ELEM(zm1, 1, 32) << 32); - env->vfp.regs[rm] =3D make_float64(m0); - env->vfp.regs[rm + 1] =3D make_float64(m1); - env->vfp.regs[rd] =3D make_float64(d0); - env->vfp.regs[rd + 1] =3D make_float64(d1); + + rm[0] =3D m0; + rm[1] =3D m1; + rd[0] =3D d0; + rd[1] =3D d1; } =20 -void HELPER(neon_unzip8)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_unzip8)(void *vd, void *vm) { - uint64_t zm =3D float64_val(env->vfp.regs[rm]); - uint64_t zd =3D float64_val(env->vfp.regs[rd]); + uint64_t *rd =3D vd, *rm =3D vm; + uint64_t zd =3D rd[0], zm =3D rm[0]; + uint64_t d0 =3D ELEM(zd, 0, 8) | (ELEM(zd, 2, 8) << 8) | (ELEM(zd, 4, 8) << 16) | (ELEM(zd, 6, 8) << 24) | (ELEM(zm, 0, 8) << 32) | (ELEM(zm, 2, 8) << 40) @@ -2103,28 +2107,31 @@ void HELPER(neon_unzip8)(CPUARMState *env, uint32_t= rd, uint32_t rm) | (ELEM(zd, 5, 8) << 16) | (ELEM(zd, 7, 8) << 24) | (ELEM(zm, 1, 8) << 32) | (ELEM(zm, 3, 8) << 40) | (ELEM(zm, 5, 8) << 48) | (ELEM(zm, 7, 8) << 56); - env->vfp.regs[rm] =3D make_float64(m0); - env->vfp.regs[rd] =3D make_float64(d0); + + rm[0] =3D m0; + rd[0] =3D d0; } =20 -void HELPER(neon_unzip16)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_unzip16)(void *vd, void *vm) { - uint64_t zm =3D float64_val(env->vfp.regs[rm]); - uint64_t zd =3D float64_val(env->vfp.regs[rd]); + uint64_t *rd =3D vd, *rm =3D vm; + uint64_t zd =3D rd[0], zm =3D rm[0]; + uint64_t d0 =3D ELEM(zd, 0, 16) | (ELEM(zd, 2, 16) << 16) | (ELEM(zm, 0, 16) << 32) | (ELEM(zm, 2, 16) << 48); uint64_t m0 =3D ELEM(zd, 1, 16) | (ELEM(zd, 3, 16) << 16) | (ELEM(zm, 1, 16) << 32) | (ELEM(zm, 3, 16) << 48); - env->vfp.regs[rm] =3D make_float64(m0); - env->vfp.regs[rd] =3D make_float64(d0); + + rm[0] =3D m0; + rd[0] =3D d0; } =20 -void HELPER(neon_qzip8)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qzip8)(void *vd, void *vm) { - uint64_t zm0 =3D float64_val(env->vfp.regs[rm]); - uint64_t zm1 =3D float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 =3D float64_val(env->vfp.regs[rd]); - uint64_t zd1 =3D float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd =3D vd, *rm =3D vm; + uint64_t zd0 =3D rd[0], zd1 =3D rd[1]; + uint64_t zm0 =3D rm[0], zm1 =3D rm[1]; + uint64_t d0 =3D ELEM(zd0, 0, 8) | (ELEM(zm0, 0, 8) << 8) | (ELEM(zd0, 1, 8) << 16) | (ELEM(zm0, 1, 8) << 24) | (ELEM(zd0, 2, 8) << 32) | (ELEM(zm0, 2, 8) << 40) @@ -2141,18 +2148,19 @@ void HELPER(neon_qzip8)(CPUARMState *env, uint32_t = rd, uint32_t rm) | (ELEM(zd1, 5, 8) << 16) | (ELEM(zm1, 5, 8) << 24) | (ELEM(zd1, 6, 8) << 32) | (ELEM(zm1, 6, 8) << 40) | (ELEM(zd1, 7, 8) << 48) | (ELEM(zm1, 7, 8) << 56); - env->vfp.regs[rm] =3D make_float64(m0); - env->vfp.regs[rm + 1] =3D make_float64(m1); - env->vfp.regs[rd] =3D make_float64(d0); - env->vfp.regs[rd + 1] =3D make_float64(d1); + + rm[0] =3D m0; + rm[1] =3D m1; + rd[0] =3D d0; + rd[1] =3D d1; } =20 -void HELPER(neon_qzip16)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qzip16)(void *vd, void *vm) { - uint64_t zm0 =3D float64_val(env->vfp.regs[rm]); - uint64_t zm1 =3D float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 =3D float64_val(env->vfp.regs[rd]); - uint64_t zd1 =3D float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd =3D vd, *rm =3D vm; + uint64_t zd0 =3D rd[0], zd1 =3D rd[1]; + uint64_t zm0 =3D rm[0], zm1 =3D rm[1]; + uint64_t d0 =3D ELEM(zd0, 0, 16) | (ELEM(zm0, 0, 16) << 16) | (ELEM(zd0, 1, 16) << 32) | (ELEM(zm0, 1, 16) << 48); uint64_t d1 =3D ELEM(zd0, 2, 16) | (ELEM(zm0, 2, 16) << 16) @@ -2161,32 +2169,35 @@ void HELPER(neon_qzip16)(CPUARMState *env, uint32_t= rd, uint32_t rm) | (ELEM(zd1, 1, 16) << 32) | (ELEM(zm1, 1, 16) << 48); uint64_t m1 =3D ELEM(zd1, 2, 16) | (ELEM(zm1, 2, 16) << 16) | (ELEM(zd1, 3, 16) << 32) | (ELEM(zm1, 3, 16) << 48); - env->vfp.regs[rm] =3D make_float64(m0); - env->vfp.regs[rm + 1] =3D make_float64(m1); - env->vfp.regs[rd] =3D make_float64(d0); - env->vfp.regs[rd + 1] =3D make_float64(d1); + + rm[0] =3D m0; + rm[1] =3D m1; + rd[0] =3D d0; + rd[1] =3D d1; } =20 -void HELPER(neon_qzip32)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qzip32)(void *vd, void *vm) { - uint64_t zm0 =3D float64_val(env->vfp.regs[rm]); - uint64_t zm1 =3D float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 =3D float64_val(env->vfp.regs[rd]); - uint64_t zd1 =3D float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd =3D vd, *rm =3D vm; + uint64_t zd0 =3D rd[0], zd1 =3D rd[1]; + uint64_t zm0 =3D rm[0], zm1 =3D rm[1]; + uint64_t d0 =3D ELEM(zd0, 0, 32) | (ELEM(zm0, 0, 32) << 32); uint64_t d1 =3D ELEM(zd0, 1, 32) | (ELEM(zm0, 1, 32) << 32); uint64_t m0 =3D ELEM(zd1, 0, 32) | (ELEM(zm1, 0, 32) << 32); uint64_t m1 =3D ELEM(zd1, 1, 32) | (ELEM(zm1, 1, 32) << 32); - env->vfp.regs[rm] =3D make_float64(m0); - env->vfp.regs[rm + 1] =3D make_float64(m1); - env->vfp.regs[rd] =3D make_float64(d0); - env->vfp.regs[rd + 1] =3D make_float64(d1); + + rm[0] =3D m0; + rm[1] =3D m1; + rd[0] =3D d0; + rd[1] =3D d1; } =20 -void HELPER(neon_zip8)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_zip8)(void *vd, void *vm) { - uint64_t zm =3D float64_val(env->vfp.regs[rm]); - uint64_t zd =3D float64_val(env->vfp.regs[rd]); + uint64_t *rd =3D vd, *rm =3D vm; + uint64_t zd =3D rd[0], zm =3D rm[0]; + uint64_t d0 =3D ELEM(zd, 0, 8) | (ELEM(zm, 0, 8) << 8) | (ELEM(zd, 1, 8) << 16) | (ELEM(zm, 1, 8) << 24) | (ELEM(zd, 2, 8) << 32) | (ELEM(zm, 2, 8) << 40) @@ -2195,20 +2206,23 @@ void HELPER(neon_zip8)(CPUARMState *env, uint32_t r= d, uint32_t rm) | (ELEM(zd, 5, 8) << 16) | (ELEM(zm, 5, 8) << 24) | (ELEM(zd, 6, 8) << 32) | (ELEM(zm, 6, 8) << 40) | (ELEM(zd, 7, 8) << 48) | (ELEM(zm, 7, 8) << 56); - env->vfp.regs[rm] =3D make_float64(m0); - env->vfp.regs[rd] =3D make_float64(d0); + + rm[0] =3D m0; + rd[0] =3D d0; } =20 -void HELPER(neon_zip16)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_zip16)(void *vd, void *vm) { - uint64_t zm =3D float64_val(env->vfp.regs[rm]); - uint64_t zd =3D float64_val(env->vfp.regs[rd]); + uint64_t *rd =3D vd, *rm =3D vm; + uint64_t zd =3D rd[0], zm =3D rm[0]; + uint64_t d0 =3D ELEM(zd, 0, 16) | (ELEM(zm, 0, 16) << 16) | (ELEM(zd, 1, 16) << 32) | (ELEM(zm, 1, 16) << 48); uint64_t m0 =3D ELEM(zd, 2, 16) | (ELEM(zm, 2, 16) << 16) | (ELEM(zd, 3, 16) << 32) | (ELEM(zm, 3, 16) << 48); - env->vfp.regs[rm] =3D make_float64(m0); - env->vfp.regs[rd] =3D make_float64(d0); + + rm[0] =3D m0; + rd[0] =3D d0; } =20 /* Helper function for 64 bit polynomial multiply case: diff --git a/target/arm/translate.c b/target/arm/translate.c index 7b5db15861..6f02c56abb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4687,22 +4687,23 @@ static inline TCGv_i32 neon_get_scalar(int size, in= t reg) =20 static int gen_neon_unzip(int rd, int rm, int size, int q) { - TCGv_i32 tmp, tmp2; + TCGv_ptr pd, pm; + =20 if (!q && size =3D=3D 2) { return 1; } - tmp =3D tcg_const_i32(rd); - tmp2 =3D tcg_const_i32(rm); + pd =3D vfp_reg_ptr(true, rd); + pm =3D vfp_reg_ptr(true, rm); if (q) { switch (size) { case 0: - gen_helper_neon_qunzip8(cpu_env, tmp, tmp2); + gen_helper_neon_qunzip8(pd, pm); break; case 1: - gen_helper_neon_qunzip16(cpu_env, tmp, tmp2); + gen_helper_neon_qunzip16(pd, pm); break; case 2: - gen_helper_neon_qunzip32(cpu_env, tmp, tmp2); + gen_helper_neon_qunzip32(pd, pm); break; default: abort(); @@ -4710,38 +4711,39 @@ static int gen_neon_unzip(int rd, int rm, int size,= int q) } else { switch (size) { case 0: - gen_helper_neon_unzip8(cpu_env, tmp, tmp2); + gen_helper_neon_unzip8(pd, pm); break; case 1: - gen_helper_neon_unzip16(cpu_env, tmp, tmp2); + gen_helper_neon_unzip16(pd, pm); break; default: abort(); } } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(pd); + tcg_temp_free_ptr(pm); return 0; } =20 static int gen_neon_zip(int rd, int rm, int size, int q) { - TCGv_i32 tmp, tmp2; + TCGv_ptr pd, pm; + if (!q && size =3D=3D 2) { return 1; } - tmp =3D tcg_const_i32(rd); - tmp2 =3D tcg_const_i32(rm); + pd =3D vfp_reg_ptr(true, rd); + pm =3D vfp_reg_ptr(true, rm); if (q) { switch (size) { case 0: - gen_helper_neon_qzip8(cpu_env, tmp, tmp2); + gen_helper_neon_qzip8(pd, pm); break; case 1: - gen_helper_neon_qzip16(cpu_env, tmp, tmp2); + gen_helper_neon_qzip16(pd, pm); break; case 2: - gen_helper_neon_qzip32(cpu_env, tmp, tmp2); + gen_helper_neon_qzip32(pd, pm); break; default: abort(); @@ -4749,17 +4751,17 @@ static int gen_neon_zip(int rd, int rm, int size, i= nt q) } else { switch (size) { case 0: - gen_helper_neon_zip8(cpu_env, tmp, tmp2); + gen_helper_neon_zip8(pd, pm); break; case 1: - gen_helper_neon_zip16(cpu_env, tmp, tmp2); + gen_helper_neon_zip16(pd, pm); break; default: abort(); } } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(pd); + tcg_temp_free_ptr(pm); return 0; } =20 --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.54.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:54:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ic8DS/8F1ksiM2fAC/o/diUdxahtrTm3gKg3dhh/7c4=; b=LRkTO6ogihmxW6L1FcaZnp/Lkw1eaBgrH1/FU5oDZCAJZFfRyIHIxnOqv5lpTESPyr F0vQpWE8LbVAwgJWGAbwZrdWPEqUOl3i41RaFKa4UhZ1I9JN/lbFSB1KAHKhRQUa+8e4 ESHfH/cHeS3QYVPXnQM4VGD24lmVMZi0ikml0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ic8DS/8F1ksiM2fAC/o/diUdxahtrTm3gKg3dhh/7c4=; b=URDbfIWxQcKUP145xVz9jX5i2ohmw+6RsZS99MBP/6ADU1Pgyt9HtxfBbpGQ2lGbx6 /iSXUlQJs0w8CROS0Z7HCm8eLTz+k0cW93BZoSDkRQKWJiJhMmby9C5+5HaNrwEJKpzg 40tqMw/XdGwhNdC176ZAcOV05/QizJwO8w1Dgf82ddv1mUeW2Uh8rbZ1/H0nZT4Ngh7u Z9zJ+VDey0ukxoZDqmZSCqqpq6YqwP5IumPn8yw5jsg8ZrcxacVBMSQYy1E5tTFFZ/Jj nPsPNlxUP5G69JI0eQIoZ1NPGmDaWLSsHULQ786dL9LOJXOoFyhlrrAM9fy8BL7endJx ERwg== X-Gm-Message-State: AKwxyteSFA4CbIt43q+4MMl22ADCCdzdWmjTFscSHAfg22wFlJzQ/XfC fz4aPihfcblRcrCqXClaFq1V/5row6w= X-Google-Smtp-Source: ACJfBovVblp1sUEJFTGYKXP4KoxZaBmX/ZCRn3Vg5q8QEllbnGivOPzpdOE4fGHye1KgUJ1hCpUyIg== X-Received: by 10.101.90.202 with SMTP id d10mr16805769pgt.366.1516337690107; Thu, 18 Jan 2018 20:54:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:26 -0800 Message-Id: <20180119045438.28582-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 04/16] target/arm: Use pointers in neon tbl helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than passing a regno to the helper, pass pointers to the vector register directly. This eliminates the need to pass in the environment pointer and reduces the number of places that directly access env->vfp.regs[]. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.h | 2 +- target/arm/op_helper.c | 17 +++++++---------- target/arm/translate.c | 8 ++++---- 3 files changed, 12 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index dbdc38fcb7..5dec2e6262 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -188,7 +188,7 @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f3= 2, ptr) DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_2(recpe_u32, i32, i32, ptr) DEF_HELPER_FLAGS_2(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32, ptr) -DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32) +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32) =20 DEF_HELPER_3(shl_cc, i32, env, i32, i32) DEF_HELPER_3(shr_cc, i32, env, i32, i32) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 712c5c55b6..a937e76710 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -54,20 +54,17 @@ static int exception_target_el(CPUARMState *env) return target_el; } =20 -uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, - uint32_t rn, uint32_t maxindex) +uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, + uint32_t maxindex) { - uint32_t val; - uint32_t tmp; - int index; - int shift; - uint64_t *table; - table =3D (uint64_t *)&env->vfp.regs[rn]; + uint32_t val, shift; + uint64_t *table =3D vn; + val =3D 0; for (shift =3D 0; shift < 32; shift +=3D 8) { - index =3D (ireg >> shift) & 0xff; + uint32_t index =3D (ireg >> shift) & 0xff; if (index < maxindex) { - tmp =3D (table[index >> 3] >> ((index & 7) << 3)) & 0xff; + uint32_t tmp =3D (table[index >> 3] >> ((index & 7) << 3)) & 0= xff; val |=3D tmp << shift; } else { val |=3D def & (0xff << shift); diff --git a/target/arm/translate.c b/target/arm/translate.c index 6f02c56abb..852d2a75b1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7544,9 +7544,9 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) tcg_gen_movi_i32(tmp, 0); } tmp2 =3D neon_load_reg(rm, 0); - tmp4 =3D tcg_const_i32(rn); + ptr1 =3D vfp_reg_ptr(true, rn); tmp5 =3D tcg_const_i32(n); - gen_helper_neon_tbl(tmp2, cpu_env, tmp2, tmp, tmp4, tmp5); + gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp5); tcg_temp_free_i32(tmp); if (insn & (1 << 6)) { tmp =3D neon_load_reg(rd, 1); @@ -7555,9 +7555,9 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) tcg_gen_movi_i32(tmp, 0); } tmp3 =3D neon_load_reg(rm, 1); - gen_helper_neon_tbl(tmp3, cpu_env, tmp3, tmp, tmp4, tmp5); + gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp5); tcg_temp_free_i32(tmp5); - tcg_temp_free_i32(tmp4); + tcg_temp_free_ptr(ptr1); neon_store_reg(rd, 0, tmp2); neon_store_reg(rd, 1, tmp3); tcg_temp_free_i32(tmp); --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516338178086931.6480906092555; Thu, 18 Jan 2018 21:02:58 -0800 (PST) Received: from localhost ([::1]:52374 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOpN-0000XS-5e for importer@patchew.org; Fri, 19 Jan 2018 00:02:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58665) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOhe-0002Dp-FX for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecOhZ-000082-EK for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:54:58 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:44270) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecOhZ-00007D-7G for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:54:53 -0500 Received: by mail-pg0-x244.google.com with SMTP id m20so542856pgc.11 for ; Thu, 18 Jan 2018 20:54:53 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.54.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:54:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Yo+KKaXQDW/cSbgDkS0iYkcPRfDiRNJyQO+3skiGz7Q=; b=JlKeIgMGea6C+ZiqNEV0aJ3PZEz0nbg8qvNQr0g7G6o3Wg/7tVMivrxFgU7LmhoJ1o YVFPllyG58kPrdV6RcNWEfa4jt2qU4AcvkbYq9FC/iFj96DcHdu8kTeyYPTl+HOnZS0b rXq5vEmKf5pupfh6VUAqPqd2c1XBly+bRs77c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Yo+KKaXQDW/cSbgDkS0iYkcPRfDiRNJyQO+3skiGz7Q=; b=TBZ4qzjR7v93OtypFnJhKY1w4sb1m0uRAuHt4gj12P+2V+TFM+I7wq94yZsMPZbFvH eGwkiEBcfNG8deAG9Y0qrSXdNqfCiTsomfNwayA0W3uEITtJgjLNbdwA3EVNkqaIENgj EG+nZXkVgBqLfiwFguo718ACEh9pkIZe8Zvq1AOSjju38h2pZp66Q+rpoeE3hwof812G m9RLOmxd/EiIA6qAtEoDUfmHFuT+JkG4pW1S9k126erm+ua4cQGhB1Jba3ChWWVSDi50 6TBQwxulIZPop0QCkwKWo2M0wyDcoyFdg6Y6rfKZarQMVGuj2UdQlX2V+oSec+o+43oS 4Ocw== X-Gm-Message-State: AKwxyteksKfhDLT3R/vPsVqIK6+0u9KPcDz3M31aRdR+fDqCLaTtADsz HUI04YWrX6HIj1Kfgk/BzvUppLYqNOQ= X-Google-Smtp-Source: ACJfBoul28bMBxJPbyRXaitl7wQDcB8QEqOEYJcStnkKLX7+y26PnTU+Xk8SkHbSuR6CA0bQ0xEVew== X-Received: by 2002:a17:902:748b:: with SMTP id h11-v6mr969379pll.259.1516337691732; Thu, 18 Jan 2018 20:54:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:27 -0800 Message-Id: <20180119045438.28582-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 05/16] target/arm: Change the type of vfp.regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" All direct users of this field want an integral value. Drop all of the extra casting between uint64_t and float64. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 2 +- target/arm/arch_dump.c | 4 ++-- target/arm/helper.c | 20 ++++++++++---------- target/arm/machine.c | 2 +- target/arm/translate-a64.c | 8 ++++---- target/arm/translate.c | 2 +- 6 files changed, 19 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 96316700dd..76ab7953a6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -492,7 +492,7 @@ typedef struct CPUARMState { * the two execution states, and means we do not need to explicitly * map these registers when changing states. */ - float64 regs[64]; + uint64_t regs[64]; =20 uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 9e5b2fb31c..0c43e0eef8 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -100,7 +100,7 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFun= ction f, aarch64_note_init(¬e, s, "CORE", 5, NT_PRFPREG, sizeof(note.vfp)); =20 for (i =3D 0; i < 64; ++i) { - note.vfp.vregs[i] =3D cpu_to_dump64(s, float64_val(env->vfp.regs[i= ])); + note.vfp.vregs[i] =3D cpu_to_dump64(s, env->vfp.regs[i]); } =20 if (s->dump_info.d_endian =3D=3D ELFDATA2MSB) { @@ -229,7 +229,7 @@ static int arm_write_elf32_vfp(WriteCoreDumpFunction f,= CPUARMState *env, arm_note_init(¬e, s, "LINUX", 6, NT_ARM_VFP, sizeof(note.vfp)); =20 for (i =3D 0; i < 32; ++i) { - note.vfp.vregs[i] =3D cpu_to_dump64(s, float64_val(env->vfp.regs[i= ])); + note.vfp.vregs[i] =3D cpu_to_dump64(s, env->vfp.regs[i]); } =20 note.vfp.fpscr =3D cpu_to_dump32(s, vfp_get_fpscr(env)); diff --git a/target/arm/helper.c b/target/arm/helper.c index c83c901a86..8fda797582 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -64,15 +64,15 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *b= uf, int reg) /* VFP data registers are always little-endian. */ nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - stfq_le_p(buf, env->vfp.regs[reg]); + stq_le_p(buf, env->vfp.regs[reg]); return 8; } if (arm_feature(env, ARM_FEATURE_NEON)) { /* Aliases for Q regs. */ nregs +=3D 16; if (reg < nregs) { - stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); - stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); + stq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); + stq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); return 16; } } @@ -90,14 +90,14 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *b= uf, int reg) =20 nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - env->vfp.regs[reg] =3D ldfq_le_p(buf); + env->vfp.regs[reg] =3D ldq_le_p(buf); return 8; } if (arm_feature(env, ARM_FEATURE_NEON)) { nregs +=3D 16; if (reg < nregs) { - env->vfp.regs[(reg - 32) * 2] =3D ldfq_le_p(buf); - env->vfp.regs[(reg - 32) * 2 + 1] =3D ldfq_le_p(buf + 8); + env->vfp.regs[(reg - 32) * 2] =3D ldq_le_p(buf); + env->vfp.regs[(reg - 32) * 2 + 1] =3D ldq_le_p(buf + 8); return 16; } } @@ -114,8 +114,8 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, ui= nt8_t *buf, int reg) switch (reg) { case 0 ... 31: /* 128 bit FP register */ - stfq_le_p(buf, env->vfp.regs[reg * 2]); - stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); + stq_le_p(buf, env->vfp.regs[reg * 2]); + stq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); return 16; case 32: /* FPSR */ @@ -135,8 +135,8 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, ui= nt8_t *buf, int reg) switch (reg) { case 0 ... 31: /* 128 bit FP register */ - env->vfp.regs[reg * 2] =3D ldfq_le_p(buf); - env->vfp.regs[reg * 2 + 1] =3D ldfq_le_p(buf + 8); + env->vfp.regs[reg * 2] =3D ldq_le_p(buf); + env->vfp.regs[reg * 2 + 1] =3D ldq_le_p(buf + 8); return 16; case 32: /* FPSR */ diff --git a/target/arm/machine.c b/target/arm/machine.c index 176274629c..a85c2430d3 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -50,7 +50,7 @@ static const VMStateDescription vmstate_vfp =3D { .minimum_version_id =3D 3, .needed =3D vfp_needed, .fields =3D (VMStateField[]) { - VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64), + VMSTATE_UINT64_ARRAY(env.vfp.regs, ARMCPU, 64), /* The xregs array is a little awkward because element 1 (FPSCR) * requires a specific accessor, so we have to split it up in * the vmstate: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6d9b3af64c..c14fb4185c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -165,12 +165,12 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, if (flags & CPU_DUMP_FPU) { int numvfpregs =3D 32; for (i =3D 0; i < numvfpregs; i +=3D 2) { - uint64_t vlo =3D float64_val(env->vfp.regs[i * 2]); - uint64_t vhi =3D float64_val(env->vfp.regs[(i * 2) + 1]); + uint64_t vlo =3D env->vfp.regs[i * 2]; + uint64_t vhi =3D env->vfp.regs[(i * 2) + 1]; cpu_fprintf(f, "q%02d=3D%016" PRIx64 ":%016" PRIx64 " ", i, vhi, vlo); - vlo =3D float64_val(env->vfp.regs[(i + 1) * 2]); - vhi =3D float64_val(env->vfp.regs[((i + 1) * 2) + 1]); + vlo =3D env->vfp.regs[(i + 1) * 2]; + vhi =3D env->vfp.regs[((i + 1) * 2) + 1]; cpu_fprintf(f, "q%02d=3D%016" PRIx64 ":%016" PRIx64 "\n", i + 1, vhi, vlo); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 852d2a75b1..cfe49bf579 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12572,7 +12572,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, numvfpregs +=3D 16; } for (i =3D 0; i < numvfpregs; i++) { - uint64_t v =3D float64_val(env->vfp.regs[i]); + uint64_t v =3D env->vfp.regs[i]; cpu_fprintf(f, "s%02d=3D%08x s%02d=3D%08x d%02d=3D%016" PRIx64= "\n", i * 2, (uint32_t)v, i * 2 + 1, (uint32_t)(v >> 32), --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 06/16] target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Helpers that return a pointer into env->vfp.regs so that we isolate the logic of how to index the regs array for different cpu modes. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 27 +++++++++++++++++++++++++++ linux-user/signal.c | 22 ++++++++++++---------- target/arm/arch_dump.c | 8 +++++--- target/arm/helper-a64.c | 5 +++-- target/arm/helper.c | 32 ++++++++++++++++++++------------ target/arm/kvm32.c | 4 ++-- target/arm/kvm64.c | 31 ++++++++++--------------------- target/arm/translate-a64.c | 25 ++++++++----------------- target/arm/translate.c | 16 +++++++++------- 9 files changed, 96 insertions(+), 74 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 76ab7953a6..7d396606f3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2885,4 +2885,31 @@ static inline void *arm_get_el_change_hook_opaque(AR= MCPU *cpu) return cpu->el_change_hook_opaque; } =20 +/** + * aa32_vfp_dreg: + * Return a pointer to the Dn register within env in 32-bit mode. + */ +static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) +{ + return &env->vfp.regs[regno]; +} + +/** + * aa32_vfp_qreg: + * Return a pointer to the Qn register within env in 32-bit mode. + */ +static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) +{ + return &env->vfp.regs[2 * regno]; +} + +/** + * aa64_vfp_qreg: + * Return a pointer to the Qn register within env in 64-bit mode. + */ +static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) +{ + return &env->vfp.regs[2 * regno]; +} + #endif diff --git a/linux-user/signal.c b/linux-user/signal.c index f85f0dd780..5321f9e795 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -1487,12 +1487,13 @@ static int target_setup_sigframe(struct target_rt_s= igframe *sf, } =20 for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); #ifdef TARGET_WORDS_BIGENDIAN - __put_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2 + 1]); - __put_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2]); + __put_user(q[0], &aux->fpsimd.vregs[i * 2 + 1]); + __put_user(q[1], &aux->fpsimd.vregs[i * 2]); #else - __put_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2]); - __put_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2 + 1]= ); + __put_user(q[0], &aux->fpsimd.vregs[i * 2]); + __put_user(q[1], &aux->fpsimd.vregs[i * 2 + 1]); #endif } __put_user(vfp_get_fpsr(env), &aux->fpsimd.fpsr); @@ -1539,12 +1540,13 @@ static int target_restore_sigframe(CPUARMState *env, } =20 for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); #ifdef TARGET_WORDS_BIGENDIAN - __get_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2 + 1]); - __get_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2]); + __get_user(q[0], &aux->fpsimd.vregs[i * 2 + 1]); + __get_user(q[1], &aux->fpsimd.vregs[i * 2]); #else - __get_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2]); - __get_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2 + 1]= ); + __get_user(q[0], &aux->fpsimd.vregs[i * 2]); + __get_user(q[1], &aux->fpsimd.vregs[i * 2 + 1]); #endif } __get_user(fpsr, &aux->fpsimd.fpsr); @@ -1903,7 +1905,7 @@ static abi_ulong *setup_sigframe_v2_vfp(abi_ulong *re= gspace, CPUARMState *env) __put_user(TARGET_VFP_MAGIC, &vfpframe->magic); __put_user(sizeof(*vfpframe), &vfpframe->size); for (i =3D 0; i < 32; i++) { - __put_user(float64_val(env->vfp.regs[i]), &vfpframe->ufp.fpregs[i]= ); + __put_user(*aa32_vfp_dreg(env, i), &vfpframe->ufp.fpregs[i]); } __put_user(vfp_get_fpscr(env), &vfpframe->ufp.fpscr); __put_user(env->vfp.xregs[ARM_VFP_FPEXC], &vfpframe->ufp_exc.fpexc); @@ -2210,7 +2212,7 @@ static abi_ulong *restore_sigframe_v2_vfp(CPUARMState= *env, abi_ulong *regspace) return 0; } for (i =3D 0; i < 32; i++) { - __get_user(float64_val(env->vfp.regs[i]), &vfpframe->ufp.fpregs[i]= ); + __get_user(*aa32_vfp_dreg(env, i), &vfpframe->ufp.fpregs[i]); } __get_user(fpscr, &vfpframe->ufp.fpscr); vfp_set_fpscr(env, fpscr); diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 0c43e0eef8..26a2c09868 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -99,8 +99,10 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunc= tion f, =20 aarch64_note_init(¬e, s, "CORE", 5, NT_PRFPREG, sizeof(note.vfp)); =20 - for (i =3D 0; i < 64; ++i) { - note.vfp.vregs[i] =3D cpu_to_dump64(s, env->vfp.regs[i]); + for (i =3D 0; i < 32; ++i) { + uint64_t *q =3D aa64_vfp_qreg(env, i); + note.vfp.vregs[2*i + 0] =3D cpu_to_dump64(s, q[0]); + note.vfp.vregs[2*i + 1] =3D cpu_to_dump64(s, q[1]); } =20 if (s->dump_info.d_endian =3D=3D ELFDATA2MSB) { @@ -229,7 +231,7 @@ static int arm_write_elf32_vfp(WriteCoreDumpFunction f,= CPUARMState *env, arm_note_init(¬e, s, "LINUX", 6, NT_ARM_VFP, sizeof(note.vfp)); =20 for (i =3D 0; i < 32; ++i) { - note.vfp.vregs[i] =3D cpu_to_dump64(s, env->vfp.regs[i]); + note.vfp.vregs[i] =3D cpu_to_dump64(s, *aa32_vfp_dreg(env, i)); } =20 note.vfp.fpscr =3D cpu_to_dump32(s, vfp_get_fpscr(env)); diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 3e00a9ead1..06fd321fae 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -153,13 +153,14 @@ uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t = result, uint64_t indices, if (index < 16 * numregs) { /* Convert index (a byte offset into the virtual table * which is a series of 128-bit vectors concatenated) - * into the correct vfp.regs[] element plus a bit offset + * into the correct register element plus a bit offset * into that element, bearing in mind that the table * can wrap around from V31 to V0. */ int elt =3D (rn * 2 + (index >> 3)) % 64; int bitidx =3D (index & 7) * 8; - uint64_t val =3D extract64(env->vfp.regs[elt], bitidx, 8); + uint64_t *q =3D aa64_vfp_qreg(env, elt >> 1); + uint64_t val =3D extract64(q[elt & 1], bitidx, 8); =20 result =3D deposit64(result, shift, 8, val); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 8fda797582..6705903301 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -64,15 +64,16 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *b= uf, int reg) /* VFP data registers are always little-endian. */ nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - stq_le_p(buf, env->vfp.regs[reg]); + stq_le_p(buf, *aa32_vfp_dreg(env, reg)); return 8; } if (arm_feature(env, ARM_FEATURE_NEON)) { /* Aliases for Q regs. */ nregs +=3D 16; if (reg < nregs) { - stq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); - stq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); + uint64_t *q =3D aa32_vfp_qreg(env, reg - 32); + stq_le_p(buf, q[0]); + stq_le_p(buf + 8, q[1]); return 16; } } @@ -90,14 +91,15 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *b= uf, int reg) =20 nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - env->vfp.regs[reg] =3D ldq_le_p(buf); + *aa32_vfp_dreg(env, reg) =3D ldq_le_p(buf); return 8; } if (arm_feature(env, ARM_FEATURE_NEON)) { nregs +=3D 16; if (reg < nregs) { - env->vfp.regs[(reg - 32) * 2] =3D ldq_le_p(buf); - env->vfp.regs[(reg - 32) * 2 + 1] =3D ldq_le_p(buf + 8); + uint64_t *q =3D aa32_vfp_qreg(env, reg - 32); + q[0] =3D ldq_le_p(buf); + q[1] =3D ldq_le_p(buf + 8); return 16; } } @@ -114,9 +116,12 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, u= int8_t *buf, int reg) switch (reg) { case 0 ... 31: /* 128 bit FP register */ - stq_le_p(buf, env->vfp.regs[reg * 2]); - stq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); - return 16; + { + uint64_t *q =3D aa64_vfp_qreg(env, reg); + stq_le_p(buf, q[0]); + stq_le_p(buf + 8, q[1]); + return 16; + } case 32: /* FPSR */ stl_p(buf, vfp_get_fpsr(env)); @@ -135,9 +140,12 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, u= int8_t *buf, int reg) switch (reg) { case 0 ... 31: /* 128 bit FP register */ - env->vfp.regs[reg * 2] =3D ldq_le_p(buf); - env->vfp.regs[reg * 2 + 1] =3D ldq_le_p(buf + 8); - return 16; + { + uint64_t *q =3D aa64_vfp_qreg(env, reg); + q[0] =3D ldq_le_p(buf); + q[1] =3D ldq_le_p(buf + 8); + return 16; + } case 32: /* FPSR */ vfp_set_fpsr(env, ldl_p(buf)); diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f925a21481..f77c9c494b 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -358,7 +358,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) /* VFP registers */ r.id =3D KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; for (i =3D 0; i < 32; i++) { - r.addr =3D (uintptr_t)(&env->vfp.regs[i]); + r.addr =3D (uintptr_t)aa32_vfp_dreg(env, i); ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); if (ret) { return ret; @@ -445,7 +445,7 @@ int kvm_arch_get_registers(CPUState *cs) /* VFP registers */ r.id =3D KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; for (i =3D 0; i < 32; i++) { - r.addr =3D (uintptr_t)(&env->vfp.regs[i]); + r.addr =3D (uintptr_t)aa32_vfp_dreg(env, i); ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); if (ret) { return ret; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6554c30007..ac728494a4 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -696,21 +696,16 @@ int kvm_arch_put_registers(CPUState *cs, int level) } } =20 - /* Advanced SIMD and FP registers - * We map Qn =3D regs[2n+1]:regs[2n] - */ + /* Advanced SIMD and FP registers. */ for (i =3D 0; i < 32; i++) { - int rd =3D i << 1; - uint64_t fp_val[2]; + uint64_t *q =3D aa64_vfp_qreg(env, i); #ifdef HOST_WORDS_BIGENDIAN - fp_val[0] =3D env->vfp.regs[rd + 1]; - fp_val[1] =3D env->vfp.regs[rd]; + uint64_t fp_val[2] =3D { q[1], q[0] }; + reg.addr =3D (uintptr_t)fp_val; #else - fp_val[1] =3D env->vfp.regs[rd + 1]; - fp_val[0] =3D env->vfp.regs[rd]; + reg.addr =3D (uintptr_t)q; #endif reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - reg.addr =3D (uintptr_t)(&fp_val); ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); if (ret) { return ret; @@ -837,24 +832,18 @@ int kvm_arch_get_registers(CPUState *cs) env->spsr =3D env->banked_spsr[i]; } =20 - /* Advanced SIMD and FP registers - * We map Qn =3D regs[2n+1]:regs[2n] - */ + /* Advanced SIMD and FP registers */ for (i =3D 0; i < 32; i++) { - uint64_t fp_val[2]; + uint64_t *q =3D aa64_vfp_qreg(env, i); reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - reg.addr =3D (uintptr_t)(&fp_val); + reg.addr =3D (uintptr_t)q; ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); if (ret) { return ret; } else { - int rd =3D i << 1; #ifdef HOST_WORDS_BIGENDIAN - env->vfp.regs[rd + 1] =3D fp_val[0]; - env->vfp.regs[rd] =3D fp_val[1]; -#else - env->vfp.regs[rd + 1] =3D fp_val[1]; - env->vfp.regs[rd] =3D fp_val[0]; + uint64_t t; + t =3D q[0], q[0] =3D q[1], q[1] =3D t; #endif } } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c14fb4185c..eed64c73e5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -164,15 +164,12 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, =20 if (flags & CPU_DUMP_FPU) { int numvfpregs =3D 32; - for (i =3D 0; i < numvfpregs; i +=3D 2) { - uint64_t vlo =3D env->vfp.regs[i * 2]; - uint64_t vhi =3D env->vfp.regs[(i * 2) + 1]; - cpu_fprintf(f, "q%02d=3D%016" PRIx64 ":%016" PRIx64 " ", - i, vhi, vlo); - vlo =3D env->vfp.regs[(i + 1) * 2]; - vhi =3D env->vfp.regs[((i + 1) * 2) + 1]; - cpu_fprintf(f, "q%02d=3D%016" PRIx64 ":%016" PRIx64 "\n", - i + 1, vhi, vlo); + for (i =3D 0; i < numvfpregs; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); + uint64_t vlo =3D q[0]; + uint64_t vhi =3D q[1]; + cpu_fprintf(f, "q%02d=3D%016" PRIx64 ":%016" PRIx64 "%c", + i, vhi, vlo, (i & 1 ? '\n' : ' ')); } cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", vfp_get_fpcr(env), vfp_get_fpsr(env)); @@ -558,19 +555,13 @@ static TCGv_ptr vec_full_reg_ptr(DisasContext *s, int= regno) */ static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size) { - int offs =3D offsetof(CPUARMState, vfp.regs[regno * 2]); -#ifdef HOST_WORDS_BIGENDIAN - offs +=3D (8 - (1 << size)); -#endif - assert_fp_access_checked(s); - return offs; + return vec_reg_offset(s, regno, 0, size); } =20 /* Offset of the high half of the 128 bit vector Qn */ static inline int fp_reg_hi_offset(DisasContext *s, int regno) { - assert_fp_access_checked(s); - return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]); + return vec_reg_offset(s, regno, 1, MO_64); } =20 /* Convenience accessors for reading and writing single and double diff --git a/target/arm/translate.c b/target/arm/translate.c index cfe49bf579..55826b7e5a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1515,14 +1515,16 @@ static inline void gen_vfp_st(DisasContext *s, int = dp, TCGv_i32 addr) static inline long vfp_reg_offset (int dp, int reg) { - if (dp) + if (dp) { return offsetof(CPUARMState, vfp.regs[reg]); - else if (reg & 1) { - return offsetof(CPUARMState, vfp.regs[reg >> 1]) - + offsetof(CPU_DoubleU, l.upper); } else { - return offsetof(CPUARMState, vfp.regs[reg >> 1]) - + offsetof(CPU_DoubleU, l.lower); + long ofs =3D offsetof(CPUARMState, vfp.regs[reg >> 1]); + if (reg & 1) { + ofs +=3D offsetof(CPU_DoubleU, l.upper); + } else { + ofs +=3D offsetof(CPU_DoubleU, l.lower); + } + return ofs; } } =20 @@ -12572,7 +12574,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, numvfpregs +=3D 16; } for (i =3D 0; i < numvfpregs; i++) { - uint64_t v =3D env->vfp.regs[i]; + uint64_t v =3D *aa32_vfp_dreg(env, i); cpu_fprintf(f, "s%02d=3D%08x s%02d=3D%08x d%02d=3D%016" PRIx64= "\n", i * 2, (uint32_t)v, i * 2 + 1, (uint32_t)(v >> 32), --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516337820801135.26002581708462; Thu, 18 Jan 2018 20:57:00 -0800 (PST) Received: from localhost ([::1]:52266 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOjb-0003aU-VO for importer@patchew.org; Thu, 18 Jan 2018 23:57:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58664) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOhe-0002Dn-FJ for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:54:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecOhc-0000C1-KU for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:54:58 -0500 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:45122) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecOhc-0000Aw-Ea for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:54:56 -0500 Received: by mail-pf0-x242.google.com with SMTP id a88so515686pfe.12 for ; Thu, 18 Jan 2018 20:54:56 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.54.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:54:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x9PA8yjdEe9Kvb1NLwDZCFpm0U0h6iWdOQkgNTDHrIg=; b=OMy+5GPMpcPjniyJX3YLuejtVarh4MjwfU26uXYdyvh1SKSmRwqviejT6zn88dI8vj eTBGzFyzkYiD7j8zsYwWDLj08E6U3lNvUBAz/XXfzQw2yEn7OAH3+6ank2fNg34PAxzl JhHmFMdNRD/sGwyriSPUqnmhioqOSuyDIyk1Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x9PA8yjdEe9Kvb1NLwDZCFpm0U0h6iWdOQkgNTDHrIg=; b=gr6DjnkG3HGXqTxPZYhHDQOMkTH3a4FtzSs4LLJcLpVfg44n9cVgPtH7xfrXFoU44d gqml25/Er22V9hGiTQa2UZQR6+kj8/S6dUbUOWsxt98Cz4tM7POQ3kwSD5Qw5j7+exZf XzLxAyfWaaRGYpW8AX5Ar7nSshmLUc7Dw8k8BIgbhBKaeWSAxPo1Calby5L8ETDZ6VAu w3RkgASzERWF3ZebaqFeDFnexeeo0VaAWPiLpurTzHDmxavRxx6rpmzWzceGnFxOXgBl 45I3iLdjGf1WTD/PAYTtn5CH9rLKpR2JNMi+rDbXLLpGuxD0K2tIXsqlJeIZeE25BTDa h19w== X-Gm-Message-State: AKwxytfYt2/WR62F2frpPhHjaAKpLI5M5+04F81mFTRSv09QKbqkaFGj kBoxXkKt0CqtXSOFFgAb69fScQ8OGk0= X-Google-Smtp-Source: ACJfBossT0WRsHBZQaN7NepecfWIqiFynZo7IGKV3IhcBWCKAvwECON88ZzuqdXXMFN5qRDHKWIhUQ== X-Received: by 10.101.65.205 with SMTP id b13mr5856533pgq.280.1516337694962; Thu, 18 Jan 2018 20:54:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:29 -0800 Message-Id: <20180119045438.28582-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v2 07/16] vmstate: Add VMSTATE_UINT64_SUB_ARRAY X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 At the same time, move VMSTATE_UINT32_SUB_ARRAY beside the other UINT32 definitions. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/migration/vmstate.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 88b55df5ae..8c3889433c 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -905,6 +905,9 @@ extern const VMStateInfo vmstate_info_qtailq; #define VMSTATE_UINT32_ARRAY(_f, _s, _n) \ VMSTATE_UINT32_ARRAY_V(_f, _s, _n, 0) =20 +#define VMSTATE_UINT32_SUB_ARRAY(_f, _s, _start, _num) \ + VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_uint32, uint32= _t) + #define VMSTATE_UINT32_2DARRAY(_f, _s, _n1, _n2) \ VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, 0) =20 @@ -914,6 +917,9 @@ extern const VMStateInfo vmstate_info_qtailq; #define VMSTATE_UINT64_ARRAY(_f, _s, _n) \ VMSTATE_UINT64_ARRAY_V(_f, _s, _n, 0) =20 +#define VMSTATE_UINT64_SUB_ARRAY(_f, _s, _start, _num) \ + VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_uint64, uint64= _t) + #define VMSTATE_UINT64_2DARRAY(_f, _s, _n1, _n2) \ VMSTATE_UINT64_2DARRAY_V(_f, _s, _n1, _n2, 0) =20 @@ -932,9 +938,6 @@ extern const VMStateInfo vmstate_info_qtailq; #define VMSTATE_INT32_ARRAY(_f, _s, _n) \ VMSTATE_INT32_ARRAY_V(_f, _s, _n, 0) =20 -#define VMSTATE_UINT32_SUB_ARRAY(_f, _s, _start, _num) \ - VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_uint32, uint32= _t) - #define VMSTATE_INT64_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_int64, int64_t) =20 --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516338360826711.1972139145659; Thu, 18 Jan 2018 21:06:00 -0800 (PST) Received: from localhost ([::1]:52466 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOsJ-0003CK-To for importer@patchew.org; Fri, 19 Jan 2018 00:06:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58684) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOhf-0002Ej-JJ for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecOhd-0000Er-UR for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:54:59 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:43301) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecOhd-0000DD-Lz for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:54:57 -0500 Received: by mail-pg0-x244.google.com with SMTP id n17so540335pgf.10 for ; Thu, 18 Jan 2018 20:54:57 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 08/16] target/arm: Expand vector registers for SVE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Change vfp.regs as a uint64_t to vfp.zregs as an ARMVectorReg. The previous patches have made the change in representation relatively painless. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 57 ++++++++++++++++++++++++++++++------------= ---- target/arm/machine.c | 35 +++++++++++++++++++++++++++- target/arm/translate-a64.c | 8 +++---- target/arm/translate.c | 7 +++--- 4 files changed, 79 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7d396606f3..57d805b5d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -153,6 +153,40 @@ typedef struct { uint32_t base_mask; } TCR; =20 +/* Define a maximum sized vector register. + * For 32-bit, this is a 128-bit NEON/AdvSIMD register. + * For 64-bit, this is a 2048-bit SVE register. + * + * Note that the mapping between S, D, and Q views of the register bank + * differs between AArch64 and AArch32. + * In AArch32: + * Qn =3D regs[n].d[1]:regs[n].d[0] + * Dn =3D regs[n / 2].d[n & 1] + * Sn =3D regs[n / 4].d[n % 4 / 2], + * bits 31..0 for even n, and bits 63..32 for odd n + * (and regs[16] to regs[31] are inaccessible) + * In AArch64: + * Zn =3D regs[n].d[*] + * Qn =3D regs[n].d[1]:regs[n].d[0] + * Dn =3D regs[n].d[0] + * Sn =3D regs[n].d[0] bits 31..0 + * + * This corresponds to the architecturally defined mapping between + * the two execution states, and means we do not need to explicitly + * map these registers when changing states. + */ + +#ifdef TARGET_AARCH64 +# define ARM_MAX_VQ 16 +#else +# define ARM_MAX_VQ 1 +#endif + +typedef struct ARMVectorReg { + uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); +} ARMVectorReg; + + typedef struct CPUARMState { /* Regs for current mode. */ uint32_t regs[16]; @@ -477,22 +511,7 @@ typedef struct CPUARMState { =20 /* VFP coprocessor state. */ struct { - /* VFP/Neon register state. Note that the mapping between S, D and= Q - * views of the register bank differs between AArch64 and AArch32: - * In AArch32: - * Qn =3D regs[2n+1]:regs[2n] - * Dn =3D regs[n] - * Sn =3D regs[n/2] bits 31..0 for even n, and bits 63..32 for od= d n - * (and regs[32] to regs[63] are inaccessible) - * In AArch64: - * Qn =3D regs[2n+1]:regs[2n] - * Dn =3D regs[2n] - * Sn =3D regs[2n] bits 31..0 - * This corresponds to the architecturally defined mapping between - * the two execution states, and means we do not need to explicitly - * map these registers when changing states. - */ - uint64_t regs[64]; + ARMVectorReg zregs[32]; =20 uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ @@ -2891,7 +2910,7 @@ static inline void *arm_get_el_change_hook_opaque(ARM= CPU *cpu) */ static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) { - return &env->vfp.regs[regno]; + return &env->vfp.zregs[regno >> 1].d[regno & 1]; } =20 /** @@ -2900,7 +2919,7 @@ static inline uint64_t *aa32_vfp_dreg(CPUARMState *en= v, unsigned regno) */ static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) { - return &env->vfp.regs[2 * regno]; + return &env->vfp.zregs[regno].d[0]; } =20 /** @@ -2909,7 +2928,7 @@ static inline uint64_t *aa32_vfp_qreg(CPUARMState *en= v, unsigned regno) */ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) { - return &env->vfp.regs[2 * regno]; + return &env->vfp.zregs[regno].d[0]; } =20 #endif diff --git a/target/arm/machine.c b/target/arm/machine.c index a85c2430d3..cb0e1c92bb 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -50,7 +50,40 @@ static const VMStateDescription vmstate_vfp =3D { .minimum_version_id =3D 3, .needed =3D vfp_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT64_ARRAY(env.vfp.regs, ARMCPU, 64), + /* For compatibility, store Qn out of Zn here. */ + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[10].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[11].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[12].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[13].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[14].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[15].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[16].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[17].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[18].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[19].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[20].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[21].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[22].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[23].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[24].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[25].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[26].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[27].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[28].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[29].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[30].d, ARMCPU, 0, 2), + VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[31].d, ARMCPU, 0, 2), + /* The xregs array is a little awkward because element 1 (FPSCR) * requires a specific accessor, so we have to split it up in * the vmstate: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index eed64c73e5..10eef870fe 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -517,8 +517,8 @@ static inline int vec_reg_offset(DisasContext *s, int r= egno, { int offs =3D 0; #ifdef HOST_WORDS_BIGENDIAN - /* This is complicated slightly because vfp.regs[2n] is - * still the low half and vfp.regs[2n+1] the high half + /* This is complicated slightly because vfp.zregs[n].d[0] is + * still the low half and vfp.zregs[n].d[1] the high half * of the 128 bit vector, even on big endian systems. * Calculate the offset assuming a fully bigendian 128 bits, * then XOR to account for the order of the two 64 bit halves. @@ -528,7 +528,7 @@ static inline int vec_reg_offset(DisasContext *s, int r= egno, #else offs +=3D element * (1 << size); #endif - offs +=3D offsetof(CPUARMState, vfp.regs[regno * 2]); + offs +=3D offsetof(CPUARMState, vfp.zregs[regno]); assert_fp_access_checked(s); return offs; } @@ -537,7 +537,7 @@ static inline int vec_reg_offset(DisasContext *s, int r= egno, static inline int vec_full_reg_offset(DisasContext *s, int regno) { assert_fp_access_checked(s); - return offsetof(CPUARMState, vfp.regs[regno * 2]); + return offsetof(CPUARMState, vfp.zregs[regno]); } =20 /* Return a newly allocated pointer to the vector register. */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 55826b7e5a..a8c13d3758 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1512,13 +1512,12 @@ static inline void gen_vfp_st(DisasContext *s, int = dp, TCGv_i32 addr) } } =20 -static inline long -vfp_reg_offset (int dp, int reg) +static inline long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { - return offsetof(CPUARMState, vfp.regs[reg]); + return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); } else { - long ofs =3D offsetof(CPUARMState, vfp.regs[reg >> 1]); + long ofs =3D offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1= ) & 1]); if (reg & 1) { ofs +=3D offsetof(CPU_DoubleU, l.upper); } else { --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.54.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:54:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0CxMIlWhojUfXTrDvwY6qWshYlW8bQTO3vjIfqHU3hQ=; b=hxvDCnrmhEHqkF6sTpxw3PrCOCF+233jRd+8nIxoo9rliqFhh5d5kCZfhcaLs1jPAV 4vWcko+9O9EJbtGrzwh4PpAyO/rGUa3jFXR4MO/rTPp1HBYe1tjYdIkxIMoMUX/E66W+ VAafrj6CCC09YbojYJIoSeEfA+q0gkhJRg38M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0CxMIlWhojUfXTrDvwY6qWshYlW8bQTO3vjIfqHU3hQ=; b=diuoYsNHEHzPtxAd1VKyBz8EZEN449L5lsY1evkAE3DadbJ0KNKWBA3Nou9g9r1nNo BfAaFshw+hA9RPgIEWA4IuJ09nHdqAaHlJGnLDGIU0bAztKwp+tNU8sV94GobWBoYLy7 IvBH6KH9XpKtrXbTVt6vQ/GdK2f7bE3FFTqv5BdjHfSCTJOQM+JNzPuNtuTsRV8daomd 98aCEIIenc/jzdrLLAAAS83vvJaQhUijXtbXiIBMUeGIe5YS4yWW0MjLY8d4uDq1dvoI EkEX5cOirHi40P1BCszla02J7qz1PrYvkyabFWQF586qohtgAac+XYPetKXg3HXUd1r9 ID0A== X-Gm-Message-State: AKGB3mJGmt4gyUXLugJqDJfCT0w4kL59aqh6UPFHHfpr8fl1N59AtsdV C3QAPJjUN5Uy5hAYtf5s3cLW5BaHirM= X-Google-Smtp-Source: ACJfBovXhNpNhyIsx99dyG+ahDh+6PGNlZum2QB++BZqzwiQJcGjNUb0yrDhiMwgPyAzwbzYb1U+Jg== X-Received: by 10.101.78.134 with SMTP id b6mr37929917pgs.381.1516337697768; Thu, 18 Jan 2018 20:54:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:31 -0800 Message-Id: <20180119045438.28582-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 09/16] target/arm: Add predicate registers for SVE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 57d805b5d8..132da359b5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -186,6 +186,15 @@ typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; =20 +/* In AArch32 mode, predicate registers do not exist at all. */ +typedef struct ARMPredicateReg { +#ifdef TARGET_AARCH64 + uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); +#else + uint64_t p[0]; +#endif +} ARMPredicateReg; + =20 typedef struct CPUARMState { /* Regs for current mode. */ @@ -513,6 +522,9 @@ typedef struct CPUARMState { struct { ARMVectorReg zregs[32]; =20 + /* Store FFR as pregs[16] to make it easier to treat as any other.= */ + ARMPredicateReg pregs[17]; + uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ int vec_len; --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516338519798393.25763402840835; Thu, 18 Jan 2018 21:08:39 -0800 (PST) Received: from localhost ([::1]:52621 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOun-0005bK-Vy for importer@patchew.org; Fri, 19 Jan 2018 00:08:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58713) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOhh-0002GJ-8P for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecOhg-0000Lt-GP for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:01 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:42705) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecOhg-0000Jz-AS for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:00 -0500 Received: by mail-pg0-x244.google.com with SMTP id q67so544133pga.9 for ; Thu, 18 Jan 2018 20:55:00 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.54.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:54:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KlaxOBSHgQAc7vreH1EYmk6NLDntdGTsLksVrRYUrEs=; b=WfQsCL8Jnx+MUEBRToE0EYe+x0nXM/uXuFPqxTOEkcdprKfdlDr/vOyh8357eoQTCx 3kZyKAlcE+lOizntMcSvApFu6mxypIYj1GRJJnUEmK3CgH1Fxv/O+tenFSsDlpKEP4tH yxry4mVYcY68VA34tH7u01LgxtqWqihO/ncUM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KlaxOBSHgQAc7vreH1EYmk6NLDntdGTsLksVrRYUrEs=; b=HECYn0TUi0wSWlAVGRk8AFJJU6g6a+Bnp+2qEERd9PpN2efLGpAEmEYD9KLwvjARek INSymez01RYyeEfNblMPy0PTqr4XQXFBJMeo+E4k6BKZgX8xSGwo96QkkZvP7QfV20GH G57H8a6tFzmcz1nbCfsgC7UwjIzYGCHTOsY5JqEIffQTeqGRjzlkThJnNBbIh6KlNInM dNgDkktKiyZknEBCkwyyEWrTBnmroV4CH+/XkPcxXd/Xs8OLHdAucG/NeLF6sQdZOmIm KDa3lNRBp5MAZ6gZ9IiEmpdpB7qGeFnMr45CZgcXO3YqWaMh2p1Tjr4EebC8XJnpvVxM IM0Q== X-Gm-Message-State: AKGB3mI2C19O7e/x9AIdR5AfJ8hHkQWfe5p+I0a8X83kKM9+kepNMNfn KW1iaJz7nLmLdNYnaDMAjWv8rrNXTcs= X-Google-Smtp-Source: ACJfBouYXhkVVRBrVwwFy56gtXVkz6hdoLBLG2znELsxJk4ufGQ/V2paXSQIMWAXlqdUa6baItLD2g== X-Received: by 10.99.184.17 with SMTP id p17mr39680938pge.357.1516337699063; Thu, 18 Jan 2018 20:54:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:32 -0800 Message-Id: <20180119045438.28582-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 10/16] target/arm: Add ARM_FEATURE_SVE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Not enabled anywhere so far. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 132da359b5..0a923e42d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1371,6 +1371,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ + ARM_FEATURE_SVE, /* has Scalable Vector Extension */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151633881113218.70494902842688; Thu, 18 Jan 2018 21:13:31 -0800 (PST) Received: from localhost ([::1]:52960 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOzF-0001Le-Cw for importer@patchew.org; Fri, 19 Jan 2018 00:13:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58738) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOhi-0002Hl-Pv for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecOhh-0000Oa-RM for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:02 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:42705) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecOhh-0000NC-Ku for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:01 -0500 Received: by mail-pg0-x243.google.com with SMTP id q67so544220pga.9 for ; Thu, 18 Jan 2018 20:55:01 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.54.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:54:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rtUJek3aPDGG5LW/JtqEYY8tEezLcf4E59P/pioBFKI=; b=CXz/b4PoW5wRvfI94OcgvLhJifAGlbJ/fiFUcIuD/J0Y5CDU+Gbwl/HchkSM5DolWE zaX/lBzxGH3B0+WAUlZU1zR0SsZgB/k7EKsA+f2RE3Zi0rH2RlKGNdjnww4WpCNyrFd6 vkXKupKJWtT3cP26KjZviCg7RS/QGV0r1ymIU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rtUJek3aPDGG5LW/JtqEYY8tEezLcf4E59P/pioBFKI=; b=dD5O2P4u75Qq7nHWpXahDmZV6L8XWrcYJgrOQdcub1BuGPVmU6sHvHxLny2i5FOsQo Lwhcsy4POurRZRwyTM47/2uyW+Qwf6vZyzvnxERQKCMz7VHPzgD4uMfsqJqFKFcOSWpu /9AC0D3mQruuDXqfUqsCKX2mpVk4pq4t4SKUJLCZM2+1QU/CWUafaq3SeoiDOzNRYYBO CNbrAisnGeefiE0yo7w1TutbhQ01DLWxYfogJymRN4+M2uKjDQkEx3d3Hwc209v629cP pbA/5Uv27cDJuN9Pueaa/LA/5usL/tyq3PZ/r26pGM3rnBEdFuu1gNMte2dUESNt9LWt jw4g== X-Gm-Message-State: AKwxytcuYRMWCeZ9JfAXzSH9jnhPrGxyys3SI6oc8psgHXilnx4LLsZA 1sKrSeSQOu9hvTqW1eFL6VgGr4nbkdM= X-Google-Smtp-Source: ACJfBovU2+UwpFFXisD+Z/i8MlldRqyE2r1fY1Obxrasbf4jXCLucEnJbhodB63Z2n03Oifudbc/SA== X-Received: by 10.99.164.25 with SMTP id c25mr3248606pgf.430.1516337700197; Thu, 18 Jan 2018 20:55:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:33 -0800 Message-Id: <20180119045438.28582-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v2 11/16] target/arm: Add SVE to migration state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Save the high parts of the Zregs and all of the Pregs. The ZCR_ELx registers are migrated via the CP mechanism. Signed-off-by: Richard Henderson --- target/arm/machine.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 53 insertions(+) diff --git a/target/arm/machine.c b/target/arm/machine.c index cb0e1c92bb..2c8b43062f 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -122,6 +122,56 @@ static const VMStateDescription vmstate_iwmmxt =3D { } }; =20 +#ifdef TARGET_AARCH64 +/* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, + * and ARMPredicateReg is actively empty. This triggers errors + * in the expansion of the VMSTATE macros. + */ + +static bool sve_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_SVE); +} + +/* The first two words of each Zreg is stored in VFP state. */ +static const VMStateDescription vmstate_zreg_hi_reg =3D { + .name =3D "cpu/sve/zreg_hi", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_preg_reg =3D { + .name =3D "cpu/sve/preg", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_sve =3D { + .name =3D "cpu/sve", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D sve_needed, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, + vmstate_zreg_hi_reg, ARMVectorReg), + VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, + vmstate_preg_reg, ARMPredicateReg), + VMSTATE_END_OF_LIST() + } +}; +#endif /* AARCH64 */ + static bool m_needed(void *opaque) { ARMCPU *cpu =3D opaque; @@ -586,6 +636,9 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_pmsav7, &vmstate_pmsav8, &vmstate_m_security, +#ifdef TARGET_AARCH64 + &vmstate_sve, +#endif NULL } }; --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516338890341725.1032702404622; Thu, 18 Jan 2018 21:14:50 -0800 (PST) Received: from localhost ([::1]:53074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecP0r-0002qG-JC for importer@patchew.org; Fri, 19 Jan 2018 00:14:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58749) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOhk-0002IM-4O for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecOhj-0000Qf-3i for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:04 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:41850) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecOhi-0000Pf-UF for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:03 -0500 Received: by mail-pg0-x242.google.com with SMTP id 136so545866pgd.8 for ; Thu, 18 Jan 2018 20:55:02 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.55.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:55:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T0Ku/m+OPVIQXrjRjLLbX1WOvUqKhYXtYKJWBCusNt0=; b=b52bjVEhVq0Ltp0vm1xjWV6tOtRCY3wWpZQAdbFhDKaP8S+2gmfxj8PpkD3qVk16Fo Y71zpxeMb0sKOPEqX/Tc13ngAuKfsWp0zd8ZXpIkKPlaAjrHRA1XvXgjvPzLM174FXn3 IwbdVdRkdVIMrizGgFrdd8K2yFOAGNT5XpA1Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T0Ku/m+OPVIQXrjRjLLbX1WOvUqKhYXtYKJWBCusNt0=; b=VrAEBcQNhOsxi/2NJNeK/peRVd8KtP/SgBP4yOkIsNIwO5Bjbx+9JIDSp5gzszkHlh IKrfKHPMpP3HXXyyjg+qn1ztd/E4/PjdKTgCdEjsHcymifrFiX39nwNoJEXqZLwPvP1w LZzeOfz/mR4f8alOvd/rhMxyPUvONHQHsHq1Bph3XgkvoLa0FeqeSPVS8zgH/EJ5lOlD 3jYifnA1AhJiOOqWb1q8SwcKfQSlnbYCBA33BwvrN1ZfRHU+OUB6RLy/opogPyG867QP rPv+fHiNbMWZZyRXwAB5LRU0SnhwxLCaHyNtojiGbvdVEWDvGUGz3AniAg/H/caEn9uC qwXw== X-Gm-Message-State: AKwxytcQskx/02HYWIlBd8/qYUW+rJ6YqvKMijiKoXo8Mz1BdzdkwJSb nnYFhdRCB30UWh/sYQuLdJxz2yqWeWQ= X-Google-Smtp-Source: ACJfBotLTdgckaveuPIQN3AKPjXW1+h8Tt1+wQ8Q550pzlXJgA5Zci7DNLT5nTVncCFhZKLxCAsFIQ== X-Received: by 10.101.85.138 with SMTP id j10mr27067544pgs.144.1516337701575; Thu, 18 Jan 2018 20:55:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:34 -0800 Message-Id: <20180119045438.28582-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v2 12/16] target/arm: Add ZCR_ELx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Define ZCR_EL[1-3]. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++++ target/arm/helper.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 85 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0a923e42d8..c8e8155b6e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -547,6 +547,9 @@ typedef struct CPUARMState { */ float_status fp_status; float_status standard_fp_status; + + /* ZCR_EL[1-3] */ + uint64_t zcr_el[4]; } vfp; uint64_t exclusive_addr; uint64_t exclusive_val; @@ -921,6 +924,8 @@ void pmccntr_sync(CPUARMState *env); #define CPTR_TCPAC (1U << 31) #define CPTR_TTA (1U << 20) #define CPTR_TFP (1U << 10) +#define CPTR_TZ (1U << 8) /* CPTR_EL2 */ +#define CPTR_EZ (1U << 8) /* CPTR_EL3 */ =20 #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6705903301..984a4b1306 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4266,6 +4266,82 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = =3D { REGINFO_SENTINEL }; =20 +/* Return the exception level to which SVE-disabled exceptions should + * be taken, or 0 if SVE is enabled. + */ +static int sve_exception_el(CPUARMState *env) +{ +#ifndef CONFIG_USER_ONLY + int highest_el =3D arm_highest_el(env); + int current_el =3D arm_current_el(env); + int i; + + for (i =3D highest_el; i >=3D MAX(1, current_el); --i) { + switch (i) { + case 3: + if ((env->cp15.cptr_el[3] & CPTR_EZ) =3D=3D 0) { + return 3; + } + break; + case 2: + if (env->cp15.cptr_el[2] & CPTR_TZ) { + return 2; + } + break; + case 1: + switch (extract32(env->cp15.cpacr_el1, 16, 2)) { + case 1: + return current_el =3D=3D 0 ? 1 : 0; + case 3: + return 0; + default: + return 1; + } + } + } +#endif + return 0; +} + +static CPAccessResult zcr_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + switch (sve_exception_el(env)) { + case 3: + return CP_ACCESS_TRAP_EL3; + case 2: + return CP_ACCESS_TRAP_EL2; + case 1: + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Bits other than [3:0] are RAZ/WI. */ + raw_write(env, ri, value & 0xf); +} + +static const ARMCPRegInfo sve_cp_reginfo[] =3D { + { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write, }, + { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write, }, + { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D zcr_access, .type =3D ARM_CP_64BIT, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write, }, +}; + void hw_watchpoint_update(ARMCPU *cpu, int n) { CPUARMState *env =3D &cpu->env; @@ -5332,6 +5408,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } define_one_arm_cp_reg(cpu, &sctlr); } + + if (arm_feature(env, ARM_FEATURE_SVE)) { + define_arm_cp_regs(cpu, sve_cp_reginfo); + } } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516338134294995.5586051450978; Thu, 18 Jan 2018 21:02:14 -0800 (PST) Received: from localhost ([::1]:52372 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOoa-0008JL-P9 for importer@patchew.org; Fri, 19 Jan 2018 00:02:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58780) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOhp-0002NY-3m for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecOhk-0000Sj-Lh for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:09 -0500 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:33988) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecOhk-0000Rr-Dc for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:04 -0500 Received: by mail-pf0-x242.google.com with SMTP id e76so538729pfk.1 for ; Thu, 18 Jan 2018 20:55:04 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.55.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:55:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s7E2o85/dcpWdQTn4z5qcP4kMRPC74IMQXUycCabu/c=; b=SuIzDsFJA2l0k2IprwMRXdHZq9LpU6q1eR7KtIwsw7+si73QWLZUtIvi8xIV2lmSQs yFdpU/8auIqmVW1gkKZsLLyuae1e6IGbeObBlgfD+et/ESCm1y0PO/V1J1NBhKH9cSvW 4enG6JcbjJfYadOVWvqkbrKMRs8WlKKuk7IKM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s7E2o85/dcpWdQTn4z5qcP4kMRPC74IMQXUycCabu/c=; b=hHhZq8Vrrx4E+yY/PvrvJDBcuHKg4Od1SWNX4mabw3HWebo9nXeUPEN4iviYBjKG2q bL/d921B0q0ybkWQsHu4DGmfMT/1ekbREAyVqn1cRViIS/zNQhhbfUpXUMP66bsdmOOU tEuwPmhn5xjjHTdPWfxnYDSjzcJPyX8iLQRgUp0v8i4OpjT/E22aZ5EfNMJmybOGWXw3 cfcSOFI4DAMLF1q3Yl+Q9+uS6nsD48zjN9AjH5UQqCoGdFYYQQosY4SBJw6onhR3MY6J DXj5/snUjmY0nGALJiqFg5p5grCt8GYMeZwo/VK7n/YfMiRWIKzbySlt4snKuUbE+hw5 2nmA== X-Gm-Message-State: AKGB3mLeD7fkm9OeYphtIr9fu968J7/JYmb9d2dki/XvHekohWkJZyMQ Nnwc6ocYAeoxAMCosOhaQh23ZrY+IN4= X-Google-Smtp-Source: ACJfBosm0KpUg4JvVRom+TFuYlxDJ4hCVERo689CVYzB+VSdi8YvHrTY41+5EslT5udFE34EI5H/sw== X-Received: by 10.101.100.204 with SMTP id t12mr39493003pgv.135.1516337702921; Thu, 18 Jan 2018 20:55:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:35 -0800 Message-Id: <20180119045438.28582-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v2 13/16] target/arm: Move cpu_get_tb_cpu_state out of line X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 127 +-----------------------------------------------= ---- target/arm/helper.c | 126 ++++++++++++++++++++++++++++++++++++++++++++++++= +++ 2 files changed, 128 insertions(+), 125 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c8e8155b6e..2de1afb53a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2703,71 +2703,6 @@ static inline bool bswap_code(bool sctlr_b) #endif } =20 -/* Return the exception level to which FP-disabled exceptions should - * be taken, or 0 if FP is enabled. - */ -static inline int fp_exception_el(CPUARMState *env) -{ - int fpen; - int cur_el =3D arm_current_el(env); - - /* CPACR and the CPTR registers don't exist before v6, so FP is - * always accessible - */ - if (!arm_feature(env, ARM_FEATURE_V6)) { - return 0; - } - - /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: - * 0, 2 : trap EL0 and EL1/PL1 accesses - * 1 : trap only EL0 accesses - * 3 : trap no accesses - */ - fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); - switch (fpen) { - case 0: - case 2: - if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { - /* Trap to PL1, which might be EL1 or EL3 */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { - return 3; - } - return 1; - } - if (cur_el =3D=3D 3 && !is_a64(env)) { - /* Secure PL1 running at EL3 */ - return 3; - } - break; - case 1: - if (cur_el =3D=3D 0) { - return 1; - } - break; - case 3: - break; - } - - /* For the CPTR registers we don't need to guard with an ARM_FEATURE - * check because zero bits in the registers mean "don't trap". - */ - - /* CPTR_EL2 : present in v7VE or v8 */ - if (cur_el <=3D 2 && extract32(env->cp15.cptr_el[2], 10, 1) - && !arm_is_secure_below_el3(env)) { - /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ - return 2; - } - - /* CPTR_EL3 : present in v8 */ - if (extract32(env->cp15.cptr_el[3], 10, 1)) { - /* Trap all FP ops to EL3 */ - return 3; - } - - return 0; -} - #ifdef CONFIG_USER_ONLY static inline bool arm_cpu_bswap_data(CPUARMState *env) { @@ -2814,66 +2749,8 @@ static inline uint32_t arm_regime_tbi1(CPUARMState *= env, ARMMMUIdx mmu_idx) } #endif =20 -static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *f= lags) -{ - ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); - if (is_a64(env)) { - *pc =3D env->pc; - *flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; - /* Get control bits for tagged addresses */ - *flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIF= T); - *flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIF= T); - } else { - *pc =3D env->regs[15]; - *flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) - | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) - | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) - | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) - | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); - if (!(access_secure_reg(env))) { - *flags |=3D ARM_TBFLAG_NS_MASK; - } - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1)) { - *flags |=3D ARM_TBFLAG_VFPEN_MASK; - } - *flags |=3D (extract32(env->cp15.c15_cpar, 0, 2) - << ARM_TBFLAG_XSCALE_CPAR_SHIFT); - } - - *flags |=3D (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); - - /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine - * states defined in the ARM ARM for software singlestep: - * SS_ACTIVE PSTATE.SS State - * 0 x Inactive (the TB flag for SS is always 0) - * 1 0 Active-pending - * 1 1 Active-not-pending - */ - if (arm_singlestep_active(env)) { - *flags |=3D ARM_TBFLAG_SS_ACTIVE_MASK; - if (is_a64(env)) { - if (env->pstate & PSTATE_SS) { - *flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; - } - } else { - if (env->uncached_cpsr & PSTATE_SS) { - *flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; - } - } - } - if (arm_cpu_data_is_big_endian(env)) { - *flags |=3D ARM_TBFLAG_BE_DATA_MASK; - } - *flags |=3D fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; - - if (arm_v7m_is_handler_mode(env)) { - *flags |=3D ARM_TBFLAG_HANDLER_MASK; - } - - *cs_base =3D 0; -} +void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags); =20 enum { QEMU_PSCI_CONDUIT_DISABLED =3D 0, diff --git a/target/arm/helper.c b/target/arm/helper.c index 984a4b1306..9e673bb672 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11701,3 +11701,129 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t va= l, uint32_t bytes) /* Linux crc32c converts the output to one's complement. */ return crc32c(acc, buf, bytes) ^ 0xffffffff; } + +/* Return the exception level to which FP-disabled exceptions should + * be taken, or 0 if FP is enabled. + */ +static inline int fp_exception_el(CPUARMState *env) +{ + int fpen; + int cur_el =3D arm_current_el(env); + + /* CPACR and the CPTR registers don't exist before v6, so FP is + * always accessible + */ + if (!arm_feature(env, ARM_FEATURE_V6)) { + return 0; + } + + /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: + * 0, 2 : trap EL0 and EL1/PL1 accesses + * 1 : trap only EL0 accesses + * 3 : trap no accesses + */ + fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); + switch (fpen) { + case 0: + case 2: + if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { + /* Trap to PL1, which might be EL1 or EL3 */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + return 3; + } + return 1; + } + if (cur_el =3D=3D 3 && !is_a64(env)) { + /* Secure PL1 running at EL3 */ + return 3; + } + break; + case 1: + if (cur_el =3D=3D 0) { + return 1; + } + break; + case 3: + break; + } + + /* For the CPTR registers we don't need to guard with an ARM_FEATURE + * check because zero bits in the registers mean "don't trap". + */ + + /* CPTR_EL2 : present in v7VE or v8 */ + if (cur_el <=3D 2 && extract32(env->cp15.cptr_el[2], 10, 1) + && !arm_is_secure_below_el3(env)) { + /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ + return 2; + } + + /* CPTR_EL3 : present in v8 */ + if (extract32(env->cp15.cptr_el[3], 10, 1)) { + /* Trap all FP ops to EL3 */ + return 3; + } + + return 0; +} + +void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags) +{ + ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + if (is_a64(env)) { + *pc =3D env->pc; + *flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; + /* Get control bits for tagged addresses */ + *flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIF= T); + *flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIF= T); + } else { + *pc =3D env->regs[15]; + *flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) + | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) + | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) + | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) + | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); + if (!(access_secure_reg(env))) { + *flags |=3D ARM_TBFLAG_NS_MASK; + } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) + || arm_el_is_aa64(env, 1)) { + *flags |=3D ARM_TBFLAG_VFPEN_MASK; + } + *flags |=3D (extract32(env->cp15.c15_cpar, 0, 2) + << ARM_TBFLAG_XSCALE_CPAR_SHIFT); + } + + *flags |=3D (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); + + /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + * states defined in the ARM ARM for software singlestep: + * SS_ACTIVE PSTATE.SS State + * 0 x Inactive (the TB flag for SS is always 0) + * 1 0 Active-pending + * 1 1 Active-not-pending + */ + if (arm_singlestep_active(env)) { + *flags |=3D ARM_TBFLAG_SS_ACTIVE_MASK; + if (is_a64(env)) { + if (env->pstate & PSTATE_SS) { + *flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; + } + } else { + if (env->uncached_cpsr & PSTATE_SS) { + *flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; + } + } + } + if (arm_cpu_data_is_big_endian(env)) { + *flags |=3D ARM_TBFLAG_BE_DATA_MASK; + } + *flags |=3D fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; + + if (arm_v7m_is_handler_mode(env)) { + *flags |=3D ARM_TBFLAG_HANDLER_MASK; + } + + *cs_base =3D 0; +} --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516338308703916.8239367001943; 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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.55.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:55:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MrUbi1cyBrCCWqcwORQqONge1KIiagmroE4y1V6paR4=; b=fsLcWhlCS2JXc7ANw3xBG9PjYuUeoecaJMJbEgqLEyYBmc59SOli5MIOLa6sAMuv/t JUvZCeRDFFPPOHYovg7UFtR/sbMFLmdT7IfitWWojhIzkD3SdqF3NniiHh4RKFCwiAVU b7CuRrT8G4XXXsIbb37s4NL591LLsRtNvk8vw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MrUbi1cyBrCCWqcwORQqONge1KIiagmroE4y1V6paR4=; b=VPw7BcilUXJ9wTlZ7GMaufDPicf6S6l8GlxG/FLgK3DzURgOiyXtLLQE/UQqu3HhzW 9jirI8NMAksv2kEH2GGE7wuZpAjF9KyQELKh8DYN94MniVOk870IEYX9+CYuFshEz1nb 7az0kqVaDl087mGO3JKakqufCGcnyCjXlntwBs8z2Bqrg2PIOXEmG3vph/Lr4otaoDTq NAsJ62RLMoQHIHEnrsUfjVPLZoQmLu8qt6J/+CMmx92NKksAPbUq/MXaSDpsmr25lMl4 4an6r8A929JwkmTJygMyJUmKFfIUQDdR/nNmidq9xFPD3h9B7xRYW9SNi5bDfI1HD3JF M7jQ== X-Gm-Message-State: AKGB3mL85nzBf+Gi+GlDIo+Je84ZlzEWSjcerBSc4IRlBdP9D4IzDaw4 WWgp79/pJB/wfDNSVHO242TM1aGnsV8= X-Google-Smtp-Source: ACJfBosVz+htf6yjkNCLREzxRSfyhJYu8f0TZG8a6oUewSW2yDmoOLJvgZPP264cwVVha4QX/LSKWw== X-Received: by 10.99.94.193 with SMTP id s184mr38254364pgb.397.1516337704480; Thu, 18 Jan 2018 20:55:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:36 -0800 Message-Id: <20180119045438.28582-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v2 14/16] target/arm: Hoist store to flags output in cpu_get_tb_cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9e673bb672..c0e5f321c5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11768,34 +11768,36 @@ static inline int fp_exception_el(CPUARMState *en= v) } =20 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags) + target_ulong *cs_base, uint32_t *pflags) { ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + uint32_t flags; + if (is_a64(env)) { *pc =3D env->pc; - *flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; + flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; /* Get control bits for tagged addresses */ - *flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIF= T); - *flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIF= T); + flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT= ); + flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT= ); } else { *pc =3D env->regs[15]; - *flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) + flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); if (!(access_secure_reg(env))) { - *flags |=3D ARM_TBFLAG_NS_MASK; + flags |=3D ARM_TBFLAG_NS_MASK; } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { - *flags |=3D ARM_TBFLAG_VFPEN_MASK; + flags |=3D ARM_TBFLAG_VFPEN_MASK; } - *flags |=3D (extract32(env->cp15.c15_cpar, 0, 2) - << ARM_TBFLAG_XSCALE_CPAR_SHIFT); + flags |=3D (extract32(env->cp15.c15_cpar, 0, 2) + << ARM_TBFLAG_XSCALE_CPAR_SHIFT); } =20 - *flags |=3D (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); + flags |=3D (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); =20 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: @@ -11805,25 +11807,26 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, * 1 1 Active-not-pending */ if (arm_singlestep_active(env)) { - *flags |=3D ARM_TBFLAG_SS_ACTIVE_MASK; + flags |=3D ARM_TBFLAG_SS_ACTIVE_MASK; if (is_a64(env)) { if (env->pstate & PSTATE_SS) { - *flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; + flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; } } else { if (env->uncached_cpsr & PSTATE_SS) { - *flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; + flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; } } } if (arm_cpu_data_is_big_endian(env)) { - *flags |=3D ARM_TBFLAG_BE_DATA_MASK; + flags |=3D ARM_TBFLAG_BE_DATA_MASK; } - *flags |=3D fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; + flags |=3D fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; =20 if (arm_v7m_is_handler_mode(env)) { - *flags |=3D ARM_TBFLAG_HANDLER_MASK; + flags |=3D ARM_TBFLAG_HANDLER_MASK; } =20 + *pflags =3D flags; *cs_base =3D 0; } --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516338997908434.6411365349202; Thu, 18 Jan 2018 21:16:37 -0800 (PST) Received: from localhost ([::1]:53125 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecP2W-0003xz-97 for importer@patchew.org; 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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.55.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:55:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=woNrRoz9pFHE/sWC8b64H8TxwAXuOSje5AvdLVnP+6Y=; b=Kehbnv9NUtBT0iBs5D4ObCZcJ/xGs4q1spQXBXkmJLt3BKiHp9iDQkAQGLxIpZKSts O03befPmSTxcq6CMOJQOKS4DZnvTMpYD5gYvIj7diWwHp6Sxi7nyWxZWk1YGVQHv2voW OfLnubzFmWPz5ZRFD8gWln5rGDYVtyFM6bFKI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=woNrRoz9pFHE/sWC8b64H8TxwAXuOSje5AvdLVnP+6Y=; b=TexZzmCqXyhFj1gDc2g9Tw1W9KKXT6SE0Mv+Fi2qfSFmcyD3GHUC1Wn/DWwcuI61R0 sVgFM4B2Ufgtq9OTYnUG3u7TpONVz3D3EfM2CfvOS3KmLpX8uWi6NLDkE0nBZkDziKkq YummGPv/Tm+CPD8qnbLBr2o0pUAsjoFcoN2j+bUvo36iZv15aN+VnaldN/LNFEqa6Fhf KuvF9j+46+2MWDAQ+5SoyD9WKZdhBGbFhgNrWDfETmJj2f12FxJymm6r6jkE7qHPuPj0 E1NXtHQxDSTr2x4NUHvdhdn4uPk0npG/UogKP4iyLmLMsORmz9Uk7kC3ZfnSVp8DFNh5 Pymw== X-Gm-Message-State: AKGB3mKc6OT3e6A8m/32cLF2wpQLU1Mb7s+vLWydUoc/wCDX5pbo0It6 v/8Z9g2apuGG0YmXy3k+UcbuHILYBag= X-Google-Smtp-Source: ACJfBosp5yZaWAVX+2hTd7cPN600clmM74yYrBlMWm+eh2Jh1suEBPmV3QSTTDcHQ+N8TUnpMf5ADQ== X-Received: by 10.99.1.151 with SMTP id 145mr31245410pgb.229.1516337705845; Thu, 18 Jan 2018 20:55:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:37 -0800 Message-Id: <20180119045438.28582-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 15/16] target/arm: Simplify fp_exception_el for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c0e5f321c5..44814af99b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11707,6 +11707,7 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,= uint32_t bytes) */ static inline int fp_exception_el(CPUARMState *env) { +#ifndef CONFIG_USER_ONLY int fpen; int cur_el =3D arm_current_el(env); =20 @@ -11763,7 +11764,7 @@ static inline int fp_exception_el(CPUARMState *env) /* Trap all FP ops to EL3 */ return 3; } - +#endif return 0; } =20 --=20 2.14.3 From nobody Sat Apr 27 14:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151633796804723.034853233560852; Thu, 18 Jan 2018 20:59:28 -0800 (PST) Received: from localhost ([::1]:52337 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOly-000613-W8 for importer@patchew.org; Thu, 18 Jan 2018 23:59:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58794) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecOhp-0002Nb-JN for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecOho-0000Wt-Ou for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:09 -0500 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:33536) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecOho-0000Vp-Ih for qemu-devel@nongnu.org; Thu, 18 Jan 2018 23:55:08 -0500 Received: by mail-pf0-x244.google.com with SMTP id t5so538424pfi.0 for ; Thu, 18 Jan 2018 20:55:08 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id m12sm13690022pga.68.2018.01.18.20.55.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2018 20:55:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NsYKHm75l4RdxnA2GN9YianVyXTxkU5IkMB6x4+lVTg=; b=eW6IivKNjHGwmEMMmOCIaDxm1cM2mVWMmB6TlU1v+p62yEUew8BBH0q/9fZqy0M8yK S0jhykU7L8RDq1d+55HrihWKJVley5wh8awFgqI/+vDJ2PAvfzdU+2ygg5SKrXHFy0sQ NPERGu+VNywpam8Mj0l+MZSbCSfO42LXRz0DE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NsYKHm75l4RdxnA2GN9YianVyXTxkU5IkMB6x4+lVTg=; b=Pt4XRmESIdEt2H/bGVH1qV6hHo67vwzVKzHT0Du4BRQeTLDZpxIkNfWTHxOg/JkmWV 2oIJtj5v7CTIKduKsAMvmX53rvDLO19Pnp/iMzLmkRUAp5c0V4dopNtlVOwiLk1bPVk+ +w6JWIYNBK25/liw9qRKHF5Np4GQG5zIaS37gU7M9PcAsQV0JU3s9zJUmJ44Ybcgo/jV EYduec0elXgcQy/JbYGOOLxGqkO4IpEQgTgCFaRb3guv/4Px2eany88KSxsQuji0QAa6 IW9WRwyv6kJUrxxPeQ4BQbCXLs7D6oi0AhlxnxXCIPJ6ZpY40hjgSUzi98/KRRQ3RpM4 HAWw== X-Gm-Message-State: AKGB3mK3I03gXSojdTjACANH4Xz4cQvhRHFSjV9Enh9XjKPCOmCJ8LJb En+i3aHcLUw8TtrSdvIn+OwinP9m5gA= X-Google-Smtp-Source: ACJfBota8cQIjYMHxvyTGH44NOMVY7hbccGou28HXVOmZXMUHXfKoso5aKiO5lPMsN3An3qXMO77rA== X-Received: by 10.98.32.151 with SMTP id m23mr38633400pfj.182.1516337707230; Thu, 18 Jan 2018 20:55:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Jan 2018 20:54:38 -0800 Message-Id: <20180119045438.28582-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119045438.28582-1-richard.henderson@linaro.org> References: <20180119045438.28582-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v2 16/16] target/arm: Add SVE state to TB->FLAGS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add both SVE exception state and vector length. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++++ target/arm/helper.c | 23 ++++++++++++++++++++++- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2de1afb53a..d7208d56df 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2646,6 +2646,10 @@ static inline bool arm_cpu_data_is_big_endian(CPUARM= State *env) #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) +#define ARM_TBFLAG_SVEEXC_EL_SHIFT 2 +#define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) +#define ARM_TBFLAG_ZCR_LEN_SHIFT 4 +#define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) =20 /* some convenience accessor macros */ #define ARM_TBFLAG_AARCH64_STATE(F) \ diff --git a/target/arm/helper.c b/target/arm/helper.c index 44814af99b..6072634ca8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11772,14 +11772,35 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + int fp_el =3D fp_exception_el(env); uint32_t flags; =20 if (is_a64(env)) { + int sve_el =3D sve_exception_el(env); + uint32_t zcr_len; + *pc =3D env->pc; flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; /* Get control bits for tagged addresses */ flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT= ); flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT= ); + flags |=3D sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT; + + /* If SVE is disabled, but FP is enabled, + then the effective len is 0. */ + if (sve_el !=3D 0 && fp_el =3D=3D 0) { + zcr_len =3D 0; + } else { + int highest_el =3D arm_highest_el(env); + int current_el =3D arm_current_el(env); + int i; + + zcr_len =3D 0xf & (uint32_t)env->vfp.zcr_el[highest_el]; + for (i =3D highest_el - 1; i >=3D MAX(1, current_el); --i) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[i= ]); + } + } + flags |=3D zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT; } else { *pc =3D env->regs[15]; flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) @@ -11822,7 +11843,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (arm_cpu_data_is_big_endian(env)) { flags |=3D ARM_TBFLAG_BE_DATA_MASK; } - flags |=3D fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; + flags |=3D fp_el << ARM_TBFLAG_FPEXC_EL_SHIFT; =20 if (arm_v7m_is_handler_mode(env)) { flags |=3D ARM_TBFLAG_HANDLER_MASK; --=20 2.14.3