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X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PATCH v7 01/14] sdhci: add v3 capabilities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , Prasad J Pandit , Peter Crosthwaite , Andrey Smirnov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, Sai Pavan Boddu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/sd/sdhci-internal.h | 21 +++++++++++++++++++++ include/hw/sd/sdhci.h | 5 +++++ hw/sd/sdhci.c | 24 ++++++++++++++++++++++-- 3 files changed, 48 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 4ed9727ec3..ac4704eb61 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -43,6 +43,7 @@ #define SDHC_TRNS_DMA 0x0001 #define SDHC_TRNS_BLK_CNT_EN 0x0002 #define SDHC_TRNS_ACMD12 0x0004 +#define SDHC_TRNS_ACMD23 0x0008 /* since v3 */ #define SDHC_TRNS_READ 0x0010 #define SDHC_TRNS_MULTI 0x0020 #define SDHC_TRNMOD_MASK 0x0037 @@ -183,12 +184,23 @@ FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR, 1, 1); FIELD(SDHC_ACMD12ERRSTS, CRC_ERR, 2, 1); FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1); =20 +/* Host Control Register 2 (since v3) */ +#define SDHC_HOSTCTL2 0x3E +FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL, 0, 3); +FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1); +FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1); + /* HWInit Capabilities Register 0x05E80080 */ #define SDHC_CAPAB 0x40 FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6); FIELD(SDHC_CAPAB, TOUNIT, 7, 1); FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8); FIELD(SDHC_CAPAB, MAXBLOCKLENGTH, 16, 2); +FIELD(SDHC_CAPAB, EMBEDDED_8BIT, 18, 1); /* since v3 */ FIELD(SDHC_CAPAB, ADMA2, 19, 1); /* since v2 */ FIELD(SDHC_CAPAB, ADMA1, 20, 1); /* v1 only? */ FIELD(SDHC_CAPAB, HIGHSPEED, 21, 1); @@ -198,6 +210,15 @@ FIELD(SDHC_CAPAB, V33, 24, 1); FIELD(SDHC_CAPAB, V30, 25, 1); FIELD(SDHC_CAPAB, V18, 26, 1); FIELD(SDHC_CAPAB, BUS64BIT, 28, 1); /* since v2 */ +FIELD(SDHC_CAPAB, ASYNC_INT, 29, 1); /* since v3 */ +FIELD(SDHC_CAPAB, SLOT_TYPE, 30, 2); /* since v3 */ +FIELD(SDHC_CAPAB, BUS_SPEED, 32, 3); /* since v3 */ +FIELD(SDHC_CAPAB, DRIVER_STRENGTH, 36, 3); /* since v3 */ +FIELD(SDHC_CAPAB, DRIVER_TYPE_A, 36, 1); /* since v3 */ +FIELD(SDHC_CAPAB, DRIVER_TYPE_C, 37, 1); /* since v3 */ +FIELD(SDHC_CAPAB, DRIVER_TYPE_D, 38, 1); /* since v3 */ +FIELD(SDHC_CAPAB, TIMER_RETUNNING, 40, 4); /* since v3 */ +FIELD(SDHC_CAPAB, SDR50_TUNNING, 45, 1); /* since v3 */ =20 /* HWInit Maximum Current Capabilities Register 0x0 */ #define SDHC_MAXCURR 0x48 diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 7e624135f0..bf3bf243d7 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -115,6 +115,11 @@ typedef struct SDHCIState { ***********/ bool adma1, adma2; bool bus64; + + /*********** + * Spec v3 + ***********/ + uint8_t slot_type, sdr, strength; } cap; } SDHCIState; =20 diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index e2379d610f..946dff0fac 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -65,6 +65,18 @@ static uint64_t sdhci_init_capareg(SDHCIState *s, Error = **errp) uint32_t val; =20 switch (s->spec_version) { + case 3: + val =3D FIELD_EX64(capareg, SDHC_CAPAB, SLOT_TYPE); + if (val) { + error_setg(errp, "slot-type not supported"); + return 0; + } + capareg =3D FIELD_DP64(capareg, SDHC_CAPAB, SLOT_TYPE, val); + capareg =3D FIELD_DP64(capareg, SDHC_CAPAB, BUS_SPEED, s->cap.sdr); + capareg =3D FIELD_DP64(capareg, SDHC_CAPAB, DRIVER_STRENGTH, + s->cap.strength); + + /* fallback */ case 2: /* default version */ capareg =3D FIELD_DP64(capareg, SDHC_CAPAB, ADMA1, s->cap.adma1); capareg =3D FIELD_DP64(capareg, SDHC_CAPAB, ADMA2, s->cap.adma2); @@ -1175,8 +1187,11 @@ static void sdhci_init_readonly_registers(SDHCIState= *s, Error **errp) uint64_t capab; Error *local_err =3D NULL; =20 - if (s->spec_version !=3D 2) { - error_setg(errp, "Only Spec v2 is supported"); + switch (s->spec_version) { + case 2 ... 3: + break; + default: + error_setg(errp, "Only Spec v2/v3 are supported"); return; } s->version =3D (SDHC_HCVER_VENDOR << 8) | (s->spec_version - 1); @@ -1219,6 +1234,11 @@ static void sdhci_init_readonly_registers(SDHCIState= *s, Error **errp) DEFINE_PROP_BOOL("adma2", _state, cap.adma2, true), \ DEFINE_PROP_BOOL("64bit", _state, cap.bus64, false), \ \ + /* Spec v3 properties */ \ + DEFINE_PROP_UINT8("slot-type", _state, cap.slot_type, 0), \ + DEFINE_PROP_UINT8("bus-speed", _state, cap.sdr, 0), \ + DEFINE_PROP_UINT8("driver-strength", _state, cap.strength, 0), \ + \ /* deprecated: Capabilities registers provide information on supported * features of this specific host controller implementation */ \ DEFINE_PROP_UINT64("capareg", _state, capareg, UINT64_MAX), \ --=20 2.15.1