From nobody Tue Oct 28 01:57:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516208263088481.3784879467919; Wed, 17 Jan 2018 08:57:43 -0800 (PST) Received: from localhost ([::1]:47016 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebr1s-0002cL-TM for importer@patchew.org; Wed, 17 Jan 2018 11:57:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39394) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebqNP-00079X-L2 for qemu-devel@nongnu.org; Wed, 17 Jan 2018 11:15:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ebqNM-0003xa-EA for qemu-devel@nongnu.org; Wed, 17 Jan 2018 11:15:47 -0500 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:45441) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ebqNM-0003xA-5i for qemu-devel@nongnu.org; Wed, 17 Jan 2018 11:15:44 -0500 Received: by mail-pl0-x244.google.com with SMTP id p5so9242645plo.12 for ; Wed, 17 Jan 2018 08:15:44 -0800 (PST) Received: from cloudburst.twiddle.net.com (24-181-135-57.dhcp.knwc.wa.charter.com. [24.181.135.57]) by smtp.gmail.com with ESMTPSA id l10sm1099311pff.64.2018.01.17.08.15.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Jan 2018 08:15:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2Qut2C+PPvZzshMcW36vnCOe2rrAZM2M13ANAqSfibw=; b=WwgD6ELnn1gQ7r675OtQ8ac2z5in4t+p22WROO9WzipQgAvOgDdnWo2TBgxq1A/uM5 nXstZ3dXsuFRlXGG+k23dlnD3nGWMOB/K59KvhPdBjLG4WPKjKH09fr/gsX4nzhSrpQd 0L6a+yxOadkcBRDVOzN1zhIIv/0RJgnWs53XM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2Qut2C+PPvZzshMcW36vnCOe2rrAZM2M13ANAqSfibw=; b=qtyP9PdJoQ99IGAiI0gRQPGebKymPlYximQ4FYatsb6uDv84UL7ZnE7GKJRvsv3dVr /QiOpK/2TGAP+16iUl/5ibXMN1Zgz1uuRwXvlTTOexoLk6HA6yaxqOOus5xJohbnVD46 y/ykZNtWWiaWCECo6mEXhYdEXigtNZ+GrGJtNBEIe5Q/XZ/tpKclZpg8UEJEVGVIOvjy 5ViaMHVwzCIex6jcv6CEuAtu70SxsBPPJaEemcRAzSxRlpmNRhh3UCTD7Q12jcSZzl63 k1GyB8jTHqtHwtFu2Un30EPN+fVct9L3MjF4njfQeYp0zgd4D17t9xpYt6Is6g8MtRgV xFUw== X-Gm-Message-State: AKwxytc34xDyzyIqdgYY45b6Gp0ChzfkzCNQJqMtPznk8pNbSQ8T1Pi2 PSjOntNO5ZCFBKR/ApvwIudI0Q5vsxE= X-Google-Smtp-Source: ACJfBotPGPuTFwPhLzRzL6OKEAdADHWLjcdQhmQ4G862WnEDJoY6YgLB6ZfIBBG9s+BsvMdC2dxZHA== X-Received: by 10.84.169.65 with SMTP id g59mr2503458plb.200.1516205742789; Wed, 17 Jan 2018 08:15:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 17 Jan 2018 08:14:32 -0800 Message-Id: <20180117161435.28981-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180117161435.28981-1-richard.henderson@linaro.org> References: <20180117161435.28981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v10.5 17/20] target/arm: Use vector infrastructure for aa64 multiplies X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 171 ++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 138 insertions(+), 33 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 686fc98d56..e8fc4bc27e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9741,6 +9741,66 @@ static void disas_simd_3same_float(DisasContext *s, = uint32_t insn) } } =20 +static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u8(a, a, b); + gen_helper_neon_add_u8(d, d, a); +} + +static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u16(a, a, b); + gen_helper_neon_add_u16(d, d, a); +} + +static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_mul_i32(a, a, b); + tcg_gen_add_i32(d, d, a); +} + +static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_mul_i64(a, a, b); + tcg_gen_add_i64(d, d, a); +} + +static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + tcg_gen_mul_vec(vece, a, a, b); + tcg_gen_add_vec(vece, d, d, a); +} + +static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u8(a, a, b); + gen_helper_neon_sub_u8(d, d, a); +} + +static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u16(a, a, b); + gen_helper_neon_sub_u16(d, d, a); +} + +static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_mul_i32(a, a, b); + tcg_gen_sub_i32(d, d, a); +} + +static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_mul_i64(a, a, b); + tcg_gen_sub_i64(d, d, a); +} + +static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + tcg_gen_mul_vec(vece, a, a, b); + tcg_gen_sub_vec(vece, d, d, a); +} + /* Integer op subgroup of C3.6.16. */ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) { @@ -9752,7 +9812,8 @@ static void disas_simd_3same_int(DisasContext *s, uin= t32_t insn) int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); int pass; - GVecGen3Fn *gvec_op; + GVecGen3Fn *gvec_fn; + const GVecGen3 *gvec_op; TCGCond cond; =20 switch (opcode) { @@ -9795,12 +9856,70 @@ static void disas_simd_3same_int(DisasContext *s, u= int32_t insn) =20 switch (opcode) { case 0x10: /* ADD, SUB */ - gvec_op =3D u ? tcg_gen_gvec_sub : tcg_gen_gvec_add; - gvec_op(size, vec_full_reg_offset(s, rd), + gvec_fn =3D u ? tcg_gen_gvec_sub : tcg_gen_gvec_add; + do_gvec: + gvec_fn(size, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), vec_full_reg_offset(s, rm), is_q ? 16 : 8, vec_full_reg_size(s)); return; + case 0x13: /* MUL, PMUL */ + if (!u) { /* MUL */ + gvec_fn =3D tcg_gen_gvec_mul; + goto do_gvec; + } + break; + case 0x12: /* MLA, MLS */ + { + static const GVecGen3 mla_op[4] =3D { + { .fni4 =3D gen_mla8_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_8 }, + { .fni4 =3D gen_mla16_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_16 }, + { .fni4 =3D gen_mla32_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_32 }, + { .fni8 =3D gen_mla64_i64, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .vece =3D MO_64 }, + }; + static const GVecGen3 mls_op[4] =3D { + { .fni4 =3D gen_mls8_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_8 }, + { .fni4 =3D gen_mls16_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_16 }, + { .fni4 =3D gen_mls32_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_32 }, + { .fni8 =3D gen_mls64_i64, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .vece =3D MO_64 }, + }; + gvec_op =3D (u ? &mls_op[size] : &mla_op[size]); + } + goto do_gvec_op; case 0x11: if (u) { /* CMEQ */ cond =3D TCG_COND_EQ; @@ -9821,12 +9940,13 @@ static void disas_simd_3same_int(DisasContext *s, u= int32_t insn) .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; - tcg_gen_gvec_3(vec_full_reg_offset(s, rd), - vec_full_reg_offset(s, rn), - vec_full_reg_offset(s, rm), - is_q ? 16 : 8, vec_full_reg_size(s), - &cmtst_op[size]); + gvec_op =3D &cmtst_op[size]; } + do_gvec_op: + tcg_gen_gvec_3(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s), gvec_op); return; case 0x06: /* CMGT, CMHI */ cond =3D u ? TCG_COND_GTU : TCG_COND_GT; @@ -9994,23 +10114,10 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) break; } case 0x13: /* MUL, PMUL */ - if (u) { - /* PMUL */ - assert(size =3D=3D 0); - genfn =3D gen_helper_neon_mul_p8; - break; - } - /* fall through : MUL */ - case 0x12: /* MLA, MLS */ - { - static NeonGenTwoOpFn * const fns[3] =3D { - gen_helper_neon_mul_u8, - gen_helper_neon_mul_u16, - tcg_gen_mul_i32, - }; - genfn =3D fns[size]; + assert(u); /* PMUL */ + assert(size =3D=3D 0); + genfn =3D gen_helper_neon_mul_p8; break; - } case 0x16: /* SQDMULH, SQRDMULH */ { static NeonGenTwoOpEnvFn * const fns[2][2] =3D { @@ -10031,18 +10138,16 @@ static void disas_simd_3same_int(DisasContext *s,= uint32_t insn) genfn(tcg_res, tcg_op1, tcg_op2); } =20 - if (opcode =3D=3D 0xf || opcode =3D=3D 0x12) { - /* SABA, UABA, MLA, MLS: accumulating ops */ - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, - { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, - { tcg_gen_add_i32, tcg_gen_sub_i32 }, + if (opcode =3D=3D 0xf) { + /* SABA, UABA: accumulating ops */ + static NeonGenTwoOpFn * const fns[3] =3D { + gen_helper_neon_add_u8, + gen_helper_neon_add_u16, + tcg_gen_add_i32, }; - bool is_sub =3D (opcode =3D=3D 0x12 && u); /* MLS */ =20 - genfn =3D fns[size][is_sub]; read_vec_element_i32(s, tcg_op1, rd, pass, MO_32); - genfn(tcg_res, tcg_op1, tcg_res); + fns[size](tcg_res, tcg_op1, tcg_res); } =20 write_vec_element_i32(s, tcg_res, rd, pass, MO_32); --=20 2.14.3