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[24.181.135.57]) by smtp.gmail.com with ESMTPSA id l10sm1099311pff.64.2018.01.17.08.15.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Jan 2018 08:15:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6y7ncWeSPZZxGmJvRMdRjUcxyjKf893nQGswZVVKYt8=; b=IiM2qmMQyTQhlapwBkl4xbzxlOd7b/MFxlMtZZcJX/7/FGqdA6742tJ9bsiwk2s5vP fboM5bK5kyM4uCSAgompKGAhQLJvsr+MzJz3bdHJpRdAW8bYOob4RO2cPNNYCsRzhvnX C2kYkDWB1gq/mH9N+bk4Pkb5YMnBhPJrBku70= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6y7ncWeSPZZxGmJvRMdRjUcxyjKf893nQGswZVVKYt8=; b=N0jHBDARQdMKRhus2lqiM5NxqHWHs2j/chrH/zq/vGOQDAopW2w9Yv9vMwgc9F7eUf ukCjU8w24PrPXfqNSGYcJ+uCvAvyCC5M77nWA0FAJmCoK0Gq/koiIGvv19J7NUReiL47 NxMyiLyFGf1mfBnRN6R7r5RdVEv87beo8aSPCATKgo6tNRsUnwa6+0ZrqzZXgAjz0hvV kVPS8Z98EzZEPRMSJjxWAuTK5SAPlgYS/x+FnzQgP0IoB2LtGPH/0XmD2JrmB4T0+Iso mwJVYNn3KwCO64CWwIs6E1czkSNcz56Q2VGh1fM0kASgkvn6DyZm2LEGE2DkouCyUErG S6Qw== X-Gm-Message-State: AKGB3mI95a6b+Xz3HcPCqpSle56f785RUP/xwDZPOEZZWLb0CF2C98dg HrL+wlNow8Z4SNvZ1a+RPa5+aoUnzxk= X-Google-Smtp-Source: ACJfBovHT0oNKUyiQf7goLG9GtA4gz7hUFM+cjL5G3+x+sMD+xJKYvDsAmsd8AYBxICwg3ORGaz9Sw== X-Received: by 10.159.242.196 with SMTP id x4mr35107795plw.408.1516205739534; Wed, 17 Jan 2018 08:15:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 17 Jan 2018 08:14:31 -0800 Message-Id: <20180117161435.28981-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180117161435.28981-1-richard.henderson@linaro.org> References: <20180117161435.28981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v10.5 16/20] target/arm: Use vector infrastructure for aa64 compares X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 96 ++++++++++++++++++++++++++++++------------= ---- 1 file changed, 62 insertions(+), 34 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1b5005637d..686fc98d56 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7172,6 +7172,28 @@ static void disas_simd_scalar_three_reg_diff(DisasCo= ntext *s, uint32_t insn) } } =20 +/* CMTST : test is "if (X & Y !=3D 0)". */ +static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_and_i32(d, a, b); + tcg_gen_setcondi_i32(TCG_COND_NE, d, d, 0); + tcg_gen_neg_i32(d, d); +} + +static void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_and_i64(d, a, b); + tcg_gen_setcondi_i64(TCG_COND_NE, d, d, 0); + tcg_gen_neg_i64(d, d); +} + +static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec = b) +{ + tcg_gen_and_vec(vece, d, a, b); + tcg_gen_dupi_vec(vece, a, 0); + tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a); +} + static void handle_3same_64(DisasContext *s, int opcode, bool u, TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg= _rm) { @@ -7215,10 +7237,7 @@ static void handle_3same_64(DisasContext *s, int opc= ode, bool u, cond =3D TCG_COND_EQ; goto do_cmop; } - /* CMTST : test is "if (X & Y !=3D 0)". */ - tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); - tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0); - tcg_gen_neg_i64(tcg_rd, tcg_rd); + gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm); break; case 0x8: /* SSHL, USHL */ if (u) { @@ -9734,6 +9753,7 @@ static void disas_simd_3same_int(DisasContext *s, uin= t32_t insn) int rd =3D extract32(insn, 0, 5); int pass; GVecGen3Fn *gvec_op; + TCGCond cond; =20 switch (opcode) { case 0x13: /* MUL, PMUL */ @@ -9781,6 +9801,44 @@ static void disas_simd_3same_int(DisasContext *s, ui= nt32_t insn) vec_full_reg_offset(s, rm), is_q ? 16 : 8, vec_full_reg_size(s)); return; + case 0x11: + if (u) { /* CMEQ */ + cond =3D TCG_COND_EQ; + goto do_gvec_cmp; + } else { /* CMTST */ + static const GVecGen3 cmtst_op[4] =3D { + { .fni4 =3D gen_helper_neon_tst_u8, + .fniv =3D gen_cmtst_vec, + .vece =3D MO_8 }, + { .fni4 =3D gen_helper_neon_tst_u16, + .fniv =3D gen_cmtst_vec, + .vece =3D MO_16 }, + { .fni4 =3D gen_cmtst_i32, + .fniv =3D gen_cmtst_vec, + .vece =3D MO_32 }, + { .fni8 =3D gen_cmtst_i64, + .fniv =3D gen_cmtst_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + tcg_gen_gvec_3(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s), + &cmtst_op[size]); + } + return; + case 0x06: /* CMGT, CMHI */ + cond =3D u ? TCG_COND_GTU : TCG_COND_GT; + goto do_gvec_cmp; + case 0x07: /* CMGE, CMHS */ + cond =3D u ? TCG_COND_GEU : TCG_COND_GE; + do_gvec_cmp: + tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s)); + return; } =20 if (size =3D=3D 3) { @@ -9863,26 +9921,6 @@ static void disas_simd_3same_int(DisasContext *s, ui= nt32_t insn) genenvfn =3D fns[size][u]; break; } - case 0x6: /* CMGT, CMHI */ - { - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_u8 }, - { gen_helper_neon_cgt_s16, gen_helper_neon_cgt_u16 }, - { gen_helper_neon_cgt_s32, gen_helper_neon_cgt_u32 }, - }; - genfn =3D fns[size][u]; - break; - } - case 0x7: /* CMGE, CMHS */ - { - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_cge_s8, gen_helper_neon_cge_u8 }, - { gen_helper_neon_cge_s16, gen_helper_neon_cge_u16 }, - { gen_helper_neon_cge_s32, gen_helper_neon_cge_u32 }, - }; - genfn =3D fns[size][u]; - break; - } case 0x8: /* SSHL, USHL */ { static NeonGenTwoOpFn * const fns[3][2] =3D { @@ -9955,16 +9993,6 @@ static void disas_simd_3same_int(DisasContext *s, ui= nt32_t insn) genfn =3D fns[size][u]; break; } - case 0x11: /* CMTST, CMEQ */ - { - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_tst_u8, gen_helper_neon_ceq_u8 }, - { gen_helper_neon_tst_u16, gen_helper_neon_ceq_u16 }, - { gen_helper_neon_tst_u32, gen_helper_neon_ceq_u32 }, - }; - genfn =3D fns[size][u]; - break; - } case 0x13: /* MUL, PMUL */ if (u) { /* PMUL */ --=20 2.14.3