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[24.181.135.63]) by smtp.gmail.com with ESMTPSA id t25sm6368905pfk.162.2018.01.17.08.09.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Jan 2018 08:09:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vwUcioa4aIYbkW7yILTXEtQO1bjKmCKAcVFBi0AQ/ws=; b=ZKPHTblUJMdv5SAnJ7C0/SOCLmFTGYcujt8nAG7CGoh+88zGMwfUraiIVQILo2X4cR YGK2VyV/qa/zCE/zaxfDaOIsESGUK0fYkuAJxvYUB7OW9YcncC4OqeqTwY4/vVO7Mmc8 UlH4xe04TqLgq0vsJptyHhFdKh0Ug0GkT3Py8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vwUcioa4aIYbkW7yILTXEtQO1bjKmCKAcVFBi0AQ/ws=; b=mqnKLQT0TX3V4blxGz4FzLY9SiWQ8wx62nIKyCOU1mjvIHon7TGZ7Rwe2CBIKriLWn eqqj+P7X4kB0NIj8lKy+5Sd3fKqhuaa+zpIyTyA1cYAML4VSgqV3VRGa8Z23szZ/JZ0+ S85L90ywzi8pkoRWfA0IFoBH8kzzqQf0ZqZjvfwvCGH3WHK242hAQ2xIKjQdKKEmG/4w WCZZaD61idPG0TuL+fKup5pzVdBSEK6Z4lBCNptpHzXZSpbAp2dVNjH0hh+qnYGIWs8/ Y5x4TGcevaI+zUsP4R6CQ4jXEdPrNjccxFbtO3x2XSwrA4LStHM+3O5Pp/unUbJPzND7 3u+Q== X-Gm-Message-State: AKwxytesXP7U9sWa/M/mdOEpEt/5kUVPxz9O14cawLM9yU4rPVB44h8L 9g85pAn3wBSkQB9v6b2ticidIpoEQC0= X-Google-Smtp-Source: ACJfBotdcnUVqtO1NwKdCsxzYbJ6JlCgNVd/o3D/9Wg0jsr4jnMbVchWnjbBtQBJH+953+2sk8+zDA== X-Received: by 10.159.251.136 with SMTP id m8mr21746752pls.432.1516205387328; Wed, 17 Jan 2018 08:09:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 17 Jan 2018 08:09:17 -0800 Message-Id: <20180117160933.28086-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180117160933.28086-1-richard.henderson@linaro.org> References: <20180117160933.28086-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v10 05/21] tcg: Loosen vec_gen_op* typecheck rules X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For ARM SVE with VQ=3D3, we want to be able to dup a scalar into a v256, use that, and then perform a second operation with the v256 punned to a v128. Allow operands to a vector operation be wider than necessary for the output. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 5cfe4af6bd..97b437e41a 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -78,7 +78,8 @@ static void vec_gen_op2(TCGOpcode opc, unsigned vece, TCG= v_vec r, TCGv_vec a) TCGTemp *at =3D tcgv_vec_temp(a); TCGType type =3D rt->base_type; =20 - tcg_debug_assert(at->base_type =3D=3D type); + /* Must enough inputs for the output. */ + tcg_debug_assert(at->base_type >=3D type); vec_gen_2(opc, type, vece, temp_arg(rt), temp_arg(at)); } =20 @@ -90,8 +91,9 @@ static void vec_gen_op3(TCGOpcode opc, unsigned vece, TCGTemp *bt =3D tcgv_vec_temp(b); TCGType type =3D rt->base_type; =20 - tcg_debug_assert(at->base_type =3D=3D type); - tcg_debug_assert(bt->base_type =3D=3D type); + /* Must enough inputs for the output. */ + tcg_debug_assert(at->base_type >=3D type); + tcg_debug_assert(bt->base_type >=3D type); vec_gen_3(opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt)); } =20 @@ -257,14 +259,14 @@ void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, T= CGv_i64 a) =20 if (TCG_TARGET_REG_BITS =3D=3D 64) { TCGArg ai =3D tcgv_i64_arg(a); - vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai); + vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } else if (vece =3D=3D MO_64) { TCGArg al =3D tcgv_i32_arg(TCGV_LOW(a)); TCGArg ah =3D tcgv_i32_arg(TCGV_HIGH(a)); vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah); } else { TCGArg ai =3D tcgv_i32_arg(TCGV_LOW(a)); - vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai); + vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } } =20 --=20 2.14.3