From nobody Tue Oct 28 01:56:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1516156888207480.06630039879565; Tue, 16 Jan 2018 18:41:28 -0800 (PST) Received: from localhost ([::1]:56035 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebdfL-0003R7-9e for importer@patchew.org; Tue, 16 Jan 2018 21:41:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45579) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebdQJ-0007rT-Lf for qemu-devel@nongnu.org; Tue, 16 Jan 2018 21:25:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ebdQI-0001J6-2O for qemu-devel@nongnu.org; Tue, 16 Jan 2018 21:25:55 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:51279) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ebdQH-0001Gy-OQ; Tue, 16 Jan 2018 21:25:54 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zLrY474hTz9sP1; Wed, 17 Jan 2018 13:25:44 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1516155945; bh=byyMZfj5aqf0zKje/LrrEZN+HjPb8ugqhTGq6zc6jXk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YCCGJcvB2FfI/QFIHRnF9t/hwUi7h4AXhBrBY6Wckvb1yoL8FTNccJ/IX1n3Lvaj1 /SaOhseV5L3wUkHWaMbgTTRaaiAPAXALilz7vWpPIazgUycxJ7mlLV6659AzB5yout PYnpJjKU09qJuSfiW3i/60q0Ch6LXIFuRD7clZdo= From: David Gibson To: peter.maydell@linaro.org Date: Wed, 17 Jan 2018 13:25:06 +1100 Message-Id: <20180117022525.31767-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180117022525.31767-1-david@gibson.dropbear.id.au> References: <20180117022525.31767-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 03/22] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, surajjs@au1.ibm.com, joserz@linux.vnet.ibm.com, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This adds an spapr capability bit for Hardware Transactional Memory. It is enabled by default for pseries-2.11 and earlier machine types. with POWER8 or later CPUs (as it must be, since earlier qemu versions would implicitly allow it). However it is disabled by default for the latest pseries-2.12 machine type. This means that with the latest machine type, HTM will not be available, regardless of CPU, unless it is explicitly enabled on the command line. That change is made on the basis that: * This way running with -M pseries,accel=3Dtcg will start with whatever cpu and will provide the same guest visible model as with accel=3Dkvm. - More specifically, this means existing make check tests don't have to be modified to use cap-htm=3Doff in order to run with TCG * We hope to add a new "HTM without suspend" feature in the not too distant future which could work on both POWER8 and POWER9 cpus, and could be enabled by default. * Best guesses suggest that future POWER cpus may well only support the HTM-without-suspend model, not the (frankly, horribly overcomplicated) POWER8 style HTM with suspend. * Anecdotal evidence suggests problems with HTM being enabled when it wasn't wanted are more common than being missing when it was. Signed-off-by: David Gibson Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 15 ++++++++++----- hw/ppc/spapr_caps.c | 29 ++++++++++++++++++++++++++++- include/hw/ppc/spapr.h | 3 +++ 3 files changed, 41 insertions(+), 6 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index a6cf1234d8..73310bd3ee 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -253,7 +253,9 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int offse= t, PowerPCCPU *cpu) } =20 /* Populate the "ibm,pa-features" property */ -static void spapr_populate_pa_features(PowerPCCPU *cpu, void *fdt, int off= set, +static void spapr_populate_pa_features(sPAPRMachineState *spapr, + PowerPCCPU *cpu, + void *fdt, int offset, bool legacy_guest) { CPUPPCState *env =3D &cpu->env; @@ -318,7 +320,7 @@ static void spapr_populate_pa_features(PowerPCCPU *cpu,= void *fdt, int offset, */ pa_features[3] |=3D 0x20; } - if (kvmppc_has_cap_htm() && pa_size > 24) { + if (spapr_has_cap(spapr, SPAPR_CAP_HTM) && pa_size > 24) { pa_features[24] |=3D 0x80; /* Transactional memory support */ } if (legacy_guest && pa_size > 40) { @@ -384,8 +386,8 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineSt= ate *spapr) return ret; } =20 - spapr_populate_pa_features(cpu, fdt, offset, - spapr->cas_legacy_guest_workaroun= d); + spapr_populate_pa_features(spapr, cpu, fdt, offset, + spapr->cas_legacy_guest_workaround); } return ret; } @@ -579,7 +581,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, page_sizes_prop, page_sizes_prop_size))); } =20 - spapr_populate_pa_features(cpu, fdt, offset, false); + spapr_populate_pa_features(spapr, cpu, fdt, offset, false); =20 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", cs->cpu_index / vcpus_per_socket))); @@ -3903,7 +3905,10 @@ static void spapr_machine_2_11_instance_options(Mach= ineState *machine) =20 static void spapr_machine_2_11_class_options(MachineClass *mc) { + sPAPRMachineClass *smc =3D SPAPR_MACHINE_CLASS(mc); + spapr_machine_2_12_class_options(mc); + smc->default_caps =3D spapr_caps(SPAPR_CAP_HTM); SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); } =20 diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 968ba7b857..3b35b91a5b 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -24,6 +24,10 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "sysemu/hw_accel.h" +#include "target/ppc/cpu.h" +#include "cpu-models.h" +#include "kvm_ppc.h" =20 #include "hw/ppc/spapr.h" =20 @@ -40,18 +44,41 @@ typedef struct sPAPRCapabilityInfo { void (*disallow)(sPAPRMachineState *spapr, Error **errp); } sPAPRCapabilityInfo; =20 +static void cap_htm_allow(sPAPRMachineState *spapr, Error **errp) +{ + if (tcg_enabled()) { + error_setg(errp, + "No Transactional Memory support in TCG, try cap-htm=3D= off"); + } else if (kvm_enabled() && !kvmppc_has_cap_htm()) { + error_setg(errp, +"KVM implementation does not support Transactional Memory, try cap-htm=3Do= ff" + ); + } +} + static sPAPRCapabilityInfo capability_table[] =3D { + { + .name =3D "htm", + .description =3D "Allow Hardware Transactional Memory (HTM)", + .flag =3D SPAPR_CAP_HTM, + .allow =3D cap_htm_allow, + /* TODO: add cap_htm_disallow */ + }, }; =20 static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr, CPUState *cs) { sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + PowerPCCPU *cpu =3D POWERPC_CPU(cs); sPAPRCapabilities caps; =20 caps =3D smc->default_caps; =20 - /* TODO: clamp according to cpu model */ + if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, + 0, spapr->max_compat_pvr)) { + caps.mask &=3D ~SPAPR_CAP_HTM; + } =20 return caps; } diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 5569caf1d4..dc64f4ebcb 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -54,6 +54,9 @@ typedef enum { * Capabilities */ =20 +/* Hardware Transactional Memory */ +#define SPAPR_CAP_HTM 0x0000000000000001ULL + typedef struct sPAPRCapabilities sPAPRCapabilities; struct sPAPRCapabilities { uint64_t mask; --=20 2.14.3