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[24.181.135.57]) by smtp.gmail.com with ESMTPSA id y7sm3875780pfe.48.2018.01.16.08.46.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Jan 2018 08:46:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6NsXEr3flB7sBkwFuqOd8m3pcuQPwR79IBEPep8/0tE=; b=UT1akP8bizUIqvSYHFEZz4m66sGKbgh7LxXoRkqzy9tPfxXOyslibJdlwh/PKpL0Lt iF98IGrg87bDOiZHBZfitmnzppPur3SCjMU36TksQn5LtSuKipNPgE5SzFnl4H/NY7mZ FR14aNnTMsQ4AeinjaCYpqUZUKTyZQ+BDZl1o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6NsXEr3flB7sBkwFuqOd8m3pcuQPwR79IBEPep8/0tE=; b=OKmqiV/uHxBazk+83o2+Igg+bMwbMjaivbgj76Z3G8EMdrsmprmgYvIuVKccVeBHXl GStya8m/ibbegPpfQFmlLKPwZP4kBxNUovg/PgvPUtNFYk5E37dj1FrZFg8+tjf/ab1d PskTu0u5FkInaHSbC/ZfRPO1Ew3JNgI8aY23vyeaGVb6oaCgq2jwts4eHF0S7SUphdqJ MNTEcB4bsq5OLMiQDXppfkGXt7uepB6xps0sBlEgoU1BwD5EfBx/iyc0oUT/up4YNUIL 8NMxhcNWjo+vTrh0lzTuFon9hWw93mdZW7O5MhGsRwogq2ZSc5A3/bcEWaUlvZ737zFo JHAw== X-Gm-Message-State: AKGB3mIXGnYGrtrDMRoDmuihUYwNIQiar59A+38vPYLKxamPT6xrp4Iz AtoZJ3ODFaCd7IwQsOUpCNiF98lPFrU= X-Google-Smtp-Source: ACJfBosvO8HpYBy0gXCJPSbZ9EJCS44av9xXwxcxvnoJz+3qfGdkFYltRXJBlX79RVhhVVF5qNqiPg== X-Received: by 10.99.97.69 with SMTP id v66mr28033366pgb.307.1516121165075; Tue, 16 Jan 2018 08:46:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Jan 2018 08:45:57 -0800 Message-Id: <20180116164600.7480-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180116164600.7480-1-richard.henderson@linaro.org> References: <20180116164600.7480-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL v2 1/4] tcg/arm: Fix double-word comparisons X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The code sequence we were generating was only good for unsigned comparisons. For signed comparisions, use the sequence from gcc. Fixes booting of ppc64 firmware, with a patch changing the code sequence for ppc comparisons. Tested-by: Michael Roth Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 86 +++++++++++++++++++++++++++++++++-----------= ---- 1 file changed, 60 insertions(+), 26 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 98a12535a5..d7b09e8e0c 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1103,6 +1103,56 @@ static inline void tcg_out_mb(TCGContext *s, TCGArg = a0) } } =20 +static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, + const int *const_args) +{ + TCGReg al =3D args[0]; + TCGReg ah =3D args[1]; + TCGArg bl =3D args[2]; + TCGArg bh =3D args[3]; + TCGCond cond =3D args[4]; + int const_bl =3D const_args[2]; + int const_bh =3D const_args[3]; + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_NE: + case TCG_COND_LTU: + case TCG_COND_LEU: + case TCG_COND_GTU: + case TCG_COND_GEU: + /* We perform a conditional comparision. If the high half is + equal, then overwrite the flags with the comparison of the + low half. The resulting flags cover the whole. */ + tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); + tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); + return cond; + + case TCG_COND_LT: + case TCG_COND_GE: + /* We perform a double-word subtraction and examine the result. + We do not actually need the result of the subtract, so the + low part "subtract" is a compare. For the high half we have + no choice but to compute into a temporary. */ + tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); + tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, + TCG_REG_TMP, ah, bh, const_bh); + return cond; + + case TCG_COND_LE: + case TCG_COND_GT: + /* Similar, but with swapped arguments, via reversed subtract. */ + tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, + TCG_REG_TMP, al, bl, const_bl); + tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, + TCG_REG_TMP, ah, bh, const_bh); + return tcg_swap_cond(cond); + + default: + g_assert_not_reached(); + } +} + #ifdef CONFIG_SOFTMMU #include "tcg-ldst.inc.c" =20 @@ -1964,22 +2014,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], arg_label(args[3])); break; - case INDEX_op_brcond2_i32: - /* The resulting conditions are: - * TCG_COND_EQ --> a0 =3D=3D a2 && a1 =3D=3D a3, - * TCG_COND_NE --> (a0 !=3D a2 && a1 =3D=3D a3) || a1 !=3D a3, - * TCG_COND_LT(U) --> (a0 < a2 && a1 =3D=3D a3) || a1 < a3, - * TCG_COND_GE(U) --> (a0 >=3D a2 && a1 =3D=3D a3) || (a1 >=3D a3 = && a1 !=3D a3), - * TCG_COND_LE(U) --> (a0 <=3D a2 && a1 =3D=3D a3) || (a1 <=3D a3 = && a1 !=3D a3), - * TCG_COND_GT(U) --> (a0 > a2 && a1 =3D=3D a3) || a1 > a3, - */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[3], const_args[3]); - tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, - args[0], args[2], const_args[2]); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], - arg_label(args[5])); - break; case INDEX_op_setcond_i32: tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, args[1], args[2], const_args[2]); @@ -1988,15 +2022,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], ARITH_MOV, args[0], 0, 0); break; + + case INDEX_op_brcond2_i32: + c =3D tcg_out_cmp2(s, args, const_args); + tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); + break; case INDEX_op_setcond2_i32: - /* See brcond2_i32 comment */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[2], args[4], const_args[4]); - tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, - args[1], args[3], const_args[3]); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]], - ARITH_MOV, args[0], 0, 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])], + c =3D tcg_out_cmp2(s, args + 1, const_args + 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0,= 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], ARITH_MOV, args[0], 0, 0); break; =20 @@ -2093,9 +2127,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef sub2 =3D { .args_ct_str =3D { "r", "r", "rI", "rI", "rIN", "rIK" } }; static const TCGTargetOpDef br2 - =3D { .args_ct_str =3D { "r", "r", "rIN", "rIN" } }; + =3D { .args_ct_str =3D { "r", "r", "rI", "rI" } }; static const TCGTargetOpDef setc2 - =3D { .args_ct_str =3D { "r", "r", "r", "rIN", "rIN" } }; + =3D { .args_ct_str =3D { "r", "r", "r", "rI", "rI" } }; =20 switch (op) { case INDEX_op_goto_ptr: --=20 2.14.3