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[24.181.135.63]) by smtp.gmail.com with ESMTPSA id z19sm1139528pfh.185.2018.01.15.19.45.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Jan 2018 19:45:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kcgN9QYcD//AttPkT0aCUwSVYh6TH6r/0nhC8YAp0oU=; b=Pkp8cJBokYpTrsfpV+xgsLDuYKdlh3EFumUXJOSzCHcUBMG9k5KGrQvSYvVlyMjqcV /YDUBhGJUwQet0SJs0mXwxnfZ1lcCQXNorvV/C0HxpVrobShNtyWWOV1MOuui4WvtOcH fFcZyL3fep6Sq6x7I6up1Wq24paEcVp+sM8Lw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kcgN9QYcD//AttPkT0aCUwSVYh6TH6r/0nhC8YAp0oU=; b=tYmPM9cRBbnP+Q1sPAy/OJVNPXV7Xswq6FK13txARATdp76kWa3ZEE0XPSmIYg6Sk/ TBSy5zVF6GezgS7PXNQXRlG/8jzQJaz4MKcNv7PY64FD2L07pU9gfqjrmyIcaxVxAT4r IH4wTELB7xqTXitQC58bZqOwds6Xfp9z8jfz3P8eF2NypkLhy+L8MF8/qr+pXP1RzPns O1xeEDhhqBXeNaaL11laEJoFE+DP9Vq2bYZb3ussoaDqDV1jGCCnc5Ltoa4+9NWW/eWo DzZ//sWvjqRxPVT3Pv/B1+u7tpUzk+0REBwre5ocxW2IwWQTZBuw+pysBMowoSEhMF1K lRWg== X-Gm-Message-State: AKGB3mKG0HKZ0iwZIiJtLzJO8hTgob+8zfGad9qpaaXuf9dJED2ZtJbO Kn4QB1MY3wNCXssoujOE2HvZrhlt2gE= X-Google-Smtp-Source: ACJfBoueSzXBbkVlJjOpIJouOjfLGsUQKSslKubVMBA4ol2s9Kek7yaPr5Zz4QR9EYTeixUR/H6rBQ== X-Received: by 10.159.252.197 with SMTP id o5mr26434311pls.67.1516074312100; Mon, 15 Jan 2018 19:45:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 15 Jan 2018 19:45:03 -0800 Message-Id: <20180116034503.31926-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180116034503.31926-1-richard.henderson@linaro.org> References: <20180116034503.31926-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v2 2/4] tcg/arm: Support tlb offsets larger than 64k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" AArch64 with SVE has an offset of 80k to the 8th TLB. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 0ff283d84f..8f5d4f208d 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1246,12 +1246,6 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGRe= g argreg, /* We're expecting to use an 8-bit immediate and to mask. */ QEMU_BUILD_BUG_ON(CPU_TLB_BITS > 8); =20 -/* We're expecting to use an 8-bit immediate add + 8-bit ldrd offset. - Using the offset of the second entry in the last tlb table ensures - that we can index all of the elements of the first entry. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1]) - > 0xffff); - /* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ =20 @@ -1264,6 +1258,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addrlo, TCGReg addrhi, ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write)); int add_off =3D offsetof(CPUArchState, tlb_table[mem_index][0].addend); + int mask_off; unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 @@ -1295,16 +1290,25 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); } =20 - /* We checked that the offset is contained within 16 bits above. */ - if (add_off > 0xfff - || (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64 - && cmp_off > 0xff)) { + /* Add portions of the offset until the memory access is in range. + * If we plan on using ldrd, reduce to an 8-bit offset; otherwise + * we can use a 12-bit offset. */ + if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + mask_off =3D 0xff; + } else { + mask_off =3D 0xfff; + } + while (cmp_off > mask_off) { + int shift =3D ctz32(cmp_off & ~mask_off) & ~1; + int rot =3D ((32 - shift) << 7) & 0xf00; + int addend =3D cmp_off & (0xff << shift); tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, - (24 << 7) | (cmp_off >> 8)); + rot | ((cmp_off >> shift) & 0xff)); base =3D TCG_REG_R2; - add_off -=3D cmp_off & 0xff00; - cmp_off &=3D 0xff; + add_off -=3D addend; + cmp_off -=3D addend; } + if (!use_armv7_instructions) { tcg_out_dat_imm(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); --=20 2.14.3