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[24.181.135.57]) by smtp.gmail.com with ESMTPSA id c83sm1281024pfk.8.2018.01.15.19.34.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Jan 2018 19:34:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sXpbyqdhU7j6nERUHaLNt/wQal1xOlPV2LvWC6p16Nk=; b=HSqfn9ZeIzyUrIE+eKuWOrvTq9y1nb08uDRmjByzSi1w1J/mv7jq1YwKdN8Ufrn0+p 9QqvXRi28DfI4x37QnF8t45uIk1Oni2eqJ1fTLMsUhuYfxcxypxyxPbfTSRqTnEDNybV IJtfm33h0/sxO4rpqikGiP/6cd7x90kjXUmyQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sXpbyqdhU7j6nERUHaLNt/wQal1xOlPV2LvWC6p16Nk=; b=cgMc4joO1q2LCHU3x60w3ZSGYMPMSHtjjwHzR1HgKx5Wwwx3doT5lQzXahVJET4JvV iyFnqeiL+lAREzMOnK6BurHq3a/HuRh5r3rSKVu1u9QqaXVPeIDSNQlFNjghh5UufDn/ UIcxad9okLJomI/Onhm4+RZQ2oLBH7hRW9JaysUqyoLMeqsHPkGqMdf/SiASpqtOmZex OdFdOJumG+S8+b0wrEPHw3Eo4xgGHrBQw1DYx1irWhcLg+gjJs8RNATxA3/basK0J1kY OJ6ldno+Z2XIDT1yHIghpx+eupXBt92d9+BbCuuhDrFckweJCHJcmKN9IXCYw+X8NRtm RO0g== X-Gm-Message-State: AKwxytdlp7jepopIjruVPQo6AjRpJ1s4EjMWfdkzmstRtkChNQCut3fE VK0+I87dTj8/lI/aFbI9sivJAnv1B0g= X-Google-Smtp-Source: ACJfBotvBrG5q/5F+2aunNGv1DyxIPr1axm0cZ3PMyt0HtXeHboGj5fwahlx6sCaha+s0RRsoOew3g== X-Received: by 10.99.113.20 with SMTP id m20mr17133962pgc.400.1516073681041; Mon, 15 Jan 2018 19:34:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 15 Jan 2018 19:33:49 -0800 Message-Id: <20180116033404.31532-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180116033404.31532-1-richard.henderson@linaro.org> References: <20180116033404.31532-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v9 11/26] tcg: Loosen vec_gen_op* typecheck rules X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For ARM SVE with VQ=3D3, we want to be able to dup a scalar into a v256, use that, and then perform a second operation with the v256 punned to a v128. Allow operands to a vector operation be wider than necessary for the output. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index a73d094ddb..ad9a45b653 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -78,7 +78,7 @@ static void vec_gen_op2(TCGOpcode opc, unsigned vece, TCG= v_vec r, TCGv_vec a) TCGTemp *at =3D tcgv_vec_temp(a); TCGType type =3D rt->base_type; =20 - tcg_debug_assert(at->base_type =3D=3D type); + tcg_debug_assert(at->base_type >=3D type); vec_gen_2(opc, type, vece, temp_arg(rt), temp_arg(at)); } =20 @@ -90,8 +90,8 @@ static void vec_gen_op3(TCGOpcode opc, unsigned vece, TCGTemp *bt =3D tcgv_vec_temp(b); TCGType type =3D rt->base_type; =20 - tcg_debug_assert(at->base_type =3D=3D type); - tcg_debug_assert(bt->base_type =3D=3D type); + tcg_debug_assert(at->base_type >=3D type); + tcg_debug_assert(bt->base_type >=3D type); vec_gen_3(opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt)); } =20 @@ -257,14 +257,14 @@ void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, T= CGv_i64 a) =20 if (TCG_TARGET_REG_BITS =3D=3D 64) { TCGArg ai =3D tcgv_i64_arg(a); - vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai); + vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } else if (vece =3D=3D MO_64) { TCGArg al =3D tcgv_i32_arg(TCGV_LOW(a)); TCGArg ah =3D tcgv_i32_arg(TCGV_HIGH(a)); vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah); } else { TCGArg ai =3D tcgv_i32_arg(TCGV_LOW(a)); - vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai); + vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } } =20 @@ -493,8 +493,8 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGType type =3D rt->base_type; int can; =20 - tcg_debug_assert(at->base_type =3D=3D type); - tcg_debug_assert(bt->base_type =3D=3D type); + tcg_debug_assert(at->base_type >=3D type); + tcg_debug_assert(bt->base_type >=3D type); can =3D tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece); if (can > 0) { vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond); @@ -515,8 +515,8 @@ void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_ve= c a, TCGv_vec b) TCGType type =3D rt->base_type; int can; =20 - tcg_debug_assert(at->base_type =3D=3D type); - tcg_debug_assert(bt->base_type =3D=3D type); + tcg_debug_assert(at->base_type >=3D type); + tcg_debug_assert(bt->base_type >=3D type); can =3D tcg_can_emit_vec_op(INDEX_op_mul_vec, type, vece); if (can > 0) { vec_gen_3(INDEX_op_mul_vec, type, vece, ri, ai, bi); --=20 2.14.3