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X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v4 08/14] i.MX: Add implementation of i.MX7 GPR IP block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrey Smirnov , Jason Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daud=C3=A9 Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/Makefile.objs | 1 + hw/misc/imx7_gpr.c | 119 +++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/imx7_gpr.h | 28 +++++++++++ 3 files changed, 148 insertions(+) create mode 100644 hw/misc/imx7_gpr.c create mode 100644 include/hw/misc/imx7_gpr.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 019886912c..fce426eb75 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -36,6 +36,7 @@ obj-$(CONFIG_IMX) +=3D imx6_src.o obj-$(CONFIG_IMX) +=3D imx7_ccm.o obj-$(CONFIG_IMX) +=3D imx2_wdt.o obj-$(CONFIG_IMX) +=3D imx7_snvs.o +obj-$(CONFIG_IMX) +=3D imx7_gpr.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-hpdmc.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-pfpu.o obj-$(CONFIG_MAINSTONE) +=3D mst_fpga.o diff --git a/hw/misc/imx7_gpr.c b/hw/misc/imx7_gpr.c new file mode 100644 index 0000000000..9e8ccea9e8 --- /dev/null +++ b/hw/misc/imx7_gpr.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 GPR IP block emulation code + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + * Bare minimum emulation code needed to support being able to shut + * down linux guest gracefully. + */ + +#include "qemu/osdep.h" +#include "hw/misc/imx7_gpr.h" +#include "qemu/log.h" +#include "sysemu/sysemu.h" + +enum IMX7GPRRegisters { + IOMUXC_GPR0 =3D 0x00, + IOMUXC_GPR1 =3D 0x04, + IOMUXC_GPR2 =3D 0x08, + IOMUXC_GPR3 =3D 0x0c, + IOMUXC_GPR4 =3D 0x10, + IOMUXC_GPR5 =3D 0x14, + IOMUXC_GPR6 =3D 0x18, + IOMUXC_GPR7 =3D 0x1c, + IOMUXC_GPR8 =3D 0x20, + IOMUXC_GPR9 =3D 0x24, + IOMUXC_GPR10 =3D 0x28, + IOMUXC_GPR11 =3D 0x2c, + IOMUXC_GPR12 =3D 0x30, + IOMUXC_GPR13 =3D 0x34, + IOMUXC_GPR14 =3D 0x38, + IOMUXC_GPR15 =3D 0x3c, + IOMUXC_GPR16 =3D 0x40, + IOMUXC_GPR17 =3D 0x44, + IOMUXC_GPR18 =3D 0x48, + IOMUXC_GPR19 =3D 0x4c, + IOMUXC_GPR20 =3D 0x50, + IOMUXC_GPR21 =3D 0x54, + IOMUXC_GPR22 =3D 0x58, +}; + +#define IMX7D_GPR1_IRQ_MASK BIT(12) +#define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK BIT(13) +#define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK BIT(14) +#define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13) +#define IMX7D_GPR1_ENET1_CLK_DIR_MASK BIT(17) +#define IMX7D_GPR1_ENET2_CLK_DIR_MASK BIT(18) +#define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17) + +#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI BIT(4) +#define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5) +#define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31) + + +static uint64_t imx7_gpr_read(void *opaque, hwaddr offset, unsigned size) +{ + if (offset =3D=3D IOMUXC_GPR22) { + return IMX7D_GPR22_PCIE_PHY_PLL_LOCKED; + } + + return 0; +} + +static void imx7_gpr_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ +} + +static const struct MemoryRegionOps imx7_gpr_ops =3D { + .read =3D imx7_gpr_read, + .write =3D imx7_gpr_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + /* + * Our device would not work correctly if the guest was doing + * unaligned access. This might not be a limitation on the + * real device but in practice there is no reason for a guest + * to access this device unaligned. + */ + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void imx7_gpr_init(Object *obj) +{ + SysBusDevice *sd =3D SYS_BUS_DEVICE(obj); + IMX7GPRState *s =3D IMX7_GPR(obj); + + memory_region_init_io(&s->mmio, obj, &imx7_gpr_ops, s, + TYPE_IMX7_GPR, 64 * 1024); + sysbus_init_mmio(sd, &s->mmio); +} + +static void imx7_gpr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "i.MX7 General Purpose Registers Module"; +} + +static const TypeInfo imx7_gpr_info =3D { + .name =3D TYPE_IMX7_GPR, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IMX7GPRState), + .instance_init =3D imx7_gpr_init, + .class_init =3D imx7_gpr_class_init, +}; + +static void imx7_gpr_register_type(void) +{ + type_register_static(&imx7_gpr_info); +} +type_init(imx7_gpr_register_type) diff --git a/include/hw/misc/imx7_gpr.h b/include/hw/misc/imx7_gpr.h new file mode 100644 index 0000000000..e19373d274 --- /dev/null +++ b/include/hw/misc/imx7_gpr.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 GPR IP block emulation code + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef IMX7_GPR_H +#define IMX7_GPR_H + +#include "qemu/bitops.h" +#include "hw/sysbus.h" + +#define TYPE_IMX7_GPR "imx7.gpr" +#define IMX7_GPR(obj) OBJECT_CHECK(IMX7GPRState, (obj), TYPE_IMX7_GPR) + +typedef struct IMX7GPRState { + /* */ + SysBusDevice parent_obj; + + MemoryRegion mmio; +} IMX7GPRState; + +#endif /* IMX7_GPR_H */ --=20 2.14.3