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X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v8 11/14] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , Andrey Smirnov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, Kevin O'Connor , Marcel Apfelbaum Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 running qtests: $ make check-qtest-arm GTESTER check-qtest-arm SDHC rd_4b @0x44 not implemented SDHC wr_4b @0x40 <- 0x89abcdef not implemented SDHC wr_4b @0x44 <- 0x01234567 not implemented Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- include/hw/sd/sdhci.h | 4 ++-- hw/sd/sdhci.c | 23 +++++++++++++++++++---- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 8041c9629e..442e30aff2 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -72,8 +72,8 @@ typedef struct SDHCIState { uint64_t admasysaddr; /* ADMA System Address Register */ =20 /* Read-only registers */ - uint32_t capareg; /* Capabilities Register */ - uint32_t maxcurr; /* Maximum Current Capabilities Register */ + uint64_t capareg; /* Capabilities Register */ + uint64_t maxcurr; /* Maximum Current Capabilities Register */ =20 uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */ uint32_t buf_maxsz; diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index c4e486e2ff..d4fcebcd6a 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -899,10 +899,16 @@ static uint64_t sdhci_read(void *opaque, hwaddr offse= t, unsigned size) ret =3D s->acmd12errsts; break; case SDHC_CAPAB: - ret =3D s->capareg; + ret =3D (uint32_t)s->capareg; + break; + case SDHC_CAPAB + 4: + ret =3D (uint32_t)(s->capareg >> 32); break; case SDHC_MAXCURR: - ret =3D s->maxcurr; + ret =3D (uint32_t)s->maxcurr; + break; + case SDHC_MAXCURR + 4: + ret =3D (uint32_t)(s->maxcurr >> 32); break; case SDHC_ADMAERR: ret =3D s->admaerr; @@ -1123,6 +1129,15 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t va= l, unsigned size) } sdhci_update_irq(s); break; + + case SDHC_CAPAB: + case SDHC_CAPAB + 4: + case SDHC_MAXCURR: + case SDHC_MAXCURR + 4: + qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx + " <- 0x%08x read-only\n", size, offset, value >> shi= ft); + break; + default: qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%= 08x " "not implemented\n", size, offset, value >> shift); @@ -1163,8 +1178,8 @@ static inline unsigned int sdhci_get_fifolen(SDHCISta= te *s) #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ /* Capabilities registers provide information on supported features * of this specific host controller implementation */ \ - DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT)= , \ - DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0) + DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT)= , \ + DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0) =20 static void sdhci_initfn(SDHCIState *s) { --=20 2.15.1