From nobody Tue Feb 10 19:49:26 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515927056988485.4795171283739; Sun, 14 Jan 2018 02:50:56 -0800 (PST) Received: from localhost ([::1]:57422 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eafsJ-0000Zm-JI for importer@patchew.org; Sun, 14 Jan 2018 05:50:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41206) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eafqa-0007wx-M5 for qemu-devel@nongnu.org; Sun, 14 Jan 2018 05:49:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eafqY-0000s4-Rl for qemu-devel@nongnu.org; Sun, 14 Jan 2018 05:49:04 -0500 Received: from chuckie.co.uk ([82.165.15.123]:41895 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eafqY-0000gJ-Hd for qemu-devel@nongnu.org; Sun, 14 Jan 2018 05:49:02 -0500 Received: from host86-191-132-7.range86-191.btcentralplus.com ([86.191.132.7] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1eafqZ-0000Uc-K7; Sun, 14 Jan 2018 10:49:05 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 14 Jan 2018 10:47:41 +0000 Message-Id: <20180114104751.21965-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180114104751.21965-1-mark.cave-ayland@ilande.co.uk> References: <20180114104751.21965-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.191.132.7 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 01/11] apb: split simba PCI bridge into hw/pci-bridge/simba.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcel Apfelbaum , Mark Cave-Ayland , "Michael S . Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the QOM type and macros into a new include/hw/pci-bridge/simba.h file, and add a new CONFIG_SIMBA Makefile.objs variable which is enabled for sparc64-softmmu builds only. Signed-off-by: Mark Cave-Ayland CC: Michael S. Tsirkin CC: Marcel Apfelbaum Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- default-configs/sparc64-softmmu.mak | 1 + hw/pci-bridge/Makefile.objs | 2 + hw/pci-bridge/simba.c | 101 ++++++++++++++++++++++++++++++++= ++++ hw/pci-host/apb.c | 62 +--------------------- include/hw/pci-bridge/simba.h | 38 ++++++++++++++ include/hw/pci-host/apb.h | 9 ---- 6 files changed, 143 insertions(+), 70 deletions(-) create mode 100644 hw/pci-bridge/simba.c create mode 100644 include/hw/pci-bridge/simba.h diff --git a/default-configs/sparc64-softmmu.mak b/default-configs/sparc64-= softmmu.mak index 3e177bbd7b..9b742a7b41 100644 --- a/default-configs/sparc64-softmmu.mak +++ b/default-configs/sparc64-softmmu.mak @@ -12,6 +12,7 @@ CONFIG_FDC=3Dy CONFIG_IDE_ISA=3Dy CONFIG_IDE_CMD646=3Dy CONFIG_PCI_APB=3Dy +CONFIG_SIMBA=3Dy CONFIG_SUNHME=3Dy CONFIG_MC146818RTC=3Dy CONFIG_ISA_TESTDEV=3Dy diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs index 1b05023662..47065f87d9 100644 --- a/hw/pci-bridge/Makefile.objs +++ b/hw/pci-bridge/Makefile.objs @@ -6,3 +6,5 @@ common-obj-$(CONFIG_IOH3420) +=3D ioh3420.o common-obj-$(CONFIG_I82801B11) +=3D i82801b11.o # NewWorld PowerMac common-obj-$(CONFIG_DEC_PCI) +=3D dec.o +# Sun4u +common-obj-$(CONFIG_SIMBA) +=3D simba.o diff --git a/hw/pci-bridge/simba.c b/hw/pci-bridge/simba.c new file mode 100644 index 0000000000..05ba6f0f34 --- /dev/null +++ b/hw/pci-bridge/simba.c @@ -0,0 +1,101 @@ +/* + * QEMU Simba PCI bridge + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2018 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci-bridge/simba.h" + +/* + * Chipset docs: + * APB: "Advanced PCI Bridge (APB) User's Manual", + * http://www.sun.com/processors/manuals/805-1251.pdf + */ + +static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) +{ + /* + * command register: + * According to PCI bridge spec, after reset + * bus master bit is off + * memory space enable bit is off + * According to manual (805-1251.pdf). + * the reset value should be zero unless the boot pin is tied high + * (which is true) and thus it should be PCI_COMMAND_MEMORY. + */ + PBMPCIBridge *br =3D PBM_PCI_BRIDGE(dev); + + pci_bridge_initfn(dev, TYPE_PCI_BUS); + + pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_set_word(dev->config + PCI_STATUS, + PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | + PCI_STATUS_DEVSEL_MEDIUM); + + /* Allow 32-bit IO addresses */ + pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32); + pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32); + pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff); + pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff); + + pci_bridge_update_mappings(PCI_BRIDGE(br)); +} + +static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D apb_pci_bridge_realize; + k->exit =3D pci_bridge_exitfn; + k->vendor_id =3D PCI_VENDOR_ID_SUN; + k->device_id =3D PCI_DEVICE_ID_SUN_SIMBA; + k->revision =3D 0x11; + k->config_write =3D pci_bridge_write_config; + k->is_bridge =3D 1; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + dc->reset =3D pci_bridge_reset; + dc->vmsd =3D &vmstate_pci_device; +} + +static const TypeInfo pbm_pci_bridge_info =3D { + .name =3D TYPE_PBM_PCI_BRIDGE, + .parent =3D TYPE_PCI_BRIDGE, + .class_init =3D pbm_pci_bridge_class_init, + .instance_size =3D sizeof(PBMPCIBridge), + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + +static void pbm_register_types(void) +{ + type_register_static(&pbm_pci_bridge_info); +} + +type_init(pbm_register_types) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index ec676f94b6..3a5c046794 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -33,6 +33,7 @@ #include "hw/pci/pci_host.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" +#include "hw/pci-bridge/simba.h" #include "hw/pci-host/apb.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" @@ -53,9 +54,6 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) * Chipset docs: * PBM: "UltraSPARC IIi User's Manual", * http://www.sun.com/processors/manuals/805-0087.pdf - * - * APB: "Advanced PCI Bridge (APB) User's Manual", - * http://www.sun.com/processors/manuals/805-1251.pdf */ =20 #define PBM_PCI_IMR_MASK 0x7fffffff @@ -348,35 +346,6 @@ static void pci_apb_set_irq(void *opaque, int irq_num,= int level) } } =20 -static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) -{ - /* - * command register: - * According to PCI bridge spec, after reset - * bus master bit is off - * memory space enable bit is off - * According to manual (805-1251.pdf). - * the reset value should be zero unless the boot pin is tied high - * (which is true) and thus it should be PCI_COMMAND_MEMORY. - */ - PBMPCIBridge *br =3D PBM_PCI_BRIDGE(dev); - - pci_bridge_initfn(dev, TYPE_PCI_BUS); - - pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY); - pci_set_word(dev->config + PCI_STATUS, - PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | - PCI_STATUS_DEVSEL_MEDIUM); - - /* Allow 32-bit IO addresses */ - pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32); - pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32); - pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff); - pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff); - - pci_bridge_update_mappings(PCI_BRIDGE(br)); -} - static void pci_pbm_reset(DeviceState *d) { APBState *s =3D APB_DEVICE(d); @@ -564,39 +533,10 @@ static const TypeInfo pbm_host_info =3D { .class_init =3D pbm_host_class_init, }; =20 -static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); - - k->realize =3D apb_pci_bridge_realize; - k->exit =3D pci_bridge_exitfn; - k->vendor_id =3D PCI_VENDOR_ID_SUN; - k->device_id =3D PCI_DEVICE_ID_SUN_SIMBA; - k->revision =3D 0x11; - k->config_write =3D pci_bridge_write_config; - k->is_bridge =3D 1; - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->reset =3D pci_bridge_reset; - dc->vmsd =3D &vmstate_pci_device; -} - -static const TypeInfo pbm_pci_bridge_info =3D { - .name =3D TYPE_PBM_PCI_BRIDGE, - .parent =3D TYPE_PCI_BRIDGE, - .class_init =3D pbm_pci_bridge_class_init, - .instance_size =3D sizeof(PBMPCIBridge), - .interfaces =3D (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, -}; - static void pbm_register_types(void) { type_register_static(&pbm_host_info); type_register_static(&pbm_pci_host_info); - type_register_static(&pbm_pci_bridge_info); } =20 type_init(pbm_register_types) diff --git a/include/hw/pci-bridge/simba.h b/include/hw/pci-bridge/simba.h new file mode 100644 index 0000000000..5ab1330236 --- /dev/null +++ b/include/hw/pci-bridge/simba.h @@ -0,0 +1,38 @@ +/* + * QEMU Simba PCI bridge + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2017 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci_bridge.h" + + +typedef struct PBMPCIBridge { + /*< private >*/ + PCIBridge parent_obj; +} PBMPCIBridge; + +#define TYPE_PBM_PCI_BRIDGE "pbm-bridge" +#define PBM_PCI_BRIDGE(obj) \ + OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 604d899b1e..5e28f3e1f3 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -42,13 +42,4 @@ typedef struct APBState { unsigned int nr_resets; } APBState; =20 -typedef struct PBMPCIBridge { - /*< private >*/ - PCIBridge parent_obj; -} PBMPCIBridge; - -#define TYPE_PBM_PCI_BRIDGE "pbm-bridge" -#define PBM_PCI_BRIDGE(obj) \ - OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) - #endif --=20 2.11.0